Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/contrib/device-tree/src/arm/imx6ul-ccimx6ulsbcpro.dts
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1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Digi International's ConnectCore6UL SBC Pro board device tree source 4 * 5 * Copyright 2018 Digi International, Inc. 6 * 7 */ 8 9 /dts-v1/; 10 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include "imx6ul.dtsi" 13 #include "imx6ul-ccimx6ulsom.dtsi" 14 15 / { 16 model = "Digi International ConnectCore 6UL SBC Pro."; 17 compatible = "digi,ccimx6ulsbcpro", "digi,ccimx6ulsom", "fsl,imx6ul"; 18 19 lcd_backlight: backlight { 20 compatible = "pwm-backlight"; 21 pwms = <&pwm5 0 50000>; 22 brightness-levels = <0 4 8 16 32 64 128 255>; 23 default-brightness-level = <6>; 24 status = "okay"; 25 }; 26 27 panel { 28 compatible = "auo,g101evn010"; 29 power-supply = <&ldo4_ext>; 30 backlight = <&lcd_backlight>; 31 32 port { 33 panel_in: endpoint { 34 remote-endpoint = <&display_out>; 35 }; 36 }; 37 }; 38 39 reg_usb_otg1_vbus: regulator-usb-otg1 { 40 compatible = "regulator-fixed"; 41 regulator-name = "usb_otg1_vbus"; 42 regulator-min-microvolt = <5000000>; 43 regulator-max-microvolt = <5000000>; 44 gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; 45 enable-active-high; 46 }; 47 }; 48 49 &adc1 { 50 pinctrl-names = "default"; 51 pinctrl-0 = <&pinctrl_adc1>; 52 status = "okay"; 53 }; 54 55 &can1 { 56 pinctrl-names = "default"; 57 pinctrl-0 = <&pinctrl_flexcan1>; 58 xceiver-supply = <&ext_3v3>; 59 status = "okay"; 60 }; 61 62 /* CAN2 is multiplexed with UART2 RTS/CTS */ 63 &can2 { 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pinctrl_flexcan2>; 66 xceiver-supply = <&ext_3v3>; 67 status = "disabled"; 68 }; 69 70 &ecspi1 { 71 cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; 72 pinctrl-names = "default"; 73 pinctrl-0 = <&pinctrl_ecspi1_master>; 74 status = "okay"; 75 }; 76 77 &fec1 { 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pinctrl_enet1>; 80 phy-mode = "rmii"; 81 phy-handle = <ðphy0>; 82 status = "okay"; 83 }; 84 85 &fec2 { 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; 88 phy-mode = "rmii"; 89 phy-handle = <ðphy1>; 90 phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; 91 phy-reset-duration = <26>; 92 status = "okay"; 93 94 mdio { 95 #address-cells = <1>; 96 #size-cells = <0>; 97 98 ethphy0: ethernet-phy@0 { 99 compatible = "ethernet-phy-ieee802.3-c22"; 100 smsc,disable-energy-detect; 101 reg = <0>; 102 }; 103 104 ethphy1: ethernet-phy@1 { 105 compatible = "ethernet-phy-ieee802.3-c22"; 106 smsc,disable-energy-detect; 107 reg = <1>; 108 }; 109 }; 110 }; 111 112 &gpio5 { 113 emmc-usd-mux-hog { 114 gpio-hog; 115 gpios = <1 GPIO_ACTIVE_LOW>; 116 output-high; 117 }; 118 }; 119 120 &i2c1 { 121 touchscreen@14 { 122 compatible = "goodix,gt911"; 123 reg = <0x14>; 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_goodix_touch>; 126 interrupt-parent = <&gpio5>; 127 interrupts = <2 IRQ_TYPE_EDGE_RISING>; 128 irq-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; 129 status = "okay"; 130 }; 131 }; 132 133 &lcdif { 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_lcdif_dat0_17 136 &pinctrl_lcdif_clken 137 &pinctrl_lcdif_hvsync>; 138 lcd-supply = <&ldo4_ext>; /* BU90T82 LVDS bridge power */ 139 status = "okay"; 140 141 port { 142 display_out: endpoint { 143 remote-endpoint = <&panel_in>; 144 }; 145 }; 146 }; 147 148 &ldo4_ext { 149 regulator-max-microvolt = <1800000>; 150 }; 151 152 &pwm1 { 153 status = "okay"; 154 }; 155 156 &pwm2 { 157 status = "okay"; 158 }; 159 160 &pwm3 { 161 status = "okay"; 162 }; 163 164 &pwm4 { 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_pwm4>; 167 status = "okay"; 168 }; 169 170 &pwm5 { 171 #pwm-cells = <2>; 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_pwm5>; 174 status = "okay"; 175 }; 176 177 &pwm6 { 178 status = "okay"; 179 }; 180 181 &pwm7 { 182 status = "okay"; 183 }; 184 185 &pwm8 { 186 status = "okay"; 187 }; 188 189 &sai2 { 190 pinctrl-names = "default", "sleep"; 191 pinctrl-0 = <&pinctrl_sai2>; 192 pinctrl-1 = <&pinctrl_sai2_sleep>; 193 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, 194 <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>, 195 <&clks IMX6UL_CLK_SAI2>; 196 assigned-clock-rates = <0>, <786432000>, <12288000>; 197 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 198 status = "okay"; 199 }; 200 201 /* UART2 RTS/CTS muxed with CAN2 */ 202 &uart2 { 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_uart2_4wires>; 205 uart-has-rtscts; 206 status = "okay"; 207 }; 208 209 /* UART3 RTS/CTS muxed with CAN 1 */ 210 &uart3 { 211 pinctrl-names = "default"; 212 pinctrl-0 = <&pinctrl_uart3_2wires>; 213 status = "okay"; 214 }; 215 216 &uart5 { 217 pinctrl-names = "default"; 218 pinctrl-0 = <&pinctrl_uart5>; 219 status = "okay"; 220 }; 221 222 &usbotg1 { 223 dr_mode = "otg"; 224 vbus-supply = <®_usb_otg1_vbus>; 225 pinctrl-0 = <&pinctrl_usbotg1>; 226 status = "okay"; 227 }; 228 229 &usbotg2 { 230 dr_mode = "host"; 231 disable-over-current; 232 status = "okay"; 233 }; 234 235 /* USDHC2 (microSD conflicts with eMMC) */ 236 &usdhc2 { 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinctrl_usdhc2>; 239 no-1-8-v; 240 broken-cd; /* no carrier detect line (use polling) */ 241 status = "okay"; 242 }; 243 244 &iomuxc { 245 pinctrl_adc1: adc1grp { 246 fsl,pins = < 247 /* EXP_GPIO_2 -> GPIO1_3/ADC1_IN3 */ 248 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 249 >; 250 }; 251 252 pinctrl_ecspi1_master: ecspi1grp1 { 253 fsl,pins = < 254 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x10b0 255 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x10b0 256 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x10b0 257 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 258 >; 259 }; 260 261 pinctrl_enet1: enet1grp { 262 fsl,pins = < 263 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 264 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 265 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 266 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 267 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 268 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 269 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 270 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051 271 >; 272 }; 273 274 pinctrl_enet2: enet2grp { 275 fsl,pins = < 276 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 277 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 278 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 279 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 280 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 281 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 282 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 283 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x40017051 284 >; 285 }; 286 287 pinctrl_enet2_mdio: mdioenet2grp { 288 fsl,pins = < 289 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 290 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 291 >; 292 }; 293 294 pinctrl_flexcan1: flexcan1grp{ 295 fsl,pins = < 296 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 297 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 298 >; 299 }; 300 pinctrl_flexcan2: flexcan2grp{ 301 fsl,pins = < 302 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 303 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 304 >; 305 }; 306 307 pinctrl_goodix_touch: goodixgrp{ 308 fsl,pins = < 309 MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1020 310 >; 311 }; 312 313 pinctrl_lcdif_dat0_17: lcdifdatgrp0-17 { 314 fsl,pins = < 315 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 316 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 317 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 318 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 319 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 320 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 321 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 322 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 323 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 324 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 325 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 326 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 327 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 328 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 329 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 330 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 331 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 332 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 333 >; 334 }; 335 336 pinctrl_lcdif_clken: lcdifctrlgrp1 { 337 fsl,pins = < 338 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x17050 339 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 340 >; 341 }; 342 343 pinctrl_lcdif_hvsync: lcdifctrlgrp2 { 344 fsl,pins = < 345 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 346 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 347 >; 348 }; 349 350 pinctrl_pwm4: pwm4grp { 351 fsl,pins = < 352 MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 353 >; 354 }; 355 356 pinctrl_pwm5: pwm5grp { 357 fsl,pins = < 358 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0 359 >; 360 }; 361 362 pinctrl_sai2: sai2grp { 363 fsl,pins = < 364 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 365 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 366 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 367 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 368 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 369 /* Interrupt */ 370 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10b0 371 >; 372 }; 373 374 pinctrl_sai2_sleep: sai2grp-sleep { 375 fsl,pins = < 376 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x3000 377 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x3000 378 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x3000 379 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x3000 380 /* Interrupt */ 381 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x3000 382 >; 383 }; 384 385 pinctrl_uart2_4wires: uart2grp-4wires { 386 fsl,pins = < 387 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 388 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 389 MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 390 MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 391 >; 392 }; 393 394 pinctrl_uart3_2wires: uart3grp-2wires { 395 fsl,pins = < 396 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 397 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 398 >; 399 }; 400 401 pinctrl_uart5: uart5grp { 402 fsl,pins = < 403 MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 404 MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 405 >; 406 }; 407 408 pinctrl_usdhc2: usdhc2grp { 409 fsl,pins = < 410 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 411 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10039 412 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 413 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 414 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 415 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 416 /* Mux selector between eMMC/SD# */ 417 MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x79 418 >; 419 }; 420 421 pinctrl_usbotg1: usbotg1grp { 422 fsl,pins = < 423 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 424 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x17059 425 MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x17059 426 >; 427 }; 428 };
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