Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx6ul-pico.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 // 3 // Copyright 2015 Technexion Ltd. 4 // 5 // Author: Wig Cheng <wig.cheng@technexion.com> 6 // Richard Hu <richard.hu@technexion.com> 7 // Tapani Utriainen <tapani@technexion.com> 8 /dts-v1/; 9 10 #include "imx6ul.dtsi" 11 12 / { 13 /* Will be filled by the bootloader */ 14 memory@80000000 { 15 device_type = "memory"; 16 reg = <0x80000000 0>; 17 }; 18 19 chosen { 20 stdout-path = &uart6; 21 }; 22 23 backlight: backlight { 24 compatible = "pwm-backlight"; 25 pwms = <&pwm3 0 5000000>; 26 brightness-levels = <0 4 8 16 32 64 128 255>; 27 default-brightness-level = <6>; 28 status = "okay"; 29 }; 30 31 reg_2p5v: regulator-2p5v { 32 compatible = "regulator-fixed"; 33 regulator-name = "2P5V"; 34 regulator-min-microvolt = <2500000>; 35 regulator-max-microvolt = <2500000>; 36 }; 37 38 reg_3p3v: regulator-3p3v { 39 compatible = "regulator-fixed"; 40 regulator-name = "3P3V"; 41 regulator-min-microvolt = <3300000>; 42 regulator-max-microvolt = <3300000>; 43 }; 44 45 reg_sd1_vmmc: regulator-sd1-vmmc { 46 compatible = "regulator-fixed"; 47 regulator-name = "VSD_3V3"; 48 regulator-min-microvolt = <3300000>; 49 regulator-max-microvolt = <3300000>; 50 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; 51 enable-active-high; 52 }; 53 54 reg_usb_otg_vbus: regulator-usb-otg-vbus { 55 compatible = "regulator-fixed"; 56 pinctrl-names = "default"; 57 pinctrl-0 = <&pinctrl_usb_otg1>; 58 regulator-name = "usb_otg_vbus"; 59 regulator-min-microvolt = <5000000>; 60 regulator-max-microvolt = <5000000>; 61 gpio = <&gpio1 6 0>; 62 }; 63 64 reg_brcm: regulator-brcm { 65 compatible = "regulator-fixed"; 66 enable-active-high; 67 gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; 68 pinctrl-names = "default"; 69 pinctrl-0 = <&pinctrl_brcm_reg>; 70 regulator-name = "brcm_reg"; 71 regulator-min-microvolt = <3300000>; 72 regulator-max-microvolt = <3300000>; 73 startup-delay-us = <200000>; 74 }; 75 76 panel { 77 compatible = "vxt,vl050-8048nt-c01"; 78 backlight = <&backlight>; 79 80 port { 81 panel_in: endpoint { 82 remote-endpoint = <&display_out>; 83 }; 84 }; 85 }; 86 }; 87 88 &can1 { 89 pinctrl-names = "default"; 90 pinctrl-0 = <&pinctrl_flexcan1>; 91 status = "okay"; 92 }; 93 94 &can2 { 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_flexcan2>; 97 status = "okay"; 98 }; 99 100 &clks { 101 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 102 assigned-clock-rates = <786432000>; 103 }; 104 105 &fec2 { 106 pinctrl-names = "default"; 107 pinctrl-0 = <&pinctrl_enet2>; 108 phy-mode = "rmii"; 109 phy-handle = <ðphy1>; 110 status = "okay"; 111 phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; 112 phy-reset-duration = <1>; 113 114 mdio { 115 #address-cells = <1>; 116 #size-cells = <0>; 117 118 ethphy1: ethernet-phy@1 { 119 compatible = "ethernet-phy-ieee802.3-c22"; 120 reg = <1>; 121 max-speed = <100>; 122 interrupt-parent = <&gpio5>; 123 interrupts = <6 IRQ_TYPE_LEVEL_LOW>; 124 }; 125 }; 126 }; 127 128 &i2c1 { 129 clock-frequency = <100000>; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_i2c1>; 132 status = "okay"; 133 134 pmic: pfuze3000@8 { 135 compatible = "fsl,pfuze3000"; 136 reg = <0x08>; 137 138 regulators { 139 /* VDD_ARM_SOC_IN*/ 140 sw1b_reg: sw1b { 141 regulator-min-microvolt = <700000>; 142 regulator-max-microvolt = <1475000>; 143 regulator-boot-on; 144 regulator-always-on; 145 regulator-ramp-delay = <6250>; 146 }; 147 148 /* DRAM */ 149 sw3a_reg: sw3 { 150 regulator-min-microvolt = <900000>; 151 regulator-max-microvolt = <1650000>; 152 regulator-boot-on; 153 regulator-always-on; 154 }; 155 156 /* DRAM */ 157 vref_reg: vrefddr { 158 regulator-boot-on; 159 regulator-always-on; 160 }; 161 }; 162 }; 163 }; 164 165 &lcdif { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; 168 status = "okay"; 169 170 port { 171 display_out: endpoint { 172 remote-endpoint = <&panel_in>; 173 }; 174 }; 175 }; 176 177 &pwm3 { 178 #pwm-cells = <2>; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_pwm3>; 181 status = "okay"; 182 }; 183 184 &pwm7 { 185 pinctrl-names = "default"; 186 pinctrl-0 = <&pinctrl_pwm7>; 187 status = "okay"; 188 }; 189 190 &pwm8 { 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_pwm8>; 193 status = "okay"; 194 }; 195 196 &sai1 { 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_sai1>; 199 status = "okay"; 200 }; 201 202 &uart3 { 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_uart3>; 205 uart-has-rtscts; 206 status = "okay"; 207 }; 208 209 &uart6 { 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_uart6>; 212 status = "okay"; 213 }; 214 215 &usbotg1 { 216 vbus-supply = <®_usb_otg_vbus>; 217 pinctrl-names = "default"; 218 pinctrl-0 = <&pinctrl_usb_otg1_id>; 219 dr_mode = "otg"; 220 disable-over-current; 221 status = "okay"; 222 }; 223 224 &usbotg2 { 225 dr_mode = "host"; 226 disable-over-current; 227 status = "okay"; 228 }; 229 230 &usdhc1 { 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_usdhc1>; 233 bus-width = <8>; 234 no-1-8-v; 235 non-removable; 236 keep-power-in-suspend; 237 status = "okay"; 238 }; 239 240 &usdhc2 { /* Wifi SDIO */ 241 pinctrl-names = "default"; 242 pinctrl-0 = <&pinctrl_usdhc2>; 243 no-1-8-v; 244 non-removable; 245 keep-power-in-suspend; 246 wakeup-source; 247 vmmc-supply = <®_brcm>; 248 status = "okay"; 249 }; 250 251 &wdog1 { 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_wdog>; 254 fsl,ext-reset-output; 255 }; 256 257 &iomuxc { 258 pinctrl_brcm_reg: brcmreggrp { 259 fsl,pins = < 260 MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */ 261 MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */ 262 >; 263 }; 264 265 pinctrl_enet2: enet2grp { 266 fsl,pins = < 267 MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0 268 MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0 269 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 270 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 271 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 272 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 273 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 274 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 275 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 276 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 277 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800 278 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79 279 >; 280 }; 281 282 pinctrl_flexcan1: flexcan1grp { 283 fsl,pins = < 284 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 285 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 286 >; 287 }; 288 289 pinctrl_flexcan2: flexcan2grp { 290 fsl,pins = < 291 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 292 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 293 >; 294 }; 295 296 pinctrl_i2c1: i2c1grp { 297 fsl,pins = < 298 MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 299 MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0 300 >; 301 }; 302 303 pinctrl_i2c2: i2c2grp { 304 fsl,pins = < 305 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 306 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 307 >; 308 }; 309 310 pinctrl_i2c3: i2c3grp { 311 fsl,pins = < 312 MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0 313 MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0 314 >; 315 }; 316 317 pinctrl_lcdif_dat: lcdifdatgrp { 318 fsl,pins = < 319 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 320 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 321 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 322 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 323 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 324 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 325 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 326 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 327 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 328 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 329 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 330 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 331 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 332 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 333 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 334 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 335 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 336 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 337 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 338 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 339 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 340 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 341 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 342 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 343 >; 344 }; 345 346 pinctrl_lcdif_ctrl: lcdifctrlgrp { 347 fsl,pins = < 348 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 349 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 350 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 351 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 352 /* LCD reset */ 353 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 354 >; 355 }; 356 357 pinctrl_pwm3: pwm3grp { 358 fsl,pins = < 359 MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0 360 >; 361 }; 362 363 pinctrl_pwm7: pwm7grp { 364 fsl,pins = < 365 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0 366 >; 367 }; 368 369 pinctrl_pwm8: pwm8grp { 370 fsl,pins = < 371 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 372 >; 373 }; 374 375 pinctrl_sai1: sai1grp { 376 fsl,pins = < 377 MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 378 MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 379 MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 380 MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 381 >; 382 }; 383 384 pinctrl_uart3: uart3grp { 385 fsl,pins = < 386 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0 387 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0 388 MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0 389 MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0 390 >; 391 }; 392 393 pinctrl_uart5: uart5grp { 394 fsl,pins = < 395 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1 396 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1 397 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 398 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 399 >; 400 }; 401 402 pinctrl_uart6: uart6grp { 403 fsl,pins = < 404 MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 405 MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 406 >; 407 }; 408 409 pinctrl_usb_otg1: usbotg1grp { 410 fsl,pins = < 411 MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0 412 >; 413 }; 414 415 pinctrl_usb_otg1_id: usbotg1idgrp { 416 fsl,pins = < 417 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 418 >; 419 }; 420 421 pinctrl_usdhc1: usdhc1grp { 422 fsl,pins = < 423 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 424 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 425 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 426 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 427 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 428 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 429 MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029 430 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 431 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 432 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 433 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 434 >; 435 }; 436 437 pinctrl_usdhc2: usdhc2grp { 438 fsl,pins = < 439 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 440 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 441 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 442 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 443 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 444 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 445 >; 446 }; 447 448 pinctrl_wdog: wdoggrp { 449 fsl,pins = < 450 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 451 >; 452 }; 453 };
Cache object: 9da064910d305760da7e9b0e88ae9a98
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