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sys/contrib/device-tree/src/arm/imx6ul.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright 2015 Freescale Semiconductor, Inc. 4 5 #include <dt-bindings/clock/imx6ul-clock.h> 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/input/input.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include "imx6ul-pinfunc.h" 10 11 / { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 /* 15 * The decompressor and also some bootloaders rely on a 16 * pre-existing /chosen node to be available to insert the 17 * command line and merge other ATAGS info. 18 */ 19 chosen {}; 20 21 aliases { 22 ethernet0 = &fec1; 23 ethernet1 = &fec2; 24 gpio0 = &gpio1; 25 gpio1 = &gpio2; 26 gpio2 = &gpio3; 27 gpio3 = &gpio4; 28 gpio4 = &gpio5; 29 i2c0 = &i2c1; 30 i2c1 = &i2c2; 31 i2c2 = &i2c3; 32 i2c3 = &i2c4; 33 mmc0 = &usdhc1; 34 mmc1 = &usdhc2; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 serial4 = &uart5; 40 serial5 = &uart6; 41 serial6 = &uart7; 42 serial7 = &uart8; 43 sai1 = &sai1; 44 sai2 = &sai2; 45 sai3 = &sai3; 46 spi0 = &ecspi1; 47 spi1 = &ecspi2; 48 spi2 = &ecspi3; 49 spi3 = &ecspi4; 50 usb0 = &usbotg1; 51 usb1 = &usbotg2; 52 usbphy0 = &usbphy1; 53 usbphy1 = &usbphy2; 54 }; 55 56 cpus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 cpu0: cpu@0 { 61 compatible = "arm,cortex-a7"; 62 device_type = "cpu"; 63 reg = <0>; 64 clock-frequency = <696000000>; 65 clock-latency = <61036>; /* two CLK32 periods */ 66 #cooling-cells = <2>; 67 operating-points = 68 /* kHz uV */ 69 <696000 1275000>, 70 <528000 1175000>, 71 <396000 1025000>, 72 <198000 950000>; 73 fsl,soc-operating-points = 74 /* KHz uV */ 75 <696000 1275000>, 76 <528000 1175000>, 77 <396000 1175000>, 78 <198000 1175000>; 79 clocks = <&clks IMX6UL_CLK_ARM>, 80 <&clks IMX6UL_CLK_PLL2_BUS>, 81 <&clks IMX6UL_CLK_PLL2_PFD2>, 82 <&clks IMX6UL_CA7_SECONDARY_SEL>, 83 <&clks IMX6UL_CLK_STEP>, 84 <&clks IMX6UL_CLK_PLL1_SW>, 85 <&clks IMX6UL_CLK_PLL1_SYS>; 86 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", 87 "secondary_sel", "step", "pll1_sw", 88 "pll1_sys"; 89 arm-supply = <®_arm>; 90 soc-supply = <®_soc>; 91 nvmem-cells = <&cpu_speed_grade>; 92 nvmem-cell-names = "speed_grade"; 93 }; 94 }; 95 96 timer { 97 compatible = "arm,armv7-timer"; 98 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 99 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 100 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 102 interrupt-parent = <&intc>; 103 status = "disabled"; 104 }; 105 106 ckil: clock-cli { 107 compatible = "fixed-clock"; 108 #clock-cells = <0>; 109 clock-frequency = <32768>; 110 clock-output-names = "ckil"; 111 }; 112 113 osc: clock-osc { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 clock-frequency = <24000000>; 117 clock-output-names = "osc"; 118 }; 119 120 ipp_di0: clock-di0 { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 clock-frequency = <0>; 124 clock-output-names = "ipp_di0"; 125 }; 126 127 ipp_di1: clock-di1 { 128 compatible = "fixed-clock"; 129 #clock-cells = <0>; 130 clock-frequency = <0>; 131 clock-output-names = "ipp_di1"; 132 }; 133 134 pmu { 135 compatible = "arm,cortex-a7-pmu"; 136 interrupt-parent = <&gpc>; 137 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 138 }; 139 140 soc: soc { 141 #address-cells = <1>; 142 #size-cells = <1>; 143 compatible = "simple-bus"; 144 interrupt-parent = <&gpc>; 145 ranges; 146 147 ocram: sram@900000 { 148 compatible = "mmio-sram"; 149 reg = <0x00900000 0x20000>; 150 ranges = <0 0x00900000 0x20000>; 151 #address-cells = <1>; 152 #size-cells = <1>; 153 }; 154 155 intc: interrupt-controller@a01000 { 156 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 157 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 158 #interrupt-cells = <3>; 159 interrupt-controller; 160 interrupt-parent = <&intc>; 161 reg = <0x00a01000 0x1000>, 162 <0x00a02000 0x2000>, 163 <0x00a04000 0x2000>, 164 <0x00a06000 0x2000>; 165 }; 166 167 dma_apbh: dma-apbh@1804000 { 168 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 169 reg = <0x01804000 0x2000>; 170 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, 171 <0 13 IRQ_TYPE_LEVEL_HIGH>, 172 <0 13 IRQ_TYPE_LEVEL_HIGH>, 173 <0 13 IRQ_TYPE_LEVEL_HIGH>; 174 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 175 #dma-cells = <1>; 176 dma-channels = <4>; 177 clocks = <&clks IMX6UL_CLK_APBHDMA>; 178 }; 179 180 gpmi: nand-controller@1806000 { 181 compatible = "fsl,imx6q-gpmi-nand"; 182 #address-cells = <1>; 183 #size-cells = <1>; 184 reg = <0x01806000 0x2000>, <0x01808000 0x2000>; 185 reg-names = "gpmi-nand", "bch"; 186 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 187 interrupt-names = "bch"; 188 clocks = <&clks IMX6UL_CLK_GPMI_IO>, 189 <&clks IMX6UL_CLK_GPMI_APB>, 190 <&clks IMX6UL_CLK_GPMI_BCH>, 191 <&clks IMX6UL_CLK_GPMI_BCH_APB>, 192 <&clks IMX6UL_CLK_PER_BCH>; 193 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 194 "gpmi_bch_apb", "per1_bch"; 195 dmas = <&dma_apbh 0>; 196 dma-names = "rx-tx"; 197 status = "disabled"; 198 }; 199 200 aips1: bus@2000000 { 201 compatible = "fsl,aips-bus", "simple-bus"; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 reg = <0x02000000 0x100000>; 205 ranges; 206 207 spba-bus@2000000 { 208 compatible = "fsl,spba-bus", "simple-bus"; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 reg = <0x02000000 0x40000>; 212 ranges; 213 214 ecspi1: spi@2008000 { 215 #address-cells = <1>; 216 #size-cells = <0>; 217 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 218 reg = <0x02008000 0x4000>; 219 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&clks IMX6UL_CLK_ECSPI1>, 221 <&clks IMX6UL_CLK_ECSPI1>; 222 clock-names = "ipg", "per"; 223 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; 224 dma-names = "rx", "tx"; 225 status = "disabled"; 226 }; 227 228 ecspi2: spi@200c000 { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 232 reg = <0x0200c000 0x4000>; 233 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&clks IMX6UL_CLK_ECSPI2>, 235 <&clks IMX6UL_CLK_ECSPI2>; 236 clock-names = "ipg", "per"; 237 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; 238 dma-names = "rx", "tx"; 239 status = "disabled"; 240 }; 241 242 ecspi3: spi@2010000 { 243 #address-cells = <1>; 244 #size-cells = <0>; 245 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 246 reg = <0x02010000 0x4000>; 247 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&clks IMX6UL_CLK_ECSPI3>, 249 <&clks IMX6UL_CLK_ECSPI3>; 250 clock-names = "ipg", "per"; 251 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; 252 dma-names = "rx", "tx"; 253 status = "disabled"; 254 }; 255 256 ecspi4: spi@2014000 { 257 #address-cells = <1>; 258 #size-cells = <0>; 259 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; 260 reg = <0x02014000 0x4000>; 261 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&clks IMX6UL_CLK_ECSPI4>, 263 <&clks IMX6UL_CLK_ECSPI4>; 264 clock-names = "ipg", "per"; 265 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; 266 dma-names = "rx", "tx"; 267 status = "disabled"; 268 }; 269 270 uart7: serial@2018000 { 271 compatible = "fsl,imx6ul-uart", 272 "fsl,imx6q-uart"; 273 reg = <0x02018000 0x4000>; 274 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&clks IMX6UL_CLK_UART7_IPG>, 276 <&clks IMX6UL_CLK_UART7_SERIAL>; 277 clock-names = "ipg", "per"; 278 status = "disabled"; 279 }; 280 281 uart1: serial@2020000 { 282 compatible = "fsl,imx6ul-uart", 283 "fsl,imx6q-uart"; 284 reg = <0x02020000 0x4000>; 285 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&clks IMX6UL_CLK_UART1_IPG>, 287 <&clks IMX6UL_CLK_UART1_SERIAL>; 288 clock-names = "ipg", "per"; 289 status = "disabled"; 290 }; 291 292 uart8: serial@2024000 { 293 compatible = "fsl,imx6ul-uart", 294 "fsl,imx6q-uart"; 295 reg = <0x02024000 0x4000>; 296 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&clks IMX6UL_CLK_UART8_IPG>, 298 <&clks IMX6UL_CLK_UART8_SERIAL>; 299 clock-names = "ipg", "per"; 300 status = "disabled"; 301 }; 302 303 sai1: sai@2028000 { 304 #sound-dai-cells = <0>; 305 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; 306 reg = <0x02028000 0x4000>; 307 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&clks IMX6UL_CLK_SAI1_IPG>, 309 <&clks IMX6UL_CLK_SAI1>, 310 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; 311 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 312 dmas = <&sdma 35 24 0>, 313 <&sdma 36 24 0>; 314 dma-names = "rx", "tx"; 315 status = "disabled"; 316 }; 317 318 sai2: sai@202c000 { 319 #sound-dai-cells = <0>; 320 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; 321 reg = <0x0202c000 0x4000>; 322 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&clks IMX6UL_CLK_SAI2_IPG>, 324 <&clks IMX6UL_CLK_SAI2>, 325 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; 326 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 327 dmas = <&sdma 37 24 0>, 328 <&sdma 38 24 0>; 329 dma-names = "rx", "tx"; 330 status = "disabled"; 331 }; 332 333 sai3: sai@2030000 { 334 #sound-dai-cells = <0>; 335 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; 336 reg = <0x02030000 0x4000>; 337 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&clks IMX6UL_CLK_SAI3_IPG>, 339 <&clks IMX6UL_CLK_SAI3>, 340 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; 341 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 342 dmas = <&sdma 39 24 0>, 343 <&sdma 40 24 0>; 344 dma-names = "rx", "tx"; 345 status = "disabled"; 346 }; 347 348 asrc: asrc@2034000 { 349 compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc"; 350 reg = <0x2034000 0x4000>; 351 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&clks IMX6UL_CLK_ASRC_IPG>, 353 <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>, 354 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 355 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 356 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 357 <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>, 358 <&clks IMX6UL_CLK_SPBA>; 359 clock-names = "mem", "ipg", "asrck_0", 360 "asrck_1", "asrck_2", "asrck_3", "asrck_4", 361 "asrck_5", "asrck_6", "asrck_7", "asrck_8", 362 "asrck_9", "asrck_a", "asrck_b", "asrck_c", 363 "asrck_d", "asrck_e", "asrck_f", "spba"; 364 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, 365 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; 366 dma-names = "rxa", "rxb", "rxc", 367 "txa", "txb", "txc"; 368 fsl,asrc-rate = <48000>; 369 fsl,asrc-width = <16>; 370 status = "okay"; 371 }; 372 }; 373 374 tsc: tsc@2040000 { 375 compatible = "fsl,imx6ul-tsc"; 376 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; 377 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&clks IMX6UL_CLK_IPG>, 380 <&clks IMX6UL_CLK_ADC2>; 381 clock-names = "tsc", "adc"; 382 status = "disabled"; 383 }; 384 385 pwm1: pwm@2080000 { 386 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 387 reg = <0x02080000 0x4000>; 388 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&clks IMX6UL_CLK_PWM1>, 390 <&clks IMX6UL_CLK_PWM1>; 391 clock-names = "ipg", "per"; 392 #pwm-cells = <3>; 393 status = "disabled"; 394 }; 395 396 pwm2: pwm@2084000 { 397 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 398 reg = <0x02084000 0x4000>; 399 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&clks IMX6UL_CLK_PWM2>, 401 <&clks IMX6UL_CLK_PWM2>; 402 clock-names = "ipg", "per"; 403 #pwm-cells = <3>; 404 status = "disabled"; 405 }; 406 407 pwm3: pwm@2088000 { 408 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 409 reg = <0x02088000 0x4000>; 410 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&clks IMX6UL_CLK_PWM3>, 412 <&clks IMX6UL_CLK_PWM3>; 413 clock-names = "ipg", "per"; 414 #pwm-cells = <3>; 415 status = "disabled"; 416 }; 417 418 pwm4: pwm@208c000 { 419 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 420 reg = <0x0208c000 0x4000>; 421 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&clks IMX6UL_CLK_PWM4>, 423 <&clks IMX6UL_CLK_PWM4>; 424 clock-names = "ipg", "per"; 425 #pwm-cells = <3>; 426 status = "disabled"; 427 }; 428 429 can1: can@2090000 { 430 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; 431 reg = <0x02090000 0x4000>; 432 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&clks IMX6UL_CLK_CAN1_IPG>, 434 <&clks IMX6UL_CLK_CAN1_SERIAL>; 435 clock-names = "ipg", "per"; 436 fsl,stop-mode = <&gpr 0x10 1>; 437 status = "disabled"; 438 }; 439 440 can2: can@2094000 { 441 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; 442 reg = <0x02094000 0x4000>; 443 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&clks IMX6UL_CLK_CAN2_IPG>, 445 <&clks IMX6UL_CLK_CAN2_SERIAL>; 446 clock-names = "ipg", "per"; 447 fsl,stop-mode = <&gpr 0x10 2>; 448 status = "disabled"; 449 }; 450 451 gpt1: timer@2098000 { 452 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; 453 reg = <0x02098000 0x4000>; 454 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&clks IMX6UL_CLK_GPT1_BUS>, 456 <&clks IMX6UL_CLK_GPT1_SERIAL>; 457 clock-names = "ipg", "per"; 458 }; 459 460 gpio1: gpio@209c000 { 461 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 462 reg = <0x0209c000 0x4000>; 463 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&clks IMX6UL_CLK_GPIO1>; 466 gpio-controller; 467 #gpio-cells = <2>; 468 interrupt-controller; 469 #interrupt-cells = <2>; 470 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, 471 <&iomuxc 16 33 16>; 472 }; 473 474 gpio2: gpio@20a0000 { 475 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 476 reg = <0x020a0000 0x4000>; 477 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&clks IMX6UL_CLK_GPIO2>; 480 gpio-controller; 481 #gpio-cells = <2>; 482 interrupt-controller; 483 #interrupt-cells = <2>; 484 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; 485 }; 486 487 gpio3: gpio@20a4000 { 488 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 489 reg = <0x020a4000 0x4000>; 490 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&clks IMX6UL_CLK_GPIO3>; 493 gpio-controller; 494 #gpio-cells = <2>; 495 interrupt-controller; 496 #interrupt-cells = <2>; 497 gpio-ranges = <&iomuxc 0 65 29>; 498 }; 499 500 gpio4: gpio@20a8000 { 501 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 502 reg = <0x020a8000 0x4000>; 503 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&clks IMX6UL_CLK_GPIO4>; 506 gpio-controller; 507 #gpio-cells = <2>; 508 interrupt-controller; 509 #interrupt-cells = <2>; 510 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; 511 }; 512 513 gpio5: gpio@20ac000 { 514 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; 515 reg = <0x020ac000 0x4000>; 516 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&clks IMX6UL_CLK_GPIO5>; 519 gpio-controller; 520 #gpio-cells = <2>; 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; 524 }; 525 526 fec2: ethernet@20b4000 { 527 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; 528 reg = <0x020b4000 0x4000>; 529 interrupt-names = "int0", "pps"; 530 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&clks IMX6UL_CLK_ENET>, 533 <&clks IMX6UL_CLK_ENET_AHB>, 534 <&clks IMX6UL_CLK_ENET_PTP>, 535 <&clks IMX6UL_CLK_ENET2_REF_125M>, 536 <&clks IMX6UL_CLK_ENET2_REF_125M>; 537 clock-names = "ipg", "ahb", "ptp", 538 "enet_clk_ref", "enet_out"; 539 fsl,num-tx-queues = <1>; 540 fsl,num-rx-queues = <1>; 541 fsl,stop-mode = <&gpr 0x10 4>; 542 fsl,magic-packet; 543 status = "disabled"; 544 }; 545 546 kpp: keypad@20b8000 { 547 compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp"; 548 reg = <0x020b8000 0x4000>; 549 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&clks IMX6UL_CLK_KPP>; 551 status = "disabled"; 552 }; 553 554 wdog1: watchdog@20bc000 { 555 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 556 reg = <0x020bc000 0x4000>; 557 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&clks IMX6UL_CLK_WDOG1>; 559 }; 560 561 wdog2: watchdog@20c0000 { 562 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 563 reg = <0x020c0000 0x4000>; 564 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&clks IMX6UL_CLK_WDOG2>; 566 status = "disabled"; 567 }; 568 569 clks: clock-controller@20c4000 { 570 compatible = "fsl,imx6ul-ccm"; 571 reg = <0x020c4000 0x4000>; 572 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 574 #clock-cells = <1>; 575 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; 576 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; 577 }; 578 579 anatop: anatop@20c8000 { 580 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", 581 "syscon", "simple-mfd"; 582 reg = <0x020c8000 0x1000>; 583 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 586 587 reg_3p0: regulator-3p0 { 588 compatible = "fsl,anatop-regulator"; 589 regulator-name = "vdd3p0"; 590 regulator-min-microvolt = <2625000>; 591 regulator-max-microvolt = <3400000>; 592 anatop-reg-offset = <0x120>; 593 anatop-vol-bit-shift = <8>; 594 anatop-vol-bit-width = <5>; 595 anatop-min-bit-val = <0>; 596 anatop-min-voltage = <2625000>; 597 anatop-max-voltage = <3400000>; 598 anatop-enable-bit = <0>; 599 }; 600 601 reg_arm: regulator-vddcore { 602 compatible = "fsl,anatop-regulator"; 603 regulator-name = "cpu"; 604 regulator-min-microvolt = <725000>; 605 regulator-max-microvolt = <1450000>; 606 regulator-always-on; 607 anatop-reg-offset = <0x140>; 608 anatop-vol-bit-shift = <0>; 609 anatop-vol-bit-width = <5>; 610 anatop-delay-reg-offset = <0x170>; 611 anatop-delay-bit-shift = <24>; 612 anatop-delay-bit-width = <2>; 613 anatop-min-bit-val = <1>; 614 anatop-min-voltage = <725000>; 615 anatop-max-voltage = <1450000>; 616 }; 617 618 reg_soc: regulator-vddsoc { 619 compatible = "fsl,anatop-regulator"; 620 regulator-name = "vddsoc"; 621 regulator-min-microvolt = <725000>; 622 regulator-max-microvolt = <1450000>; 623 regulator-always-on; 624 anatop-reg-offset = <0x140>; 625 anatop-vol-bit-shift = <18>; 626 anatop-vol-bit-width = <5>; 627 anatop-delay-reg-offset = <0x170>; 628 anatop-delay-bit-shift = <28>; 629 anatop-delay-bit-width = <2>; 630 anatop-min-bit-val = <1>; 631 anatop-min-voltage = <725000>; 632 anatop-max-voltage = <1450000>; 633 }; 634 635 tempmon: tempmon { 636 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; 637 interrupt-parent = <&gpc>; 638 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 639 fsl,tempmon = <&anatop>; 640 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 641 nvmem-cell-names = "calib", "temp_grade"; 642 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; 643 }; 644 }; 645 646 usbphy1: usbphy@20c9000 { 647 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 648 reg = <0x020c9000 0x1000>; 649 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&clks IMX6UL_CLK_USBPHY1>; 651 phy-3p0-supply = <®_3p0>; 652 fsl,anatop = <&anatop>; 653 }; 654 655 usbphy2: usbphy@20ca000 { 656 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 657 reg = <0x020ca000 0x1000>; 658 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&clks IMX6UL_CLK_USBPHY2>; 660 phy-3p0-supply = <®_3p0>; 661 fsl,anatop = <&anatop>; 662 }; 663 664 snvs: snvs@20cc000 { 665 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 666 reg = <0x020cc000 0x4000>; 667 668 snvs_rtc: snvs-rtc-lp { 669 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 670 regmap = <&snvs>; 671 offset = <0x34>; 672 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 674 }; 675 676 snvs_poweroff: snvs-poweroff { 677 compatible = "syscon-poweroff"; 678 regmap = <&snvs>; 679 offset = <0x38>; 680 value = <0x60>; 681 mask = <0x60>; 682 status = "disabled"; 683 }; 684 685 snvs_pwrkey: snvs-powerkey { 686 compatible = "fsl,sec-v4.0-pwrkey"; 687 regmap = <&snvs>; 688 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 689 linux,keycode = <KEY_POWER>; 690 wakeup-source; 691 status = "disabled"; 692 }; 693 694 snvs_lpgpr: snvs-lpgpr { 695 compatible = "fsl,imx6ul-snvs-lpgpr"; 696 }; 697 }; 698 699 epit1: epit@20d0000 { 700 reg = <0x020d0000 0x4000>; 701 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 702 }; 703 704 epit2: epit@20d4000 { 705 reg = <0x020d4000 0x4000>; 706 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 707 }; 708 709 src: reset-controller@20d8000 { 710 compatible = "fsl,imx6ul-src", "fsl,imx51-src"; 711 reg = <0x020d8000 0x4000>; 712 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 714 #reset-cells = <1>; 715 }; 716 717 gpc: gpc@20dc000 { 718 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; 719 reg = <0x020dc000 0x4000>; 720 interrupt-controller; 721 #interrupt-cells = <3>; 722 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 723 interrupt-parent = <&intc>; 724 }; 725 726 iomuxc: pinctrl@20e0000 { 727 compatible = "fsl,imx6ul-iomuxc"; 728 reg = <0x020e0000 0x4000>; 729 }; 730 731 gpr: iomuxc-gpr@20e4000 { 732 compatible = "fsl,imx6ul-iomuxc-gpr", 733 "fsl,imx6q-iomuxc-gpr", "syscon"; 734 reg = <0x020e4000 0x4000>; 735 }; 736 737 gpt2: timer@20e8000 { 738 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; 739 reg = <0x020e8000 0x4000>; 740 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&clks IMX6UL_CLK_GPT2_BUS>, 742 <&clks IMX6UL_CLK_GPT2_SERIAL>; 743 clock-names = "ipg", "per"; 744 status = "disabled"; 745 }; 746 747 sdma: sdma@20ec000 { 748 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", 749 "fsl,imx35-sdma"; 750 reg = <0x020ec000 0x4000>; 751 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&clks IMX6UL_CLK_IPG>, 753 <&clks IMX6UL_CLK_SDMA>; 754 clock-names = "ipg", "ahb"; 755 #dma-cells = <3>; 756 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 757 }; 758 759 pwm5: pwm@20f0000 { 760 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 761 reg = <0x020f0000 0x4000>; 762 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&clks IMX6UL_CLK_PWM5>, 764 <&clks IMX6UL_CLK_PWM5>; 765 clock-names = "ipg", "per"; 766 #pwm-cells = <3>; 767 status = "disabled"; 768 }; 769 770 pwm6: pwm@20f4000 { 771 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 772 reg = <0x020f4000 0x4000>; 773 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 774 clocks = <&clks IMX6UL_CLK_PWM6>, 775 <&clks IMX6UL_CLK_PWM6>; 776 clock-names = "ipg", "per"; 777 #pwm-cells = <3>; 778 status = "disabled"; 779 }; 780 781 pwm7: pwm@20f8000 { 782 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 783 reg = <0x020f8000 0x4000>; 784 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&clks IMX6UL_CLK_PWM7>, 786 <&clks IMX6UL_CLK_PWM7>; 787 clock-names = "ipg", "per"; 788 #pwm-cells = <3>; 789 status = "disabled"; 790 }; 791 792 pwm8: pwm@20fc000 { 793 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; 794 reg = <0x020fc000 0x4000>; 795 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&clks IMX6UL_CLK_PWM8>, 797 <&clks IMX6UL_CLK_PWM8>; 798 clock-names = "ipg", "per"; 799 #pwm-cells = <3>; 800 status = "disabled"; 801 }; 802 }; 803 804 aips2: bus@2100000 { 805 compatible = "fsl,aips-bus", "simple-bus"; 806 #address-cells = <1>; 807 #size-cells = <1>; 808 reg = <0x02100000 0x100000>; 809 ranges; 810 811 crypto: crypto@2140000 { 812 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0"; 813 #address-cells = <1>; 814 #size-cells = <1>; 815 reg = <0x2140000 0x3c000>; 816 ranges = <0 0x2140000 0x3c000>; 817 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 818 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>, 819 <&clks IMX6UL_CLK_CAAM_MEM>; 820 clock-names = "ipg", "aclk", "mem"; 821 822 sec_jr0: jr@1000 { 823 compatible = "fsl,sec-v4.0-job-ring"; 824 reg = <0x1000 0x1000>; 825 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 826 }; 827 828 sec_jr1: jr@2000 { 829 compatible = "fsl,sec-v4.0-job-ring"; 830 reg = <0x2000 0x1000>; 831 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 832 }; 833 834 sec_jr2: jr@3000 { 835 compatible = "fsl,sec-v4.0-job-ring"; 836 reg = <0x3000 0x1000>; 837 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 838 }; 839 }; 840 841 usbotg1: usb@2184000 { 842 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; 843 reg = <0x02184000 0x200>; 844 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&clks IMX6UL_CLK_USBOH3>; 846 fsl,usbphy = <&usbphy1>; 847 fsl,usbmisc = <&usbmisc 0>; 848 fsl,anatop = <&anatop>; 849 ahb-burst-config = <0x0>; 850 tx-burst-size-dword = <0x10>; 851 rx-burst-size-dword = <0x10>; 852 status = "disabled"; 853 }; 854 855 usbotg2: usb@2184200 { 856 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; 857 reg = <0x02184200 0x200>; 858 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&clks IMX6UL_CLK_USBOH3>; 860 fsl,usbphy = <&usbphy2>; 861 fsl,usbmisc = <&usbmisc 1>; 862 ahb-burst-config = <0x0>; 863 tx-burst-size-dword = <0x10>; 864 rx-burst-size-dword = <0x10>; 865 status = "disabled"; 866 }; 867 868 usbmisc: usbmisc@2184800 { 869 #index-cells = <1>; 870 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; 871 reg = <0x02184800 0x200>; 872 }; 873 874 fec1: ethernet@2188000 { 875 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; 876 reg = <0x02188000 0x4000>; 877 interrupt-names = "int0", "pps"; 878 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&clks IMX6UL_CLK_ENET>, 881 <&clks IMX6UL_CLK_ENET_AHB>, 882 <&clks IMX6UL_CLK_ENET_PTP>, 883 <&clks IMX6UL_CLK_ENET_REF>, 884 <&clks IMX6UL_CLK_ENET_REF>; 885 clock-names = "ipg", "ahb", "ptp", 886 "enet_clk_ref", "enet_out"; 887 fsl,num-tx-queues = <1>; 888 fsl,num-rx-queues = <1>; 889 fsl,stop-mode = <&gpr 0x10 3>; 890 fsl,magic-packet; 891 status = "disabled"; 892 }; 893 894 usdhc1: mmc@2190000 { 895 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; 896 reg = <0x02190000 0x4000>; 897 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&clks IMX6UL_CLK_USDHC1>, 899 <&clks IMX6UL_CLK_USDHC1>, 900 <&clks IMX6UL_CLK_USDHC1>; 901 clock-names = "ipg", "ahb", "per"; 902 fsl,tuning-step = <2>; 903 fsl,tuning-start-tap = <20>; 904 bus-width = <4>; 905 status = "disabled"; 906 }; 907 908 usdhc2: mmc@2194000 { 909 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; 910 reg = <0x02194000 0x4000>; 911 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&clks IMX6UL_CLK_USDHC2>, 913 <&clks IMX6UL_CLK_USDHC2>, 914 <&clks IMX6UL_CLK_USDHC2>; 915 clock-names = "ipg", "ahb", "per"; 916 bus-width = <4>; 917 fsl,tuning-step = <2>; 918 fsl,tuning-start-tap = <20>; 919 status = "disabled"; 920 }; 921 922 adc1: adc@2198000 { 923 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; 924 reg = <0x02198000 0x4000>; 925 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&clks IMX6UL_CLK_ADC1>; 927 clock-names = "adc"; 928 fsl,adck-max-frequency = <30000000>, <40000000>, 929 <20000000>; 930 status = "disabled"; 931 }; 932 933 i2c1: i2c@21a0000 { 934 #address-cells = <1>; 935 #size-cells = <0>; 936 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 937 reg = <0x021a0000 0x4000>; 938 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 939 clocks = <&clks IMX6UL_CLK_I2C1>; 940 status = "disabled"; 941 }; 942 943 i2c2: i2c@21a4000 { 944 #address-cells = <1>; 945 #size-cells = <0>; 946 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 947 reg = <0x021a4000 0x4000>; 948 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 949 clocks = <&clks IMX6UL_CLK_I2C2>; 950 status = "disabled"; 951 }; 952 953 i2c3: i2c@21a8000 { 954 #address-cells = <1>; 955 #size-cells = <0>; 956 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 957 reg = <0x021a8000 0x4000>; 958 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&clks IMX6UL_CLK_I2C3>; 960 status = "disabled"; 961 }; 962 963 memory-controller@21b0000 { 964 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; 965 reg = <0x021b0000 0x4000>; 966 clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; 967 }; 968 969 weim: weim@21b8000 { 970 #address-cells = <2>; 971 #size-cells = <1>; 972 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; 973 reg = <0x021b8000 0x4000>; 974 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 975 clocks = <&clks IMX6UL_CLK_EIM>; 976 fsl,weim-cs-gpr = <&gpr>; 977 status = "disabled"; 978 }; 979 980 ocotp: efuse@21bc000 { 981 #address-cells = <1>; 982 #size-cells = <1>; 983 compatible = "fsl,imx6ul-ocotp", "syscon"; 984 reg = <0x021bc000 0x4000>; 985 clocks = <&clks IMX6UL_CLK_OCOTP>; 986 987 tempmon_calib: calib@38 { 988 reg = <0x38 4>; 989 }; 990 991 tempmon_temp_grade: temp-grade@20 { 992 reg = <0x20 4>; 993 }; 994 995 cpu_speed_grade: speed-grade@10 { 996 reg = <0x10 4>; 997 }; 998 }; 999 1000 csi: csi@21c4000 { 1001 compatible = "fsl,imx6ul-csi"; 1002 reg = <0x021c4000 0x4000>; 1003 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&clks IMX6UL_CLK_CSI>; 1005 clock-names = "mclk"; 1006 status = "disabled"; 1007 }; 1008 1009 lcdif: lcdif@21c8000 { 1010 compatible = "fsl,imx6ul-lcdif", "fsl,imx6sx-lcdif"; 1011 reg = <0x021c8000 0x4000>; 1012 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, 1014 <&clks IMX6UL_CLK_LCDIF_APB>, 1015 <&clks IMX6UL_CLK_DUMMY>; 1016 clock-names = "pix", "axi", "disp_axi"; 1017 status = "disabled"; 1018 }; 1019 1020 pxp: pxp@21cc000 { 1021 compatible = "fsl,imx6ul-pxp"; 1022 reg = <0x021cc000 0x4000>; 1023 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1024 clocks = <&clks IMX6UL_CLK_PXP>; 1025 clock-names = "axi"; 1026 }; 1027 1028 qspi: spi@21e0000 { 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 compatible = "fsl,imx6ul-qspi"; 1032 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; 1033 reg-names = "QuadSPI", "QuadSPI-memory"; 1034 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&clks IMX6UL_CLK_QSPI>, 1036 <&clks IMX6UL_CLK_QSPI>; 1037 clock-names = "qspi_en", "qspi"; 1038 status = "disabled"; 1039 }; 1040 1041 wdog3: watchdog@21e4000 { 1042 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; 1043 reg = <0x021e4000 0x4000>; 1044 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&clks IMX6UL_CLK_WDOG3>; 1046 status = "disabled"; 1047 }; 1048 1049 uart2: serial@21e8000 { 1050 compatible = "fsl,imx6ul-uart", 1051 "fsl,imx6q-uart"; 1052 reg = <0x021e8000 0x4000>; 1053 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&clks IMX6UL_CLK_UART2_IPG>, 1055 <&clks IMX6UL_CLK_UART2_SERIAL>; 1056 clock-names = "ipg", "per"; 1057 status = "disabled"; 1058 }; 1059 1060 uart3: serial@21ec000 { 1061 compatible = "fsl,imx6ul-uart", 1062 "fsl,imx6q-uart"; 1063 reg = <0x021ec000 0x4000>; 1064 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&clks IMX6UL_CLK_UART3_IPG>, 1066 <&clks IMX6UL_CLK_UART3_SERIAL>; 1067 clock-names = "ipg", "per"; 1068 status = "disabled"; 1069 }; 1070 1071 uart4: serial@21f0000 { 1072 compatible = "fsl,imx6ul-uart", 1073 "fsl,imx6q-uart"; 1074 reg = <0x021f0000 0x4000>; 1075 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1076 clocks = <&clks IMX6UL_CLK_UART4_IPG>, 1077 <&clks IMX6UL_CLK_UART4_SERIAL>; 1078 clock-names = "ipg", "per"; 1079 status = "disabled"; 1080 }; 1081 1082 uart5: serial@21f4000 { 1083 compatible = "fsl,imx6ul-uart", 1084 "fsl,imx6q-uart"; 1085 reg = <0x021f4000 0x4000>; 1086 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1087 clocks = <&clks IMX6UL_CLK_UART5_IPG>, 1088 <&clks IMX6UL_CLK_UART5_SERIAL>; 1089 clock-names = "ipg", "per"; 1090 status = "disabled"; 1091 }; 1092 1093 i2c4: i2c@21f8000 { 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; 1097 reg = <0x021f8000 0x4000>; 1098 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&clks IMX6UL_CLK_I2C4>; 1100 status = "disabled"; 1101 }; 1102 1103 uart6: serial@21fc000 { 1104 compatible = "fsl,imx6ul-uart", 1105 "fsl,imx6q-uart"; 1106 reg = <0x021fc000 0x4000>; 1107 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1108 clocks = <&clks IMX6UL_CLK_UART6_IPG>, 1109 <&clks IMX6UL_CLK_UART6_SERIAL>; 1110 clock-names = "ipg", "per"; 1111 status = "disabled"; 1112 }; 1113 }; 1114 }; 1115 };
Cache object: 2f537172b6184a120f0dcf3da5d6a7fc
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