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sys/contrib/device-tree/src/arm/imx6ull-colibri.dtsi
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1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 /* 3 * Copyright 2018-2022 Toradex 4 */ 5 6 #include "imx6ull.dtsi" 7 8 / { 9 /* Ethernet aliases to ensure correct MAC addresses */ 10 aliases { 11 ethernet0 = &fec2; 12 ethernet1 = &fec1; 13 }; 14 15 backlight: backlight { 16 compatible = "pwm-backlight"; 17 brightness-levels = <0 4 8 16 32 64 128 255>; 18 default-brightness-level = <6>; 19 enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; 20 pinctrl-names = "default"; 21 pinctrl-0 = <&pinctrl_gpio_bl_on>; 22 power-supply = <®_3v3>; 23 pwms = <&pwm4 0 5000000 1>; 24 status = "okay"; 25 }; 26 27 gpio-keys { 28 compatible = "gpio-keys"; 29 pinctrl-names = "default"; 30 pinctrl-0 = <&pinctrl_snvs_gpiokeys>; 31 32 wakeup { 33 debounce-interval = <10>; 34 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ 35 label = "Wake-Up"; 36 linux,code = <KEY_WAKEUP>; 37 wakeup-source; 38 }; 39 }; 40 41 panel_dpi: panel-dpi { 42 compatible = "edt,et057090dhu"; 43 backlight = <&backlight>; 44 power-supply = <®_3v3>; 45 status = "okay"; 46 47 port { 48 lcd_panel_in: endpoint { 49 remote-endpoint = <&lcdif_out>; 50 }; 51 }; 52 }; 53 54 reg_module_3v3: regulator-module-3v3 { 55 compatible = "regulator-fixed"; 56 regulator-always-on; 57 regulator-name = "+V3.3"; 58 regulator-min-microvolt = <3300000>; 59 regulator-max-microvolt = <3300000>; 60 }; 61 62 reg_module_3v3_avdd: regulator-module-3v3-avdd { 63 compatible = "regulator-fixed"; 64 regulator-always-on; 65 regulator-name = "+V3.3_AVDD_AUDIO"; 66 regulator-min-microvolt = <3300000>; 67 regulator-max-microvolt = <3300000>; 68 }; 69 70 reg_sd1_vqmmc: regulator-sd1-vqmmc { 71 compatible = "regulator-gpio"; 72 gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_snvs_reg_sd>; 75 regulator-always-on; 76 regulator-name = "+V3.3_1.8_SD"; 77 regulator-min-microvolt = <1800000>; 78 regulator-max-microvolt = <3300000>; 79 states = <1800000 0x1 3300000 0x0>; 80 vin-supply = <®_module_3v3>; 81 }; 82 83 reg_eth_phy: regulator-eth-phy { 84 compatible = "regulator-fixed-clock"; 85 regulator-boot-on; 86 regulator-min-microvolt = <3300000>; 87 regulator-max-microvolt = <3300000>; 88 regulator-name = "+V3.3_ETH"; 89 regulator-type = "voltage"; 90 vin-supply = <®_module_3v3>; 91 clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; 92 startup-delay-us = <150000>; 93 }; 94 }; 95 96 &adc1 { 97 vref-supply = <®_module_3v3_avdd>; 98 pinctrl-names = "default"; 99 pinctrl-0 = <&pinctrl_adc1>; 100 }; 101 102 &can1 { 103 pinctrl-names = "default"; 104 pinctrl-0 = <&pinctrl_flexcan1>; 105 status = "disabled"; 106 }; 107 108 &can2 { 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_flexcan2>; 111 status = "disabled"; 112 }; 113 114 /* Colibri SPI */ 115 &ecspi1 { 116 cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; 117 pinctrl-names = "default"; 118 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 119 }; 120 121 /* Ethernet */ 122 &fec2 { 123 pinctrl-names = "default", "sleep"; 124 pinctrl-0 = <&pinctrl_enet2>; 125 pinctrl-1 = <&pinctrl_enet2_sleep>; 126 phy-mode = "rmii"; 127 phy-handle = <ðphy1>; 128 phy-supply = <®_eth_phy>; 129 status = "okay"; 130 131 mdio { 132 #address-cells = <1>; 133 #size-cells = <0>; 134 135 ethphy1: ethernet-phy@2 { 136 compatible = "ethernet-phy-ieee802.3-c22"; 137 max-speed = <100>; 138 reg = <2>; 139 }; 140 }; 141 }; 142 143 /* NAND */ 144 &gpmi { 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_gpmi_nand>; 147 fsl,use-minimum-ecc; 148 nand-on-flash-bbt; 149 nand-ecc-mode = "hw"; 150 nand-ecc-strength = <8>; 151 nand-ecc-step-size = <512>; 152 status = "okay"; 153 }; 154 155 /* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ 156 &i2c1 { 157 pinctrl-names = "default", "gpio"; 158 pinctrl-0 = <&pinctrl_i2c1>; 159 pinctrl-1 = <&pinctrl_i2c1_gpio>; 160 sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 161 scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 162 status = "okay"; 163 164 /* Atmel maxtouch controller */ 165 atmel_mxt_ts: touchscreen@4a { 166 compatible = "atmel,maxtouch"; 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_atmel_conn &pinctrl_atmel_snvs_conn>; 169 reg = <0x4a>; 170 interrupt-parent = <&gpio5>; 171 interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 / INT */ 172 reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* SODIMM 106 / RST */ 173 status = "disabled"; 174 }; 175 }; 176 177 /* 178 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 179 * touch screen controller 180 */ 181 &i2c2 { 182 /* Use low frequency to compensate for the high pull-up values. */ 183 clock-frequency = <40000>; 184 pinctrl-names = "default", "gpio"; 185 pinctrl-0 = <&pinctrl_i2c2>; 186 pinctrl-1 = <&pinctrl_i2c2_gpio>; 187 sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 188 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 189 status = "okay"; 190 191 ad7879_ts: touchscreen@2c { 192 compatible = "adi,ad7879-1"; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&pinctrl_snvs_ad7879_int>; 195 reg = <0x2c>; 196 interrupt-parent = <&gpio5>; 197 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 198 touchscreen-max-pressure = <4096>; 199 adi,resistance-plate-x = <120>; 200 adi,first-conversion-delay = /bits/ 8 <3>; 201 adi,acquisition-time = /bits/ 8 <1>; 202 adi,median-filter-size = /bits/ 8 <2>; 203 adi,averaging = /bits/ 8 <1>; 204 adi,conversion-interval = /bits/ 8 <255>; 205 }; 206 }; 207 208 &lcdif { 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_lcdif_dat 211 &pinctrl_lcdif_ctrl>; 212 213 port { 214 lcdif_out: endpoint { 215 remote-endpoint = <&lcd_panel_in>; 216 }; 217 }; 218 }; 219 220 /* PWM <A> */ 221 &pwm4 { 222 pinctrl-names = "default"; 223 pinctrl-0 = <&pinctrl_pwm4>; 224 }; 225 226 /* PWM <B> */ 227 &pwm5 { 228 pinctrl-names = "default"; 229 pinctrl-0 = <&pinctrl_pwm5>; 230 }; 231 232 /* PWM <C> */ 233 &pwm6 { 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_pwm6>; 236 }; 237 238 /* PWM <D> */ 239 &pwm7 { 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_pwm7>; 242 }; 243 244 &sdma { 245 status = "okay"; 246 }; 247 248 &snvs_pwrkey { 249 status = "disabled"; 250 }; 251 252 /* Colibri UART_A */ 253 &uart1 { 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; 256 uart-has-rtscts; 257 fsl,dte-mode; 258 }; 259 260 /* Colibri UART_B */ 261 &uart2 { 262 pinctrl-names = "default"; 263 pinctrl-0 = <&pinctrl_uart2>; 264 uart-has-rtscts; 265 fsl,dte-mode; 266 }; 267 268 /* Colibri UART_C */ 269 &uart5 { 270 pinctrl-names = "default"; 271 pinctrl-0 = <&pinctrl_uart5>; 272 fsl,dte-mode; 273 }; 274 275 /* Colibri USBC */ 276 &usbotg1 { 277 dr_mode = "otg"; 278 srp-disable; 279 hnp-disable; 280 adp-disable; 281 }; 282 283 /* Colibri USBH */ 284 &usbotg2 { 285 dr_mode = "host"; 286 }; 287 288 /* Colibri MMC/SD */ 289 &usdhc1 { 290 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 291 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; 292 pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; 293 pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; 294 pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; 295 assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; 296 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; 297 assigned-clock-rates = <0>, <198000000>; 298 bus-width = <4>; 299 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */ 300 disable-wp; 301 keep-power-in-suspend; 302 no-1-8-v; 303 vqmmc-supply = <®_sd1_vqmmc>; 304 wakeup-source; 305 }; 306 307 &wdog1 { 308 pinctrl-names = "default"; 309 pinctrl-0 = <&pinctrl_wdog>; 310 fsl,ext-reset-output; 311 }; 312 313 &iomuxc { 314 pinctrl_adc1: adc1grp { 315 fsl,pins = < 316 MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */ 317 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */ 318 MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */ 319 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */ 320 >; 321 }; 322 323 pinctrl_atmel_adap: atmeladapgrp { 324 fsl,pins = < 325 MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0a0 /* SODIMM 28 */ 326 MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0xb0a0 /* SODIMM 30 */ 327 >; 328 }; 329 330 pinctrl_atmel_conn: atmelconngrp { 331 fsl,pins = < 332 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ 333 >; 334 }; 335 336 pinctrl_can_int: canintgrp { 337 fsl,pins = < 338 MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ 339 >; 340 }; 341 342 pinctrl_enet2: enet2grp { 343 fsl,pins = < 344 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 345 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 346 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 347 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 348 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 349 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 350 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 351 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 352 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 353 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 354 >; 355 }; 356 357 pinctrl_enet2_sleep: enet2-sleepgrp { 358 fsl,pins = < 359 MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0 360 MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0 361 MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0 362 MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0 363 MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0 364 MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0 365 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 366 MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0 367 MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0 368 MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0 369 >; 370 }; 371 372 pinctrl_ecspi1_cs: ecspi1csgrp { 373 fsl,pins = < 374 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */ 375 >; 376 }; 377 378 pinctrl_ecspi1: ecspi1grp { 379 fsl,pins = < 380 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */ 381 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */ 382 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */ 383 >; 384 }; 385 386 pinctrl_flexcan1: flexcan1grp { 387 fsl,pins = < 388 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 389 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 390 >; 391 }; 392 393 pinctrl_flexcan2: flexcan2grp { 394 fsl,pins = < 395 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 396 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 397 >; 398 }; 399 400 pinctrl_gpio_bl_on: gpioblongrp { 401 fsl,pins = < 402 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */ 403 >; 404 }; 405 406 pinctrl_gpio1: gpio1grp { 407 fsl,pins = < 408 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */ 409 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */ 410 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */ 411 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */ 412 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */ 413 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */ 414 MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */ 415 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */ 416 >; 417 }; 418 419 pinctrl_gpio2: gpio2grp { /* Camera */ 420 fsl,pins = < 421 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */ 422 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */ 423 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */ 424 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */ 425 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */ 426 >; 427 }; 428 429 pinctrl_gpio3: gpio3grp { /* CAN2 */ 430 fsl,pins = < 431 MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */ 432 MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */ 433 >; 434 }; 435 436 pinctrl_gpio4: gpio4grp { 437 fsl,pins = < 438 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */ 439 >; 440 }; 441 442 pinctrl_gpio6: gpio6grp { /* Wifi pins */ 443 fsl,pins = < 444 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */ 445 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */ 446 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */ 447 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */ 448 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */ 449 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */ 450 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */ 451 >; 452 }; 453 454 pinctrl_gpio7: gpio7grp { /* CAN1 */ 455 fsl,pins = < 456 MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */ 457 MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ 458 >; 459 }; 460 461 /* 462 * With an eMMC instead of a raw NAND device the following pins 463 * are available at SODIMM pins. 464 */ 465 pinctrl_gpmi_gpio: gpmigpiogrp { 466 fsl,pins = < 467 MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */ 468 MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */ 469 MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x10b0 /* SODIMM 146 */ 470 MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SODIMM 142 */ 471 >; 472 }; 473 474 pinctrl_gpmi_nand: gpminandgrp { 475 fsl,pins = < 476 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 477 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 478 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 479 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 480 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 481 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 482 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 483 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 484 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 485 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 486 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 487 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 488 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 489 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 490 >; 491 }; 492 493 pinctrl_i2c1: i2c1grp { 494 fsl,pins = < 495 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */ 496 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */ 497 >; 498 }; 499 500 pinctrl_i2c1_gpio: i2c1-gpiogrp { 501 fsl,pins = < 502 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */ 503 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */ 504 >; 505 }; 506 507 pinctrl_i2c2: i2c2grp { 508 fsl,pins = < 509 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0 510 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0 511 >; 512 }; 513 514 pinctrl_i2c2_gpio: i2c2-gpiogrp { 515 fsl,pins = < 516 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0 517 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0 518 >; 519 }; 520 521 pinctrl_lcdif_dat: lcdifdatgrp { 522 fsl,pins = < 523 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */ 524 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */ 525 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */ 526 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */ 527 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */ 528 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */ 529 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */ 530 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */ 531 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */ 532 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */ 533 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */ 534 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */ 535 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */ 536 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */ 537 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */ 538 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */ 539 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */ 540 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */ 541 >; 542 }; 543 544 pinctrl_lcdif_ctrl: lcdifctrlgrp { 545 fsl,pins = < 546 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */ 547 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */ 548 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */ 549 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */ 550 >; 551 }; 552 553 pinctrl_pwm4: pwm4grp { 554 fsl,pins = < 555 MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */ 556 >; 557 }; 558 559 pinctrl_pwm5: pwm5grp { 560 fsl,pins = < 561 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */ 562 >; 563 }; 564 565 pinctrl_pwm6: pwm6grp { 566 fsl,pins = < 567 MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */ 568 >; 569 }; 570 571 pinctrl_pwm7: pwm7grp { 572 fsl,pins = < 573 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */ 574 >; 575 }; 576 577 pinctrl_uart1: uart1grp { 578 fsl,pins = < 579 MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */ 580 MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */ 581 MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */ 582 MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */ 583 >; 584 }; 585 586 pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */ 587 fsl,pins = < 588 MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */ 589 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */ 590 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */ 591 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */ 592 >; 593 }; 594 595 pinctrl_uart2: uart2grp { 596 fsl,pins = < 597 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */ 598 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */ 599 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */ 600 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */ 601 >; 602 }; 603 pinctrl_uart5: uart5grp { 604 fsl,pins = < 605 MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */ 606 MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */ 607 >; 608 }; 609 610 pinctrl_usbh_reg: usbhreggrp { 611 fsl,pins = < 612 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */ 613 >; 614 }; 615 616 pinctrl_usdhc1: usdhc1grp { 617 fsl,pins = < 618 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */ 619 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */ 620 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */ 621 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */ 622 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */ 623 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */ 624 >; 625 }; 626 627 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 628 fsl,pins = < 629 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 630 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 631 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 632 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 633 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 634 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 635 >; 636 }; 637 638 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 639 fsl,pins = < 640 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 641 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 642 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 643 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 644 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 645 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 646 >; 647 }; 648 649 pinctrl_usdhc2: usdhc2grp { 650 fsl,pins = < 651 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069 652 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069 653 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069 654 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069 655 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069 656 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069 657 658 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10 659 >; 660 }; 661 662 pinctrl_usdhc2emmc: usdhc2emmcgrp { 663 fsl,pins = < 664 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 665 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 666 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 667 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 668 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 669 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 670 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 671 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 672 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 673 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 674 >; 675 }; 676 677 pinctrl_wdog: wdoggrp { 678 fsl,pins = < 679 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 680 >; 681 }; 682 }; 683 684 &iomuxc_snvs { 685 pinctrl_atmel_snvs_conn: atmelsnvsconngrp { 686 fsl,pins = < 687 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ 688 >; 689 }; 690 691 pinctrl_snvs_gpio1: snvsgpio1grp { 692 fsl,pins = < 693 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ 694 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ 695 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */ 696 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */ 697 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ 698 >; 699 }; 700 701 pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */ 702 fsl,pins = < 703 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */ 704 >; 705 }; 706 707 pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */ 708 fsl,pins = < 709 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0 710 >; 711 }; 712 713 pinctrl_snvs_reg_sd: snvsregsdgrp { 714 fsl,pins = < 715 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0 716 >; 717 }; 718 719 pinctrl_snvs_usbc_det: snvsusbcdetgrp { 720 fsl,pins = < 721 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0 722 >; 723 }; 724 725 pinctrl_snvs_gpiokeys: snvsgpiokeysgrp { 726 fsl,pins = < 727 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */ 728 >; 729 }; 730 731 pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp { 732 fsl,pins = < 733 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */ 734 >; 735 }; 736 737 pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp { 738 fsl,pins = < 739 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 740 >; 741 }; 742 743 pinctrl_snvs_wifi_pdn: snvswifipdngrp { 744 fsl,pins = < 745 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 746 >; 747 }; 748 };
Cache object: 992b8ac5ac4b4c55aad921f634c355c3
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