Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imx7d-sdb.dts
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 2 // 3 // Copyright (C) 2015 Freescale Semiconductor, Inc. 4 5 /dts-v1/; 6 7 #include "imx7d.dtsi" 8 9 / { 10 model = "Freescale i.MX7 SabreSD Board"; 11 compatible = "fsl,imx7d-sdb", "fsl,imx7d"; 12 13 chosen { 14 stdout-path = &uart1; 15 }; 16 17 memory@80000000 { 18 device_type = "memory"; 19 reg = <0x80000000 0x80000000>; 20 }; 21 22 gpio-keys { 23 compatible = "gpio-keys"; 24 pinctrl-names = "default"; 25 pinctrl-0 = <&pinctrl_gpio_keys>; 26 27 volume-up { 28 label = "Volume Up"; 29 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 30 linux,code = <KEY_VOLUMEUP>; 31 wakeup-source; 32 }; 33 34 volume-down { 35 label = "Volume Down"; 36 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; 37 linux,code = <KEY_VOLUMEDOWN>; 38 wakeup-source; 39 }; 40 }; 41 42 spi4 { 43 compatible = "spi-gpio"; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_spi4>; 46 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; 47 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; 48 cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 49 num-chipselects = <1>; 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 extended_io: gpio-expander@0 { 54 compatible = "fairchild,74hc595"; 55 gpio-controller; 56 #gpio-cells = <2>; 57 reg = <0>; 58 registers-number = <1>; 59 spi-max-frequency = <100000>; 60 }; 61 }; 62 63 reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 64 compatible = "regulator-fixed"; 65 regulator-name = "usb_otg1_vbus"; 66 regulator-min-microvolt = <5000000>; 67 regulator-max-microvolt = <5000000>; 68 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 69 enable-active-high; 70 }; 71 72 reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 73 compatible = "regulator-fixed"; 74 regulator-name = "usb_otg2_vbus"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>; 77 regulator-min-microvolt = <5000000>; 78 regulator-max-microvolt = <5000000>; 79 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; 80 enable-active-high; 81 }; 82 83 reg_vref_1v8: regulator-vref-1v8 { 84 compatible = "regulator-fixed"; 85 regulator-name = "vref-1v8"; 86 regulator-min-microvolt = <1800000>; 87 regulator-max-microvolt = <1800000>; 88 }; 89 90 reg_brcm: regulator-brcm { 91 compatible = "regulator-fixed"; 92 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 93 enable-active-high; 94 regulator-name = "brcm_reg"; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_brcm_reg>; 97 regulator-min-microvolt = <3300000>; 98 regulator-max-microvolt = <3300000>; 99 startup-delay-us = <200000>; 100 }; 101 102 reg_lcd_3v3: regulator-lcd-3v3 { 103 compatible = "regulator-fixed"; 104 regulator-name = "lcd-3v3"; 105 regulator-min-microvolt = <3300000>; 106 regulator-max-microvolt = <3300000>; 107 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; 108 }; 109 110 reg_can2_3v3: regulator-can2-3v3 { 111 compatible = "regulator-fixed"; 112 regulator-name = "can2-3v3"; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_flexcan2_reg>; 115 regulator-min-microvolt = <3300000>; 116 regulator-max-microvolt = <3300000>; 117 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; 118 }; 119 120 reg_fec2_3v3: regulator-fec2-3v3 { 121 compatible = "regulator-fixed"; 122 regulator-name = "fec2-3v3"; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_enet2_reg>; 125 regulator-min-microvolt = <3300000>; 126 regulator-max-microvolt = <3300000>; 127 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; 128 }; 129 130 backlight: backlight { 131 compatible = "pwm-backlight"; 132 pwms = <&pwm1 0 5000000 0>; 133 brightness-levels = <0 4 8 16 32 64 128 255>; 134 default-brightness-level = <6>; 135 status = "okay"; 136 }; 137 138 panel { 139 compatible = "innolux,at043tn24"; 140 backlight = <&backlight>; 141 power-supply = <®_lcd_3v3>; 142 143 port { 144 panel_in: endpoint { 145 remote-endpoint = <&display_out>; 146 }; 147 }; 148 }; 149 150 sound { 151 compatible = "fsl,imx7d-evk-wm8960", 152 "fsl,imx-audio-wm8960"; 153 model = "wm8960-audio"; 154 audio-cpu = <&sai1>; 155 audio-codec = <&codec>; 156 hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; 157 audio-routing = 158 "Headphone Jack", "HP_L", 159 "Headphone Jack", "HP_R", 160 "Ext Spk", "SPK_LP", 161 "Ext Spk", "SPK_LN", 162 "Ext Spk", "SPK_RP", 163 "Ext Spk", "SPK_RN", 164 "LINPUT1", "AMIC", 165 "AMIC", "MICB"; 166 }; 167 168 sound-hdmi { 169 compatible = "fsl,imx-audio-sii902x"; 170 model = "sii902x-audio"; 171 audio-cpu = <&sai3>; 172 hdmi-out; 173 }; 174 }; 175 176 &adc1 { 177 vref-supply = <®_vref_1v8>; 178 status = "okay"; 179 }; 180 181 &adc2 { 182 vref-supply = <®_vref_1v8>; 183 status = "okay"; 184 }; 185 186 &cpu0 { 187 cpu-supply = <&sw1a_reg>; 188 }; 189 190 &cpu1 { 191 cpu-supply = <&sw1a_reg>; 192 }; 193 194 &ecspi3 { 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_ecspi3>; 197 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 198 status = "okay"; 199 200 tsc2046@0 { 201 compatible = "ti,tsc2046"; 202 reg = <0>; 203 spi-max-frequency = <1000000>; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_tsc2046_pendown>; 206 interrupt-parent = <&gpio2>; 207 interrupts = <29 0>; 208 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; 209 ti,x-min = /bits/ 16 <0>; 210 ti,x-max = /bits/ 16 <0>; 211 ti,y-min = /bits/ 16 <0>; 212 ti,y-max = /bits/ 16 <0>; 213 ti,pressure-max = /bits/ 16 <0>; 214 ti,x-plate-ohms = /bits/ 16 <400>; 215 wakeup-source; 216 }; 217 }; 218 219 &fec1 { 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pinctrl_enet1>; 222 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, 223 <&clks IMX7D_ENET1_TIME_ROOT_CLK>; 224 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 225 assigned-clock-rates = <0>, <100000000>; 226 phy-mode = "rgmii"; 227 phy-handle = <ðphy0>; 228 fsl,magic-packet; 229 phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; 230 status = "okay"; 231 232 mdio { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 236 ethphy0: ethernet-phy@0 { 237 reg = <0>; 238 }; 239 240 ethphy1: ethernet-phy@1 { 241 reg = <1>; 242 }; 243 }; 244 }; 245 246 &fec2 { 247 pinctrl-names = "default"; 248 pinctrl-0 = <&pinctrl_enet2>; 249 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, 250 <&clks IMX7D_ENET2_TIME_ROOT_CLK>; 251 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 252 assigned-clock-rates = <0>, <100000000>; 253 phy-mode = "rgmii"; 254 phy-handle = <ðphy1>; 255 phy-supply = <®_fec2_3v3>; 256 fsl,magic-packet; 257 status = "okay"; 258 }; 259 260 &flexcan2 { 261 pinctrl-names = "default"; 262 pinctrl-0 = <&pinctrl_flexcan2>; 263 xceiver-supply = <®_can2_3v3>; 264 status = "okay"; 265 }; 266 267 &i2c1 { 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_i2c1>; 270 status = "okay"; 271 272 pmic: pfuze3000@8 { 273 compatible = "fsl,pfuze3000"; 274 reg = <0x08>; 275 276 regulators { 277 sw1a_reg: sw1a { 278 regulator-min-microvolt = <700000>; 279 regulator-max-microvolt = <1475000>; 280 regulator-boot-on; 281 regulator-always-on; 282 regulator-ramp-delay = <6250>; 283 }; 284 285 /* use sw1c_reg to align with pfuze100/pfuze200 */ 286 sw1c_reg: sw1b { 287 regulator-min-microvolt = <700000>; 288 regulator-max-microvolt = <1475000>; 289 regulator-boot-on; 290 regulator-always-on; 291 regulator-ramp-delay = <6250>; 292 }; 293 294 sw2_reg: sw2 { 295 regulator-min-microvolt = <1800000>; 296 regulator-max-microvolt = <1800000>; 297 regulator-boot-on; 298 regulator-always-on; 299 }; 300 301 sw3a_reg: sw3 { 302 regulator-min-microvolt = <900000>; 303 regulator-max-microvolt = <1650000>; 304 regulator-boot-on; 305 regulator-always-on; 306 }; 307 308 swbst_reg: swbst { 309 regulator-min-microvolt = <5000000>; 310 regulator-max-microvolt = <5150000>; 311 }; 312 313 snvs_reg: vsnvs { 314 regulator-min-microvolt = <1000000>; 315 regulator-max-microvolt = <3000000>; 316 regulator-boot-on; 317 regulator-always-on; 318 }; 319 320 vref_reg: vrefddr { 321 regulator-boot-on; 322 regulator-always-on; 323 }; 324 325 vgen1_reg: vldo1 { 326 regulator-min-microvolt = <1800000>; 327 regulator-max-microvolt = <3300000>; 328 regulator-always-on; 329 }; 330 331 vgen2_reg: vldo2 { 332 regulator-min-microvolt = <800000>; 333 regulator-max-microvolt = <1550000>; 334 }; 335 336 vgen3_reg: vccsd { 337 regulator-min-microvolt = <2850000>; 338 regulator-max-microvolt = <3300000>; 339 regulator-always-on; 340 }; 341 342 vgen4_reg: v33 { 343 regulator-min-microvolt = <2850000>; 344 regulator-max-microvolt = <3300000>; 345 regulator-always-on; 346 }; 347 348 vgen5_reg: vldo3 { 349 regulator-min-microvolt = <1800000>; 350 regulator-max-microvolt = <3300000>; 351 regulator-always-on; 352 }; 353 354 vgen6_reg: vldo4 { 355 regulator-min-microvolt = <2800000>; 356 regulator-max-microvolt = <2800000>; 357 regulator-always-on; 358 }; 359 }; 360 }; 361 }; 362 363 &i2c2 { 364 pinctrl-names = "default"; 365 pinctrl-0 = <&pinctrl_i2c2>; 366 status = "okay"; 367 368 mpl3115@60 { 369 compatible = "fsl,mpl3115"; 370 reg = <0x60>; 371 }; 372 }; 373 374 &i2c3 { 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pinctrl_i2c3>; 377 status = "okay"; 378 }; 379 380 &i2c4 { 381 pinctrl-names = "default"; 382 pinctrl-0 = <&pinctrl_i2c4>; 383 status = "okay"; 384 385 codec: wm8960@1a { 386 compatible = "wlf,wm8960"; 387 reg = <0x1a>; 388 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; 389 clock-names = "mclk"; 390 wlf,shared-lrclk; 391 wlf,hp-cfg = <2 2 3>; 392 wlf,gpio-cfg = <1 3>; 393 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, 394 <&clks IMX7D_PLL_AUDIO_POST_DIV>, 395 <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; 396 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 397 assigned-clock-rates = <0>, <884736000>, <12288000>; 398 }; 399 }; 400 401 &lcdif { 402 pinctrl-names = "default"; 403 pinctrl-0 = <&pinctrl_lcdif>; 404 status = "okay"; 405 406 port { 407 display_out: endpoint { 408 remote-endpoint = <&panel_in>; 409 }; 410 }; 411 }; 412 413 &pcie { 414 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; 415 status = "okay"; 416 }; 417 418 ®_1p0d { 419 vin-supply = <&sw2_reg>; 420 }; 421 422 ®_1p2 { 423 vin-supply = <&sw2_reg>; 424 }; 425 426 &sai1 { 427 pinctrl-names = "default"; 428 pinctrl-0 = <&pinctrl_sai1>; 429 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, 430 <&clks IMX7D_PLL_AUDIO_POST_DIV>, 431 <&clks IMX7D_SAI1_ROOT_CLK>; 432 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 433 assigned-clock-rates = <0>, <884736000>, <36864000>; 434 status = "okay"; 435 }; 436 437 &sai3 { 438 pinctrl-names = "default"; 439 pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; 440 assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, 441 <&clks IMX7D_PLL_AUDIO_POST_DIV>, 442 <&clks IMX7D_SAI3_ROOT_CLK>; 443 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; 444 assigned-clock-rates = <0>, <884736000>, <36864000>; 445 status = "okay"; 446 }; 447 448 &snvs_pwrkey { 449 status = "okay"; 450 }; 451 452 &uart1 { 453 pinctrl-names = "default"; 454 pinctrl-0 = <&pinctrl_uart1>; 455 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; 456 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 457 status = "okay"; 458 }; 459 460 &uart6 { 461 pinctrl-names = "default"; 462 pinctrl-0 = <&pinctrl_uart6>; 463 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; 464 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 465 uart-has-rtscts; 466 status = "okay"; 467 }; 468 469 &usbotg1 { 470 vbus-supply = <®_usb_otg1_vbus>; 471 status = "okay"; 472 }; 473 474 &usbotg2 { 475 vbus-supply = <®_usb_otg2_vbus>; 476 dr_mode = "host"; 477 status = "okay"; 478 }; 479 480 &usdhc1 { 481 pinctrl-names = "default"; 482 pinctrl-0 = <&pinctrl_usdhc1>; 483 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 484 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 485 wakeup-source; 486 keep-power-in-suspend; 487 status = "okay"; 488 }; 489 490 &usdhc2 { 491 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 492 pinctrl-0 = <&pinctrl_usdhc2>; 493 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 494 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 495 wakeup-source; 496 keep-power-in-suspend; 497 non-removable; 498 vmmc-supply = <®_brcm>; 499 fsl,tuning-step = <2>; 500 status = "okay"; 501 }; 502 503 &usdhc3 { 504 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 505 pinctrl-0 = <&pinctrl_usdhc3>; 506 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 507 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 508 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; 509 assigned-clock-rates = <400000000>; 510 bus-width = <8>; 511 fsl,tuning-step = <2>; 512 non-removable; 513 status = "okay"; 514 }; 515 516 &wdog1 { 517 pinctrl-names = "default"; 518 pinctrl-0 = <&pinctrl_wdog>; 519 fsl,ext-reset-output; 520 }; 521 522 &iomuxc { 523 pinctrl-names = "default"; 524 pinctrl-0 = <&pinctrl_hog>; 525 526 imx7d-sdb { 527 pinctrl_brcm_reg: brcmreggrp { 528 fsl,pins = < 529 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 530 >; 531 }; 532 533 pinctrl_ecspi3: ecspi3grp { 534 fsl,pins = < 535 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 536 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 537 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 538 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 539 >; 540 }; 541 542 pinctrl_enet1: enet1grp { 543 fsl,pins = < 544 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 545 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 546 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 547 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 548 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 549 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 550 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 551 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 552 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 553 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 554 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 555 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 556 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 557 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 558 >; 559 }; 560 561 pinctrl_enet2: enet2grp { 562 fsl,pins = < 563 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 564 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 565 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 566 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 567 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 568 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 569 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 570 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 571 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 572 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 573 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 574 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 575 >; 576 }; 577 578 pinctrl_enet2_reg: enet2reggrp { 579 fsl,pins = < 580 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14 581 >; 582 }; 583 584 pinctrl_flexcan2: flexcan2grp { 585 fsl,pins = < 586 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 587 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 588 >; 589 }; 590 591 pinctrl_flexcan2_reg: flexcan2reggrp { 592 fsl,pins = < 593 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ 594 >; 595 }; 596 597 pinctrl_gpio_keys: gpio_keysgrp { 598 fsl,pins = < 599 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 600 MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 601 >; 602 }; 603 604 pinctrl_hog: hoggrp { 605 fsl,pins = < 606 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ 607 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */ 608 >; 609 }; 610 611 pinctrl_i2c1: i2c1grp { 612 fsl,pins = < 613 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 614 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f 615 >; 616 }; 617 618 pinctrl_i2c2: i2c2grp { 619 fsl,pins = < 620 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f 621 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f 622 >; 623 }; 624 625 pinctrl_i2c3: i2c3grp { 626 fsl,pins = < 627 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f 628 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f 629 >; 630 }; 631 632 pinctrl_i2c4: i2c4grp { 633 fsl,pins = < 634 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f 635 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f 636 >; 637 }; 638 639 pinctrl_lcdif: lcdifgrp { 640 fsl,pins = < 641 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 642 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 643 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 644 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 645 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 646 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 647 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 648 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 649 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 650 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 651 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 652 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 653 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 654 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 655 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 656 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 657 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 658 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 659 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 660 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 661 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 662 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 663 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 664 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 665 MX7D_PAD_LCD_CLK__LCD_CLK 0x79 666 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 667 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 668 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 669 MX7D_PAD_LCD_RESET__LCD_RESET 0x79 670 >; 671 }; 672 673 pinctrl_sai1: sai1grp { 674 fsl,pins = < 675 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f 676 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f 677 MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f 678 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 679 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f 680 >; 681 }; 682 683 pinctrl_sai2: sai2grp { 684 fsl,pins = < 685 MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f 686 MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f 687 MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 688 MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f 689 >; 690 }; 691 692 pinctrl_sai3: sai3grp { 693 fsl,pins = < 694 MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f 695 MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f 696 MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 697 >; 698 }; 699 700 pinctrl_spi4: spi4grp { 701 fsl,pins = < 702 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 703 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 704 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 705 >; 706 }; 707 708 pinctrl_tsc2046_pendown: tsc2046_pendown { 709 fsl,pins = < 710 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 711 >; 712 }; 713 714 pinctrl_uart1: uart1grp { 715 fsl,pins = < 716 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 717 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 718 >; 719 }; 720 721 pinctrl_uart5: uart5grp { 722 fsl,pins = < 723 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 724 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 725 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 726 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 727 >; 728 }; 729 730 pinctrl_uart6: uart6grp { 731 fsl,pins = < 732 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 733 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 734 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 735 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 736 >; 737 }; 738 739 pinctrl_usdhc1: usdhc1grp { 740 fsl,pins = < 741 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 742 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 743 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 744 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 745 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 746 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 747 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ 748 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ 749 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ 750 >; 751 }; 752 753 pinctrl_usdhc2: usdhc2grp { 754 fsl,pins = < 755 MX7D_PAD_SD2_CMD__SD2_CMD 0x59 756 MX7D_PAD_SD2_CLK__SD2_CLK 0x19 757 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 758 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 759 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 760 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 761 >; 762 }; 763 764 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { 765 fsl,pins = < 766 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a 767 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a 768 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a 769 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a 770 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a 771 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a 772 >; 773 }; 774 775 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { 776 fsl,pins = < 777 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b 778 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b 779 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b 780 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b 781 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b 782 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b 783 >; 784 }; 785 786 787 pinctrl_usdhc3: usdhc3grp { 788 fsl,pins = < 789 MX7D_PAD_SD3_CMD__SD3_CMD 0x59 790 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 791 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 792 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 793 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 794 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 795 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 796 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 797 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 798 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 799 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 800 >; 801 }; 802 803 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { 804 fsl,pins = < 805 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a 806 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a 807 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a 808 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a 809 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a 810 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a 811 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a 812 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a 813 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a 814 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a 815 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a 816 >; 817 }; 818 819 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { 820 fsl,pins = < 821 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b 822 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b 823 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b 824 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b 825 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b 826 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b 827 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b 828 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b 829 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b 830 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b 831 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b 832 >; 833 }; 834 }; 835 }; 836 837 &pwm1 { 838 pinctrl-names = "default"; 839 pinctrl-0 = <&pinctrl_pwm1>; 840 status = "okay"; 841 }; 842 843 &iomuxc_lpsr { 844 pinctrl_wdog: wdoggrp { 845 fsl,pins = < 846 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 847 >; 848 }; 849 850 pinctrl_pwm1: pwm1grp { 851 fsl,pins = < 852 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 853 >; 854 }; 855 856 pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp { 857 fsl,pins = < 858 MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 859 >; 860 }; 861 862 pinctrl_sai3_mclk: sai3grp_mclk { 863 fsl,pins = < 864 MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f 865 >; 866 }; 867 };
Cache object: cf55c82b5bb1c718303aa455b57d0869
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]