Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/imxrt1050.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (C) 2019 4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> 5 */ 6 7 #include "armv7-m.dtsi" 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/imxrt1050-clock.h> 10 #include <dt-bindings/gpio/gpio.h> 11 12 / { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 clocks { 17 osc: osc { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 clock-frequency = <24000000>; 21 }; 22 23 osc3M: osc3M { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <3000000>; 27 }; 28 }; 29 30 soc { 31 lpuart1: serial@40184000 { 32 compatible = "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart"; 33 reg = <0x40184000 0x4000>; 34 interrupts = <20>; 35 clocks = <&clks IMXRT1050_CLK_LPUART1>; 36 clock-names = "ipg"; 37 status = "disabled"; 38 }; 39 40 iomuxc: pinctrl@401f8000 { 41 compatible = "fsl,imxrt1050-iomuxc"; 42 reg = <0x401f8000 0x4000>; 43 fsl,mux_mask = <0x7>; 44 }; 45 46 anatop: anatop@400d8000 { 47 compatible = "fsl,imxrt-anatop"; 48 reg = <0x400d8000 0x4000>; 49 }; 50 51 clks: clock-controller@400fc000 { 52 compatible = "fsl,imxrt1050-ccm"; 53 reg = <0x400fc000 0x4000>; 54 interrupts = <95>, <96>; 55 clocks = <&osc>; 56 clock-names = "osc"; 57 #clock-cells = <1>; 58 assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>, 59 <&clks IMXRT1050_CLK_PLL1_BYPASS>, 60 <&clks IMXRT1050_CLK_PLL2_BYPASS>, 61 <&clks IMXRT1050_CLK_PLL3_BYPASS>, 62 <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>, 63 <&clks IMXRT1050_CLK_PLL2_PFD2_396M>; 64 assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>, 65 <&clks IMXRT1050_CLK_PLL1_ARM>, 66 <&clks IMXRT1050_CLK_PLL2_SYS>, 67 <&clks IMXRT1050_CLK_PLL3_USB_OTG>, 68 <&clks IMXRT1050_CLK_PLL3_USB_OTG>, 69 <&clks IMXRT1050_CLK_PLL2_SYS>; 70 }; 71 72 edma1: dma-controller@400e8000 { 73 #dma-cells = <2>; 74 compatible = "fsl,imx7ulp-edma"; 75 reg = <0x400e8000 0x4000>, 76 <0x400ec000 0x4000>; 77 dma-channels = <32>; 78 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, 79 <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>; 80 clock-names = "dma", "dmamux0"; 81 clocks = <&clks IMXRT1050_CLK_DMA>, 82 <&clks IMXRT1050_CLK_DMA_MUX>; 83 }; 84 85 usdhc1: mmc@402c0000 { 86 compatible = "fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc"; 87 reg = <0x402c0000 0x4000>; 88 interrupts = <110>; 89 clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, 90 <&clks IMXRT1050_CLK_OSC>, 91 <&clks IMXRT1050_CLK_USDHC1>; 92 clock-names = "ipg", "ahb", "per"; 93 bus-width = <4>; 94 fsl,wp-controller; 95 no-1-8-v; 96 max-frequency = <4000000>; 97 fsl,tuning-start-tap = <20>; 98 fsl,tuning-step = <2>; 99 status = "disabled"; 100 }; 101 102 gpio1: gpio@401b8000 { 103 compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; 104 reg = <0x401b8000 0x4000>; 105 interrupts = <80>, <81>; 106 gpio-controller; 107 #gpio-cells = <2>; 108 interrupt-controller; 109 #interrupt-cells = <2>; 110 }; 111 112 gpio2: gpio@401bc000 { 113 compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; 114 reg = <0x401bc000 0x4000>; 115 interrupts = <82>, <83>; 116 gpio-controller; 117 #gpio-cells = <2>; 118 interrupt-controller; 119 #interrupt-cells = <2>; 120 }; 121 122 gpio3: gpio@401c0000 { 123 compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; 124 reg = <0x401c0000 0x4000>; 125 interrupts = <84>, <85>; 126 gpio-controller; 127 #gpio-cells = <2>; 128 interrupt-controller; 129 #interrupt-cells = <2>; 130 }; 131 132 gpio4: gpio@401c4000 { 133 compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; 134 reg = <0x401c4000 0x4000>; 135 interrupts = <86>, <87>; 136 gpio-controller; 137 #gpio-cells = <2>; 138 interrupt-controller; 139 #interrupt-cells = <2>; 140 }; 141 142 gpio5: gpio@400c0000 { 143 compatible = "fsl,imxrt1050-gpio", "fsl,imx35-gpio"; 144 reg = <0x400c0000 0x4000>; 145 interrupts = <88>, <89>; 146 gpio-controller; 147 #gpio-cells = <2>; 148 interrupt-controller; 149 #interrupt-cells = <2>; 150 }; 151 152 gpt: timer@401ec000 { 153 compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; 154 reg = <0x401ec000 0x4000>; 155 interrupts = <100>; 156 clocks = <&osc3M>; 157 clock-names = "per"; 158 }; 159 }; 160 };
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