intel-ixp42x-gateworks-gw2348.dts

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    1 // SPDX-License-Identifier: ISC
    2 /*
    3  * Device Tree file for the Gateworks Avila GW2348 board.
    4  * This machine is based on IXP425.
    5  */
    6 
    7 /dts-v1/;
    8 
    9 #include "intel-ixp42x.dtsi"
   10 #include <dt-bindings/input/input.h>
   11 
   12 / {
   13         model = "Gateworks Avila GW2348";
   14         compatible = "gateworks,gw2348", "intel,ixp42x";
   15         #address-cells = <1>;
   16         #size-cells = <1>;
   17 
   18         memory@0 {
   19                 device_type = "memory";
   20                 reg = <0x00000000 0x4000000>;
   21         };
   22 
   23         chosen {
   24                 bootargs = "console=ttyS0,115200n8";
   25                 stdout-path = "uart0:115200n8";
   26         };
   27 
   28         aliases {
   29                 serial0 = &uart0;
   30         };
   31 
   32         leds {
   33                 compatible = "gpio-leds";
   34                 led-user {
   35                         label = "gw2348:green:user";
   36                         gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
   37                         default-state = "on";
   38                         linux,default-trigger = "heartbeat";
   39                 };
   40         };
   41 
   42         i2c {
   43                 compatible = "i2c-gpio";
   44                 sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
   45                 scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
   46                 #address-cells = <1>;
   47                 #size-cells = <0>;
   48 
   49                 hwmon@28 {
   50                         compatible = "adi,ad7418";
   51                         reg = <0x28>;
   52                 };
   53                 rtc: ds1672@68 {
   54                         compatible = "dallas,ds1672";
   55                         reg = <0x68>;
   56                 };
   57                 eeprom@51 {
   58                         compatible = "atmel,24c08";
   59                         reg = <0x51>;
   60                         pagesize = <16>;
   61                         size = <1024>;
   62                         read-only;
   63                 };
   64         };
   65 
   66         soc {
   67                 bus@c4000000 {
   68                         flash@0,0 {
   69                                 compatible = "intel,ixp4xx-flash", "cfi-flash";
   70                                 bank-width = <2>;
   71                                 /* Enable writes on the expansion bus */
   72                                 intel,ixp4xx-eb-write-enable = <1>;
   73                                 /* 16 MB of Flash mapped in at CS0 */
   74                                 reg = <0 0x00000000 0x1000000>;
   75 
   76                                 partitions {
   77                                         compatible = "redboot-fis";
   78                                         /* Eraseblock at 0x0fe0000 */
   79                                         fis-index-block = <0x7f>;
   80                                 };
   81                         };
   82                         ide@1,0 {
   83                                 compatible = "intel,ixp4xx-compact-flash";
   84                                 /*
   85                                  * Set up expansion bus config to a really slow timing.
   86                                  * The CF driver will dynamically reconfigure these timings
   87                                  * depending on selected PIO mode (0-4).
   88                                  */
   89                                 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
   90                                 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
   91                                 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
   92                                 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
   93                                 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
   94                                 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
   95                                 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
   96                                 intel,ixp4xx-eb-mux-address-and-data = <0>;
   97                                 intel,ixp4xx-eb-ahb-split-transfers = <0>;
   98                                 intel,ixp4xx-eb-write-enable = <1>;
   99                                 intel,ixp4xx-eb-byte-access = <1>;
  100                                 /* First register set is CMD second is CTL (notice it uses CS2) */
  101                                 reg = <1 0x00000000 0x1000000>, <2 0x00000000 0x1000000>;
  102                                 interrupt-parent = <&gpio0>;
  103                                 interrupts = <12 IRQ_TYPE_EDGE_RISING>;
  104                         };
  105                         /*
  106                          * FIXME: Latch LEDs or extra UARTs at CS4
  107                          */
  108                 };
  109 
  110                 pci@c0000000 {
  111                         status = "ok";
  112 
  113                         /*
  114                          * Taken from Avila PCI boardfile.
  115                          *
  116                          * We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
  117                          */
  118                         #interrupt-cells = <1>;
  119                         interrupt-map-mask = <0xf800 0 0 7>;
  120                         interrupt-map =
  121                         /* IDSEL 1 */
  122                         <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
  123                         <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
  124                         <0x0800 0 0 3 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
  125                         <0x0800 0 0 4 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
  126                         /* IDSEL 2 */
  127                         <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
  128                         <0x1000 0 0 2 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
  129                         <0x1000 0 0 3 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
  130                         <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
  131                         /* IDSEL 3 */
  132                         <0x1800 0 0 1 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
  133                         <0x1800 0 0 2 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
  134                         <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
  135                         <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
  136                         /* IDSEL 4 */
  137                         <0x2000 0 0 1 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
  138                         <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */
  139                         <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */
  140                         <0x2000 0 0 4 &gpio0 9  IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */
  141                 };
  142 
  143                 /* EthB */
  144                 ethernet@c8009000 {
  145                         status = "ok";
  146                         queue-rx = <&qmgr 3>;
  147                         queue-txready = <&qmgr 20>;
  148                         phy-mode = "rgmii";
  149                         phy-handle = <&phy0>;
  150 
  151                         mdio {
  152                                 #address-cells = <1>;
  153                                 #size-cells = <0>;
  154 
  155                                 phy0: ethernet-phy@0 {
  156                                         reg = <0>;
  157                                 };
  158 
  159                                 phy1: ethernet-phy@1 {
  160                                         reg = <1>;
  161                                 };
  162                         };
  163                 };
  164 
  165                 /* EthC */
  166                 ethernet@c800a000 {
  167                         status = "ok";
  168                         queue-rx = <&qmgr 4>;
  169                         queue-txready = <&qmgr 21>;
  170                         phy-mode = "rgmii";
  171                         phy-handle = <&phy1>;
  172                 };
  173         };
  174 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/intel-ixp42x-gateworks-gw2348.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/intel-ixp42x-gateworks-gw2348.dts