ls1021a-tsn.dts

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    1 // SPDX-License-Identifier: GPL-2.0
    2 /* Copyright 2016-2018 NXP Semiconductors
    3  * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
    4  */
    5 
    6 /dts-v1/;
    7 #include "ls1021a.dtsi"
    8 
    9 / {
   10         model = "NXP LS1021A-TSN Board";
   11         compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";
   12 
   13         sys_mclk: clock-mclk {
   14                 compatible = "fixed-clock";
   15                 #clock-cells = <0>;
   16                 clock-frequency = <24576000>;
   17         };
   18 
   19         reg_vdda_codec: regulator-3V3 {
   20                 compatible = "regulator-fixed";
   21                 regulator-name = "3P3V";
   22                 regulator-min-microvolt = <3300000>;
   23                 regulator-max-microvolt = <3300000>;
   24                 regulator-always-on;
   25         };
   26 
   27         reg_vddio_codec: regulator-2V5 {
   28                 compatible = "regulator-fixed";
   29                 regulator-name = "2P5V";
   30                 regulator-min-microvolt = <2500000>;
   31                 regulator-max-microvolt = <2500000>;
   32                 regulator-always-on;
   33         };
   34 };
   35 
   36 &dspi0 {
   37         bus-num = <0>;
   38         status = "okay";
   39 
   40         /* ADG704BRMZ 1:4 SPI mux/demux */
   41         sja1105: ethernet-switch@1 {
   42                 reg = <0x1>;
   43                 #address-cells = <1>;
   44                 #size-cells = <0>;
   45                 compatible = "nxp,sja1105t";
   46                 /* 12 MHz */
   47                 spi-max-frequency = <12000000>;
   48                 /* Sample data on trailing clock edge */
   49                 spi-cpha;
   50                 /* SPI controller settings for SJA1105 timing requirements */
   51                 fsl,spi-cs-sck-delay = <1000>;
   52                 fsl,spi-sck-cs-delay = <1000>;
   53 
   54                 ports {
   55                         #address-cells = <1>;
   56                         #size-cells = <0>;
   57 
   58                         port@0 {
   59                                 /* ETH5 written on chassis */
   60                                 label = "swp5";
   61                                 phy-handle = <&rgmii_phy6>;
   62                                 phy-mode = "rgmii-id";
   63                                 reg = <0>;
   64                         };
   65 
   66                         port@1 {
   67                                 /* ETH2 written on chassis */
   68                                 label = "swp2";
   69                                 phy-handle = <&rgmii_phy3>;
   70                                 phy-mode = "rgmii-id";
   71                                 reg = <1>;
   72                         };
   73 
   74                         port@2 {
   75                                 /* ETH3 written on chassis */
   76                                 label = "swp3";
   77                                 phy-handle = <&rgmii_phy4>;
   78                                 phy-mode = "rgmii-id";
   79                                 reg = <2>;
   80                         };
   81 
   82                         port@3 {
   83                                 /* ETH4 written on chassis */
   84                                 label = "swp4";
   85                                 phy-handle = <&rgmii_phy5>;
   86                                 phy-mode = "rgmii-id";
   87                                 reg = <3>;
   88                         };
   89 
   90                         port@4 {
   91                                 /* Internal port connected to eth2 */
   92                                 ethernet = <&enet2>;
   93                                 phy-mode = "rgmii";
   94                                 rx-internal-delay-ps = <0>;
   95                                 tx-internal-delay-ps = <0>;
   96                                 reg = <4>;
   97 
   98                                 fixed-link {
   99                                         speed = <1000>;
  100                                         full-duplex;
  101                                 };
  102                         };
  103                 };
  104         };
  105 };
  106 
  107 &enet0 {
  108         tbi-handle = <&tbi0>;
  109         phy-handle = <&sgmii_phy2>;
  110         phy-mode = "sgmii";
  111         status = "okay";
  112 };
  113 
  114 &enet1 {
  115         tbi-handle = <&tbi1>;
  116         phy-handle = <&sgmii_phy1>;
  117         phy-mode = "sgmii";
  118         status = "okay";
  119 };
  120 
  121 /* RGMII delays added via PCB traces */
  122 &enet2 {
  123         phy-mode = "rgmii";
  124         status = "okay";
  125 
  126         fixed-link {
  127                 speed = <1000>;
  128                 full-duplex;
  129         };
  130 };
  131 
  132 &esdhc {
  133         status = "okay";
  134 };
  135 
  136 &i2c0 {
  137         status = "okay";
  138 
  139         /* 3 axis accelerometer */
  140         accelerometer@1e {
  141                 compatible = "fsl,fxls8471";
  142                 reg = <0x1e>;
  143         };
  144 
  145         /* Audio codec (SAI2) */
  146         audio-codec@2a {
  147                 compatible = "fsl,sgtl5000";
  148                 VDDIO-supply = <&reg_vddio_codec>;
  149                 VDDA-supply = <&reg_vdda_codec>;
  150                 #sound-dai-cells = <0>;
  151                 clocks = <&sys_mclk>;
  152                 reg = <0x2a>;
  153         };
  154 
  155         /* Current sensing circuit for 1V VDDCORE PMIC rail */
  156         current-sensor@44 {
  157                 compatible = "ti,ina220";
  158                 shunt-resistor = <1000>;
  159                 reg = <0x44>;
  160         };
  161 
  162         /* Current sensing circuit for 12V VCC rail */
  163         current-sensor@45 {
  164                 compatible = "ti,ina220";
  165                 shunt-resistor = <1000>;
  166                 reg = <0x45>;
  167         };
  168 
  169         /* Thermal monitor - case */
  170         temperature-sensor@48 {
  171                 compatible = "national,lm75";
  172                 reg = <0x48>;
  173         };
  174 
  175         /* Thermal monitor - chip */
  176         temperature-sensor@4c {
  177                 compatible = "ti,tmp451";
  178                 reg = <0x4c>;
  179         };
  180 
  181         eeprom@51 {
  182                 compatible = "atmel,24c32";
  183                 reg = <0x51>;
  184         };
  185 
  186         /* Unsupported devices:
  187          * - FXAS21002C Gyroscope at 0x20
  188          * - TI ADS7924 4-channel ADC at 0x49
  189          */
  190 };
  191 
  192 &ifc {
  193         status = "disabled";
  194 };
  195 
  196 &lpuart0 {
  197         status = "okay";
  198 };
  199 
  200 &lpuart3 {
  201         status = "okay";
  202 };
  203 
  204 &mdio0 {
  205         /* AR8031 */
  206         sgmii_phy1: ethernet-phy@1 {
  207                 reg = <0x1>;
  208                 /* SGMII1_PHY_INT_B: connected to IRQ2, active low */
  209                 interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
  210         };
  211 
  212         /* AR8031 */
  213         sgmii_phy2: ethernet-phy@2 {
  214                 reg = <0x2>;
  215                 /* SGMII2_PHY_INT_B: connected to IRQ2, active low */
  216                 interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
  217         };
  218 
  219         /* BCM5464 quad PHY */
  220         rgmii_phy3: ethernet-phy@3 {
  221                 reg = <0x3>;
  222         };
  223 
  224         rgmii_phy4: ethernet-phy@4 {
  225                 reg = <0x4>;
  226         };
  227 
  228         rgmii_phy5: ethernet-phy@5 {
  229                 reg = <0x5>;
  230         };
  231 
  232         rgmii_phy6: ethernet-phy@6 {
  233                 reg = <0x6>;
  234         };
  235 
  236         /* SGMII PCS for enet0 */
  237         tbi0: tbi-phy@1f {
  238                 reg = <0x1f>;
  239                 device_type = "tbi-phy";
  240         };
  241 };
  242 
  243 &mdio1 {
  244         /* SGMII PCS for enet1 */
  245         tbi1: tbi-phy@1f {
  246                 reg = <0x1f>;
  247                 device_type = "tbi-phy";
  248         };
  249 };
  250 
  251 &qspi {
  252         status = "okay";
  253 
  254         flash@0 {
  255                 /* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */
  256                 compatible = "jedec,spi-nor";
  257                 spi-max-frequency = <20000000>;
  258                 #address-cells = <1>;
  259                 #size-cells = <1>;
  260                 reg = <0>;
  261 
  262                 partitions {
  263                         compatible = "fixed-partitions";
  264                         #address-cells = <1>;
  265                         #size-cells = <1>;
  266 
  267                         partition@0 {
  268                                 label = "RCW";
  269                                 reg = <0x0 0x40000>;
  270                         };
  271 
  272                         partition@40000 {
  273                                 label = "U-Boot";
  274                                 reg = <0x40000 0x300000>;
  275                         };
  276 
  277                         partition@340000 {
  278                                 label = "U-Boot Env";
  279                                 reg = <0x340000 0x100000>;
  280                         };
  281                 };
  282         };
  283 };
  284 
  285 &sai2 {
  286         status = "okay";
  287 };
  288 
  289 &sata {
  290         status = "okay";
  291 };
  292 
  293 &uart0 {
  294         status = "okay";
  295 };

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sys/contrib/device-tree/src/arm/ls1021a-tsn.dts