Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/mba6ulx.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2 /* 3 * Copyright 2018-2022 TQ-Systems GmbH 4 * Author: Markus Niebel <Markus.Niebel@tq-group.com> 5 */ 6 7 / { 8 model = "TQ-Systems MBA6ULx Baseboard"; 9 10 aliases { 11 mmc0 = &usdhc2; 12 mmc1 = &usdhc1; 13 rtc0 = &rtc0; 14 rtc1 = &snvs_rtc; 15 }; 16 17 chosen { 18 stdout-path = &uart1; 19 }; 20 21 backlight: backlight { 22 compatible = "pwm-backlight"; 23 power-supply = <®_mba6ul_3v3>; 24 enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>; 25 status = "disabled"; 26 }; 27 28 beeper: beeper { 29 compatible = "gpio-beeper"; 30 gpios = <&expander_out1 6 GPIO_ACTIVE_HIGH>; 31 }; 32 33 gpio_buttons: gpio-keys { 34 compatible = "gpio-keys"; 35 pinctrl-names = "default"; 36 pinctrl-0 = <&pinctrl_buttons>; 37 38 button1 { 39 label = "s14"; 40 linux,code = <KEY_1>; 41 gpios = <&expander_in0 0 GPIO_ACTIVE_LOW>; 42 }; 43 44 button2 { 45 label = "s6"; 46 linux,code = <KEY_2>; 47 gpios = <&expander_in0 1 GPIO_ACTIVE_LOW>; 48 }; 49 50 button3 { 51 label = "s7"; 52 linux,code = <KEY_3>; 53 gpios = <&expander_in0 2 GPIO_ACTIVE_LOW>; 54 }; 55 56 power-button { 57 label = "POWER"; 58 linux,code = <KEY_POWER>; 59 gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; 60 gpio-key,wakeup; 61 }; 62 }; 63 64 gpio-leds { 65 compatible = "gpio-leds"; 66 status = "okay"; 67 68 led1 { 69 label = "led1"; 70 gpios = <&expander_out1 4 GPIO_ACTIVE_HIGH>; 71 linux,default-trigger = "default-on"; 72 }; 73 74 led2 { 75 label = "led2"; 76 gpios = <&expander_out1 5 GPIO_ACTIVE_HIGH>; 77 linux,default-trigger = "heartbeat"; 78 }; 79 }; 80 81 reg_lcd_pwr: regulator-lcd-pwr { 82 compatible = "regulator-fixed"; 83 regulator-name = "lcd-pwr"; 84 gpio = <&expander_out0 1 GPIO_ACTIVE_HIGH>; 85 enable-active-high; 86 status = "disabled"; 87 }; 88 89 reg_mba6ul_3v3: regulator-mba6ul-3v3 { 90 compatible = "regulator-fixed"; 91 regulator-name = "supply-mba6ul-3v3"; 92 regulator-min-microvolt = <3300000>; 93 regulator-max-microvolt = <3300000>; 94 regulator-always-on; 95 }; 96 97 reg_mba6ul_5v0: regulator-mba6ul-5v0 { 98 compatible = "regulator-fixed"; 99 regulator-name = "supply-mba6ul-5v0"; 100 regulator-min-microvolt = <5000000>; 101 regulator-max-microvolt = <5000000>; 102 regulator-always-on; 103 }; 104 105 reg_mpcie: regulator-mpcie-3v3 { 106 compatible = "regulator-fixed"; 107 regulator-name = "mpcie-3v3"; 108 regulator-min-microvolt = <3300000>; 109 regulator-max-microvolt = <3300000>; 110 gpio = <&expander_out0 2 GPIO_ACTIVE_HIGH>; 111 enable-active-high; 112 regulator-always-on; 113 startup-delay-us = <500000>; 114 vin-supply = <®_mba6ul_3v3>; 115 }; 116 117 reg_otg2vbus_5v0: regulator-otg2-vbus-5v0 { 118 compatible = "regulator-fixed"; 119 gpio = <&expander_out1 0 GPIO_ACTIVE_HIGH>; 120 enable-active-high; 121 regulator-name = "otg2-vbus-supply-5v0"; 122 regulator-min-microvolt = <5000000>; 123 regulator-max-microvolt = <5000000>; 124 vin-supply = <®_mpcie>; 125 }; 126 127 reserved-memory { 128 #address-cells = <1>; 129 #size-cells = <1>; 130 ranges; 131 132 linux,cma { 133 compatible = "shared-dma-pool"; 134 reusable; 135 size = <0x6000000>; 136 linux,cma-default; 137 }; 138 }; 139 140 sound { 141 compatible = "fsl,imx-audio-tlv320aic32x4"; 142 model = "imx-audio-tlv320aic32x4"; 143 ssi-controller = <&sai1>; 144 audio-codec = <&tlv320aic32x4>; 145 audio-asrc = <&asrc>; 146 }; 147 }; 148 149 &can1 { 150 pinctrl-names = "default"; 151 pinctrl-0 = <&pinctrl_flexcan1>; 152 xceiver-supply = <®_mba6ul_3v3>; 153 status = "okay"; 154 }; 155 156 &can2 { 157 pinctrl-names = "default"; 158 pinctrl-0 = <&pinctrl_flexcan2>; 159 xceiver-supply = <®_mba6ul_3v3>; 160 status = "okay"; 161 }; 162 163 &clks { 164 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 165 assigned-clock-rates = <768000000>; 166 }; 167 168 &ecspi2 { 169 pinctrl-names = "default"; 170 pinctrl-0 = <&pinctrl_ecspi2>; 171 num-cs = <1>; 172 status = "okay"; 173 }; 174 175 &fec1 { 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_enet1>; 178 phy-mode = "rmii"; 179 phy-handle = <ðphy0>; 180 phy-supply = <®_mba6ul_3v3>; 181 phy-reset-gpios = <&expander_out1 1 GPIO_ACTIVE_LOW>; 182 phy-reset-duration = <25>; 183 phy-reset-post-delay = <1>; 184 status = "okay"; 185 }; 186 187 &fec2 { 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_mdc>; 190 phy-mode = "rmii"; 191 phy-handle = <ðphy1>; 192 phy-supply = <®_mba6ul_3v3>; 193 phy-reset-gpios = <&expander_out1 2 GPIO_ACTIVE_LOW>; 194 phy-reset-duration = <25>; 195 phy-reset-post-delay = <1>; 196 status = "okay"; 197 198 mdio { 199 #address-cells = <1>; 200 #size-cells = <0>; 201 202 ethphy0: ethernet-phy@0 { 203 compatible = "ethernet-phy-ieee802.3-c22"; 204 clocks = <&clks IMX6UL_CLK_ENET_REF>; 205 reg = <0>; 206 max-speed = <100>; 207 }; 208 209 ethphy1: ethernet-phy@1 { 210 compatible = "ethernet-phy-ieee802.3-c22"; 211 clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; 212 reg = <1>; 213 max-speed = <100>; 214 }; 215 }; 216 }; 217 218 &i2c4 { 219 tlv320aic32x4: audio-codec@18 { 220 compatible = "ti,tlv320aic32x4"; 221 reg = <0x18>; 222 clocks = <&clks IMX6UL_CLK_SAI1>; 223 clock-names = "mclk"; 224 ldoin-supply = <®_mba6ul_3v3>; 225 iov-supply = <®_mba6ul_3v3>; 226 }; 227 228 jc42: temperature-sensor@19 { 229 compatible = "nxp,se97", "jedec,jc-42.4-temp"; 230 reg = <0x19>; 231 }; 232 233 expander_out0: gpio-expander@20 { 234 compatible = "nxp,pca9554"; 235 reg = <0x20>; 236 gpio-controller; 237 #gpio-cells = <2>; 238 }; 239 240 expander_in0: gpio-expander@21 { 241 compatible = "nxp,pca9554"; 242 reg = <0x21>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_expander_in0>; 245 interrupt-parent = <&gpio4>; 246 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 247 interrupt-controller; 248 #interrupt-cells = <2>; 249 gpio-controller; 250 #gpio-cells = <2>; 251 252 enet1_int-hog { 253 gpio-hog; 254 gpios = <6 0>; 255 input; 256 }; 257 258 enet2_int-hog { 259 gpio-hog; 260 gpios = <7 0>; 261 input; 262 }; 263 }; 264 265 expander_out1: gpio-expander@22 { 266 compatible = "nxp,pca9554"; 267 reg = <0x22>; 268 gpio-controller; 269 #gpio-cells = <2>; 270 }; 271 272 analog_touch: touchscreen@41 { 273 compatible = "st,stmpe811"; 274 reg = <0x41>; 275 interrupts = <21 IRQ_TYPE_EDGE_FALLING>; 276 interrupt-parent = <&gpio4>; 277 interrupt-controller; 278 status = "disabled"; 279 280 stmpe_touchscreen { 281 compatible = "st,stmpe-ts"; 282 st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ 283 st,ave-ctrl = <3>; /* 8 sample average control */ 284 st,fraction-z = <7>; /* 7 length fractional part in z */ 285 /* 286 * 50 mA typical 80 mA max touchscreen drivers 287 * current limit value 288 */ 289 st,i-drive = <1>; 290 st,mod-12b = <1>; /* 12-bit ADC */ 291 st,ref-sel = <0>; /* internal ADC reference */ 292 st,sample-time = <4>; /* ADC converstion time: 80 clocks */ 293 st,settling = <3>; /* 1 ms panel driver settling time */ 294 st,touch-det-delay = <5>; /* 5 ms touch detect interrupt delay */ 295 }; 296 }; 297 298 /* NXP SE97BTP with temperature sensor + eeprom */ 299 se97b: eeprom@51 { 300 compatible = "nxp,se97b", "atmel,24c02"; 301 reg = <0x51>; 302 pagesize = <16>; 303 }; 304 }; 305 306 &pwm2 { 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_pwm2>; 309 status = "okay"; 310 }; 311 312 &sai1 { 313 pinctrl-names = "default"; 314 pinctrl-0 = <&pinctrl_sai1>; 315 assigned-clocks = <&clks IMX6UL_CLK_SAI1_SEL>, 316 <&clks IMX6UL_CLK_SAI1>; 317 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 318 assigned-clock-rates = <0>, <24000000>; 319 fsl,sai-mclk-direction-output; 320 status = "okay"; 321 }; 322 323 &uart1 { 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pinctrl_uart1>; 326 status = "okay"; 327 }; 328 329 &uart3 { 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pinctrl_uart3>; 332 status = "okay"; 333 }; 334 335 &uart6 { 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_uart6>; 338 /* for DTE mode, add below change */ 339 /* fsl,dte-mode; */ 340 /* pinctrl-0 = <&pinctrl_uart6dte>; */ 341 uart-has-rtscts; 342 linux,rs485-enabled-at-boot-time; 343 rs485-rts-active-low; 344 rs485-rx-during-tx; 345 status = "okay"; 346 }; 347 348 /* otg-port */ 349 &usbotg1 { 350 pinctrl-names = "default"; 351 pinctrl-0 = <&pinctrl_usb_otg1>; 352 power-active-high; 353 over-current-active-low; 354 /* we implement only dual role but not a fully featured OTG */ 355 hnp-disable; 356 srp-disable; 357 adp-disable; 358 dr_mode = "otg"; 359 status = "okay"; 360 }; 361 362 /* 7-port usb hub */ 363 /* id, pwr, oc pins not connected */ 364 &usbotg2 { 365 disable-over-current; 366 vbus-supply = <®_otg2vbus_5v0>; 367 dr_mode = "host"; 368 status = "okay"; 369 }; 370 371 &usdhc1 { 372 pinctrl-names = "default"; 373 pinctrl-0 = <&pinctrl_usdhc1>; 374 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; 375 wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; 376 bus-width = <4>; 377 vmmc-supply = <®_mba6ul_3v3>; 378 vqmmc-supply = <®_vccsd>; 379 no-1-8-v; 380 no-mmc; 381 no-sdio; 382 status = "okay"; 383 }; 384 385 &wdog1 { 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_wdog1>; 388 fsl,ext-reset-output; 389 status = "okay"; 390 }; 391 392 &iomuxc { 393 pinctrl_buttons: buttonsgrp { 394 fsl,pins = < 395 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x100b0 396 >; 397 }; 398 399 pinctrl_ecspi2: ecspi2grp { 400 fsl,pins = < 401 MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b020 402 MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b020 403 MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b020 404 MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x1b020 405 >; 406 }; 407 408 pinctrl_enet1: enet1grp { 409 fsl,pins = < 410 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 411 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 412 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 413 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 414 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 415 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 416 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 417 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 418 >; 419 }; 420 421 pinctrl_enet2: enet2grp { 422 fsl,pins = < 423 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 424 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 425 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 426 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 427 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0 428 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0 429 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 430 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 431 >; 432 }; 433 434 pinctrl_enet2_mdc: enet2mdcgrp { 435 fsl,pins = < 436 /* mdio */ 437 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 438 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 439 >; 440 }; 441 442 pinctrl_expander_in0: expanderin0grp { 443 fsl,pins = < 444 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x1b0b1 445 >; 446 }; 447 448 pinctrl_flexcan1: flexcan1grp { 449 fsl,pins = < 450 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 451 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 452 >; 453 }; 454 455 pinctrl_flexcan2: flexcan2grp { 456 fsl,pins = < 457 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 458 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 459 >; 460 }; 461 462 pinctrl_pwm2: pwm2grp { 463 fsl,pins = < 464 /* 100 k PD, DSE 120 OHM, SPPEED LO */ 465 MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x00003050 466 >; 467 }; 468 469 pinctrl_sai1: sai1grp { 470 fsl,pins = < 471 MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b1 472 MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b1 473 MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 474 MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 475 MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b1 476 >; 477 }; 478 479 pinctrl_uart1: uart1grp { 480 fsl,pins = < 481 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 482 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 483 >; 484 }; 485 486 pinctrl_uart3: uart3grp { 487 fsl,pins = < 488 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 489 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 490 >; 491 }; 492 493 pinctrl_uart6: uart6grp { 494 fsl,pins = < 495 MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 496 MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 497 MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1 498 MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1 499 >; 500 }; 501 502 pinctrl_uart6dte: uart6dte { 503 fsl,pins = < 504 MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x1b0b1 505 MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x1b0b1 506 MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x1b0b1 507 MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x1b0b1 508 >; 509 }; 510 511 pinctrl_usb_otg1: usbotg1grp { 512 fsl,pins = < 513 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x00017059 514 MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0001b0b0 515 MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x0001b099 516 >; 517 }; 518 519 pinctrl_usdhc1: usdhc1grp { 520 fsl,pins = < 521 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 522 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x00017059 523 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x00017059 524 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x00017059 525 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x00017059 526 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x00017059 527 /* WP */ 528 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 529 /* CD */ 530 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 531 >; 532 }; 533 534 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 535 fsl,pins = < 536 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 537 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170b9 538 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170b9 539 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170b9 540 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170b9 541 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170b9 542 /* WP */ 543 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 544 /* CD */ 545 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 546 >; 547 }; 548 549 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 550 fsl,pins = < 551 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x00017069 552 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x000170f9 553 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x000170f9 554 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x000170f9 555 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x000170f9 556 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x000170f9 557 /* WP */ 558 MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0001b099 559 /* CD */ 560 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0001b099 561 >; 562 }; 563 564 pinctrl_wdog1: wdog1grp { 565 fsl,pins = < 566 MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0001b099 567 >; 568 }; 569 };
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