Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/omap2.dtsi
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1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Device Tree Source for OMAP2 SoC 4 * 5 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8 #include <dt-bindings/bus/ti-sysc.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 11 #include <dt-bindings/pinctrl/omap.h> 12 13 / { 14 compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; 15 interrupt-parent = <&intc>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 chosen { }; 19 20 aliases { 21 serial0 = &uart1; 22 serial1 = &uart2; 23 serial2 = &uart3; 24 i2c0 = &i2c1; 25 i2c1 = &i2c2; 26 }; 27 28 cpus { 29 #address-cells = <0>; 30 #size-cells = <0>; 31 32 cpu { 33 compatible = "arm,arm1136jf-s"; 34 device_type = "cpu"; 35 }; 36 }; 37 38 pmu { 39 compatible = "arm,arm1136-pmu"; 40 interrupts = <3>; 41 }; 42 43 soc { 44 compatible = "ti,omap-infra"; 45 mpu { 46 compatible = "ti,omap2-mpu"; 47 ti,hwmods = "mpu"; 48 }; 49 }; 50 51 ocp { 52 compatible = "simple-bus"; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 ranges; 56 ti,hwmods = "l3_main"; 57 58 aes: aes@480a6000 { 59 compatible = "ti,omap2-aes"; 60 ti,hwmods = "aes"; 61 reg = <0x480a6000 0x50>; 62 dmas = <&sdma 9 &sdma 10>; 63 dma-names = "tx", "rx"; 64 }; 65 66 hdq1w: 1w@480b2000 { 67 compatible = "ti,omap2420-1w"; 68 ti,hwmods = "hdq1w"; 69 reg = <0x480b2000 0x1000>; 70 interrupts = <58>; 71 }; 72 73 intc: interrupt-controller@1 { 74 compatible = "ti,omap2-intc"; 75 interrupt-controller; 76 #interrupt-cells = <1>; 77 reg = <0x480FE000 0x1000>; 78 }; 79 80 target-module@48056000 { 81 compatible = "ti,sysc-omap2", "ti,sysc"; 82 reg = <0x48056000 0x4>, 83 <0x4805602c 0x4>, 84 <0x48056028 0x4>; 85 reg-names = "rev", "sysc", "syss"; 86 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 87 SYSC_OMAP2_EMUFREE | 88 SYSC_OMAP2_SOFTRESET | 89 SYSC_OMAP2_AUTOIDLE)>; 90 ti,sysc-midle = <SYSC_IDLE_FORCE>, 91 <SYSC_IDLE_NO>, 92 <SYSC_IDLE_SMART>; 93 ti,syss-mask = <1>; 94 clocks = <&core_l3_ck>; 95 clock-names = "fck"; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 ranges = <0 0x48056000 0x1000>; 99 100 sdma: dma-controller@0 { 101 compatible = "ti,omap2420-sdma", "ti,omap-sdma"; 102 reg = <0 0x1000>; 103 interrupts = <12>, 104 <13>, 105 <14>, 106 <15>; 107 #dma-cells = <1>; 108 dma-channels = <32>; 109 dma-requests = <64>; 110 }; 111 }; 112 113 i2c1: i2c@48070000 { 114 compatible = "ti,omap2-i2c"; 115 ti,hwmods = "i2c1"; 116 reg = <0x48070000 0x80>; 117 #address-cells = <1>; 118 #size-cells = <0>; 119 interrupts = <56>; 120 }; 121 122 i2c2: i2c@48072000 { 123 compatible = "ti,omap2-i2c"; 124 ti,hwmods = "i2c2"; 125 reg = <0x48072000 0x80>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 interrupts = <57>; 129 }; 130 131 mcspi1: spi@48098000 { 132 compatible = "ti,omap2-mcspi"; 133 ti,hwmods = "mcspi1"; 134 reg = <0x48098000 0x100>; 135 interrupts = <65>; 136 dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38 137 &sdma 39 &sdma 40 &sdma 41 &sdma 42>; 138 dma-names = "tx0", "rx0", "tx1", "rx1", 139 "tx2", "rx2", "tx3", "rx3"; 140 }; 141 142 mcspi2: spi@4809a000 { 143 compatible = "ti,omap2-mcspi"; 144 ti,hwmods = "mcspi2"; 145 reg = <0x4809a000 0x100>; 146 interrupts = <66>; 147 dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>; 148 dma-names = "tx0", "rx0", "tx1", "rx1"; 149 }; 150 151 rng: rng@480a0000 { 152 compatible = "ti,omap2-rng"; 153 ti,hwmods = "rng"; 154 reg = <0x480a0000 0x50>; 155 interrupts = <52>; 156 }; 157 158 sham: sham@480a4000 { 159 compatible = "ti,omap2-sham"; 160 ti,hwmods = "sham"; 161 reg = <0x480a4000 0x64>; 162 interrupts = <51>; 163 dmas = <&sdma 13>; 164 dma-names = "rx"; 165 }; 166 167 uart1: serial@4806a000 { 168 compatible = "ti,omap2-uart"; 169 ti,hwmods = "uart1"; 170 reg = <0x4806a000 0x2000>; 171 interrupts = <72>; 172 dmas = <&sdma 49 &sdma 50>; 173 dma-names = "tx", "rx"; 174 clock-frequency = <48000000>; 175 }; 176 177 uart2: serial@4806c000 { 178 compatible = "ti,omap2-uart"; 179 ti,hwmods = "uart2"; 180 reg = <0x4806c000 0x400>; 181 interrupts = <73>; 182 dmas = <&sdma 51 &sdma 52>; 183 dma-names = "tx", "rx"; 184 clock-frequency = <48000000>; 185 }; 186 187 uart3: serial@4806e000 { 188 compatible = "ti,omap2-uart"; 189 ti,hwmods = "uart3"; 190 reg = <0x4806e000 0x400>; 191 interrupts = <74>; 192 dmas = <&sdma 53 &sdma 54>; 193 dma-names = "tx", "rx"; 194 clock-frequency = <48000000>; 195 }; 196 197 timer2_target: target-module@4802a000 { 198 compatible = "ti,sysc-omap2-timer", "ti,sysc"; 199 reg = <0x4802a000 0x4>, 200 <0x4802a010 0x4>, 201 <0x4802a014 0x4>; 202 reg-names = "rev", "sysc", "syss"; 203 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 204 SYSC_OMAP2_EMUFREE | 205 SYSC_OMAP2_ENAWAKEUP | 206 SYSC_OMAP2_SOFTRESET | 207 SYSC_OMAP2_AUTOIDLE)>; 208 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 209 <SYSC_IDLE_NO>, 210 <SYSC_IDLE_SMART>; 211 ti,syss-mask = <1>; 212 clocks = <&gpt2_fck>, <&gpt2_ick>; 213 clock-names = "fck", "ick"; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 ranges = <0x0 0x4802a000 0x1000>; 217 218 timer2: timer@0 { 219 compatible = "ti,omap2420-timer"; 220 reg = <0 0x400>; 221 interrupts = <38>; 222 }; 223 }; 224 225 timer3: timer@48078000 { 226 compatible = "ti,omap2420-timer"; 227 reg = <0x48078000 0x400>; 228 interrupts = <39>; 229 ti,hwmods = "timer3"; 230 }; 231 232 timer4: timer@4807a000 { 233 compatible = "ti,omap2420-timer"; 234 reg = <0x4807a000 0x400>; 235 interrupts = <40>; 236 ti,hwmods = "timer4"; 237 }; 238 239 timer5: timer@4807c000 { 240 compatible = "ti,omap2420-timer"; 241 reg = <0x4807c000 0x400>; 242 interrupts = <41>; 243 ti,hwmods = "timer5"; 244 ti,timer-dsp; 245 }; 246 247 timer6: timer@4807e000 { 248 compatible = "ti,omap2420-timer"; 249 reg = <0x4807e000 0x400>; 250 interrupts = <42>; 251 ti,hwmods = "timer6"; 252 ti,timer-dsp; 253 }; 254 255 timer7: timer@48080000 { 256 compatible = "ti,omap2420-timer"; 257 reg = <0x48080000 0x400>; 258 interrupts = <43>; 259 ti,hwmods = "timer7"; 260 ti,timer-dsp; 261 }; 262 263 timer8: timer@48082000 { 264 compatible = "ti,omap2420-timer"; 265 reg = <0x48082000 0x400>; 266 interrupts = <44>; 267 ti,hwmods = "timer8"; 268 ti,timer-dsp; 269 }; 270 271 timer9: timer@48084000 { 272 compatible = "ti,omap2420-timer"; 273 reg = <0x48084000 0x400>; 274 interrupts = <45>; 275 ti,hwmods = "timer9"; 276 ti,timer-pwm; 277 }; 278 279 timer10: timer@48086000 { 280 compatible = "ti,omap2420-timer"; 281 reg = <0x48086000 0x400>; 282 interrupts = <46>; 283 ti,hwmods = "timer10"; 284 ti,timer-pwm; 285 }; 286 287 timer11: timer@48088000 { 288 compatible = "ti,omap2420-timer"; 289 reg = <0x48088000 0x400>; 290 interrupts = <47>; 291 ti,hwmods = "timer11"; 292 ti,timer-pwm; 293 }; 294 295 timer12: timer@4808a000 { 296 compatible = "ti,omap2420-timer"; 297 reg = <0x4808a000 0x400>; 298 interrupts = <48>; 299 ti,hwmods = "timer12"; 300 ti,timer-pwm; 301 }; 302 303 dss: dss@48050000 { 304 compatible = "ti,omap2-dss"; 305 reg = <0x48050000 0x400>; 306 status = "disabled"; 307 ti,hwmods = "dss_core"; 308 #address-cells = <1>; 309 #size-cells = <1>; 310 ranges; 311 312 dispc@48050400 { 313 compatible = "ti,omap2-dispc"; 314 reg = <0x48050400 0x400>; 315 interrupts = <25>; 316 ti,hwmods = "dss_dispc"; 317 }; 318 319 rfbi: encoder@48050800 { 320 compatible = "ti,omap2-rfbi"; 321 reg = <0x48050800 0x400>; 322 status = "disabled"; 323 ti,hwmods = "dss_rfbi"; 324 }; 325 326 venc: encoder@48050c00 { 327 compatible = "ti,omap2-venc"; 328 reg = <0x48050c00 0x400>; 329 status = "disabled"; 330 ti,hwmods = "dss_venc"; 331 }; 332 }; 333 }; 334 };
Cache object: 50231504d300db98a6da2a0535d4d737
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