omap2420-clocks.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0-only
    2 /*
    3  * Device Tree Source for OMAP2420 clock data
    4  *
    5  * Copyright (C) 2014 Texas Instruments, Inc.
    6  */
    7 
    8 &prcm_clocks {
    9         sys_clkout2_src_gate: sys_clkout2_src_gate@70 {
   10                 #clock-cells = <0>;
   11                 compatible = "ti,composite-no-wait-gate-clock";
   12                 clocks = <&core_ck>;
   13                 ti,bit-shift = <15>;
   14                 reg = <0x0070>;
   15         };
   16 
   17         sys_clkout2_src_mux: sys_clkout2_src_mux@70 {
   18                 #clock-cells = <0>;
   19                 compatible = "ti,composite-mux-clock";
   20                 clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
   21                 ti,bit-shift = <8>;
   22                 reg = <0x0070>;
   23         };
   24 
   25         sys_clkout2_src: sys_clkout2_src {
   26                 #clock-cells = <0>;
   27                 compatible = "ti,composite-clock";
   28                 clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
   29         };
   30 
   31         sys_clkout2: sys_clkout2@70 {
   32                 #clock-cells = <0>;
   33                 compatible = "ti,divider-clock";
   34                 clocks = <&sys_clkout2_src>;
   35                 ti,bit-shift = <11>;
   36                 ti,max-div = <64>;
   37                 reg = <0x0070>;
   38                 ti,index-power-of-two;
   39         };
   40 
   41         dsp_gate_ick: dsp_gate_ick@810 {
   42                 #clock-cells = <0>;
   43                 compatible = "ti,composite-interface-clock";
   44                 clocks = <&dsp_fck>;
   45                 ti,bit-shift = <1>;
   46                 reg = <0x0810>;
   47         };
   48 
   49         dsp_div_ick: dsp_div_ick@840 {
   50                 #clock-cells = <0>;
   51                 compatible = "ti,composite-divider-clock";
   52                 clocks = <&dsp_fck>;
   53                 ti,bit-shift = <5>;
   54                 ti,max-div = <3>;
   55                 reg = <0x0840>;
   56                 ti,index-starts-at-one;
   57         };
   58 
   59         dsp_ick: dsp_ick {
   60                 #clock-cells = <0>;
   61                 compatible = "ti,composite-clock";
   62                 clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
   63         };
   64 
   65         iva1_gate_ifck: iva1_gate_ifck@800 {
   66                 #clock-cells = <0>;
   67                 compatible = "ti,composite-gate-clock";
   68                 clocks = <&core_ck>;
   69                 ti,bit-shift = <10>;
   70                 reg = <0x0800>;
   71         };
   72 
   73         iva1_div_ifck: iva1_div_ifck@840 {
   74                 #clock-cells = <0>;
   75                 compatible = "ti,composite-divider-clock";
   76                 clocks = <&core_ck>;
   77                 ti,bit-shift = <8>;
   78                 reg = <0x0840>;
   79                 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
   80         };
   81 
   82         iva1_ifck: iva1_ifck {
   83                 #clock-cells = <0>;
   84                 compatible = "ti,composite-clock";
   85                 clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
   86         };
   87 
   88         iva1_ifck_div: iva1_ifck_div {
   89                 #clock-cells = <0>;
   90                 compatible = "fixed-factor-clock";
   91                 clocks = <&iva1_ifck>;
   92                 clock-mult = <1>;
   93                 clock-div = <2>;
   94         };
   95 
   96         iva1_mpu_int_ifck: iva1_mpu_int_ifck@800 {
   97                 #clock-cells = <0>;
   98                 compatible = "ti,wait-gate-clock";
   99                 clocks = <&iva1_ifck_div>;
  100                 ti,bit-shift = <8>;
  101                 reg = <0x0800>;
  102         };
  103 
  104         wdt3_ick: wdt3_ick@210 {
  105                 #clock-cells = <0>;
  106                 compatible = "ti,omap3-interface-clock";
  107                 clocks = <&l4_ck>;
  108                 ti,bit-shift = <28>;
  109                 reg = <0x0210>;
  110         };
  111 
  112         wdt3_fck: wdt3_fck@200 {
  113                 #clock-cells = <0>;
  114                 compatible = "ti,wait-gate-clock";
  115                 clocks = <&func_32k_ck>;
  116                 ti,bit-shift = <28>;
  117                 reg = <0x0200>;
  118         };
  119 
  120         mmc_ick: mmc_ick@210 {
  121                 #clock-cells = <0>;
  122                 compatible = "ti,omap3-interface-clock";
  123                 clocks = <&l4_ck>;
  124                 ti,bit-shift = <26>;
  125                 reg = <0x0210>;
  126         };
  127 
  128         mmc_fck: mmc_fck@200 {
  129                 #clock-cells = <0>;
  130                 compatible = "ti,wait-gate-clock";
  131                 clocks = <&func_96m_ck>;
  132                 ti,bit-shift = <26>;
  133                 reg = <0x0200>;
  134         };
  135 
  136         eac_ick: eac_ick@210 {
  137                 #clock-cells = <0>;
  138                 compatible = "ti,omap3-interface-clock";
  139                 clocks = <&l4_ck>;
  140                 ti,bit-shift = <24>;
  141                 reg = <0x0210>;
  142         };
  143 
  144         eac_fck: eac_fck@200 {
  145                 #clock-cells = <0>;
  146                 compatible = "ti,wait-gate-clock";
  147                 clocks = <&func_96m_ck>;
  148                 ti,bit-shift = <24>;
  149                 reg = <0x0200>;
  150         };
  151 
  152         i2c1_fck: i2c1_fck@200 {
  153                 #clock-cells = <0>;
  154                 compatible = "ti,wait-gate-clock";
  155                 clocks = <&func_12m_ck>;
  156                 ti,bit-shift = <19>;
  157                 reg = <0x0200>;
  158         };
  159 
  160         i2c2_fck: i2c2_fck@200 {
  161                 #clock-cells = <0>;
  162                 compatible = "ti,wait-gate-clock";
  163                 clocks = <&func_12m_ck>;
  164                 ti,bit-shift = <20>;
  165                 reg = <0x0200>;
  166         };
  167 
  168         vlynq_ick: vlynq_ick@210 {
  169                 #clock-cells = <0>;
  170                 compatible = "ti,omap3-interface-clock";
  171                 clocks = <&core_l3_ck>;
  172                 ti,bit-shift = <3>;
  173                 reg = <0x0210>;
  174         };
  175 
  176         vlynq_gate_fck: vlynq_gate_fck@200 {
  177                 #clock-cells = <0>;
  178                 compatible = "ti,composite-gate-clock";
  179                 clocks = <&core_ck>;
  180                 ti,bit-shift = <3>;
  181                 reg = <0x0200>;
  182         };
  183 
  184         core_d18_ck: core_d18_ck {
  185                 #clock-cells = <0>;
  186                 compatible = "fixed-factor-clock";
  187                 clocks = <&core_ck>;
  188                 clock-mult = <1>;
  189                 clock-div = <18>;
  190         };
  191 
  192         vlynq_mux_fck: vlynq_mux_fck@240 {
  193                 #clock-cells = <0>;
  194                 compatible = "ti,composite-mux-clock";
  195                 clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
  196                 ti,bit-shift = <15>;
  197                 reg = <0x0240>;
  198         };
  199 
  200         vlynq_fck: vlynq_fck {
  201                 #clock-cells = <0>;
  202                 compatible = "ti,composite-clock";
  203                 clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;
  204         };
  205 };
  206 
  207 &prcm_clockdomains {
  208         gfx_clkdm: gfx_clkdm {
  209                 compatible = "ti,clockdomain";
  210                 clocks = <&gfx_ick>;
  211         };
  212 
  213         core_l3_clkdm: core_l3_clkdm {
  214                 compatible = "ti,clockdomain";
  215                 clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;
  216         };
  217 
  218         wkup_clkdm: wkup_clkdm {
  219                 compatible = "ti,clockdomain";
  220                 clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
  221                          <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
  222                          <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;
  223         };
  224 
  225         iva1_clkdm: iva1_clkdm {
  226                 compatible = "ti,clockdomain";
  227                 clocks = <&iva1_mpu_int_ifck>;
  228         };
  229 
  230         dss_clkdm: dss_clkdm {
  231                 compatible = "ti,clockdomain";
  232                 clocks = <&dss_ick>, <&dss_54m_fck>;
  233         };
  234 
  235         core_l4_clkdm: core_l4_clkdm {
  236                 compatible = "ti,clockdomain";
  237                 clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
  238                          <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
  239                          <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
  240                          <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,
  241                          <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
  242                          <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,
  243                          <&uart3_ick>, <&uart3_fck>, <&cam_ick>,
  244                          <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,
  245                          <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,
  246                          <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,
  247                          <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,
  248                          <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,
  249                          <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
  250                          <&pka_ick>;
  251         };
  252 };
  253 
  254 &func_96m_ck {
  255         compatible = "fixed-factor-clock";
  256         clocks = <&apll96_ck>;
  257         clock-mult = <1>;
  258         clock-div = <1>;
  259 };
  260 
  261 &dsp_div_fck {
  262         ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
  263 };
  264 
  265 &ssi_ssr_sst_div_fck {
  266         ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
  267 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/omap2420-clocks.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/omap2420-clocks.dtsi