omap2430-clocks.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0-only
    2 /*
    3  * Device Tree Source for OMAP2430 clock data
    4  *
    5  * Copyright (C) 2014 Texas Instruments, Inc.
    6  */
    7 
    8 &scm_clocks {
    9         mcbsp3_mux_fck: mcbsp3_mux_fck@78 {
   10                 #clock-cells = <0>;
   11                 compatible = "ti,composite-mux-clock";
   12                 clocks = <&func_96m_ck>, <&mcbsp_clks>;
   13                 reg = <0x78>;
   14         };
   15 
   16         mcbsp3_fck: mcbsp3_fck {
   17                 #clock-cells = <0>;
   18                 compatible = "ti,composite-clock";
   19                 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
   20         };
   21 
   22         mcbsp4_mux_fck: mcbsp4_mux_fck@78 {
   23                 #clock-cells = <0>;
   24                 compatible = "ti,composite-mux-clock";
   25                 clocks = <&func_96m_ck>, <&mcbsp_clks>;
   26                 ti,bit-shift = <2>;
   27                 reg = <0x78>;
   28         };
   29 
   30         mcbsp4_fck: mcbsp4_fck {
   31                 #clock-cells = <0>;
   32                 compatible = "ti,composite-clock";
   33                 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
   34         };
   35 
   36         mcbsp5_mux_fck: mcbsp5_mux_fck@78 {
   37                 #clock-cells = <0>;
   38                 compatible = "ti,composite-mux-clock";
   39                 clocks = <&func_96m_ck>, <&mcbsp_clks>;
   40                 ti,bit-shift = <4>;
   41                 reg = <0x78>;
   42         };
   43 
   44         mcbsp5_fck: mcbsp5_fck {
   45                 #clock-cells = <0>;
   46                 compatible = "ti,composite-clock";
   47                 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
   48         };
   49 };
   50 
   51 &prcm_clocks {
   52         iva2_1_gate_ick: iva2_1_gate_ick@800 {
   53                 #clock-cells = <0>;
   54                 compatible = "ti,composite-gate-clock";
   55                 clocks = <&dsp_fck>;
   56                 ti,bit-shift = <0>;
   57                 reg = <0x0800>;
   58         };
   59 
   60         iva2_1_div_ick: iva2_1_div_ick@840 {
   61                 #clock-cells = <0>;
   62                 compatible = "ti,composite-divider-clock";
   63                 clocks = <&dsp_fck>;
   64                 ti,bit-shift = <5>;
   65                 ti,max-div = <3>;
   66                 reg = <0x0840>;
   67                 ti,index-starts-at-one;
   68         };
   69 
   70         iva2_1_ick: iva2_1_ick {
   71                 #clock-cells = <0>;
   72                 compatible = "ti,composite-clock";
   73                 clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
   74         };
   75 
   76         mdm_gate_ick: mdm_gate_ick@c10 {
   77                 #clock-cells = <0>;
   78                 compatible = "ti,composite-interface-clock";
   79                 clocks = <&core_ck>;
   80                 ti,bit-shift = <0>;
   81                 reg = <0x0c10>;
   82         };
   83 
   84         mdm_div_ick: mdm_div_ick@c40 {
   85                 #clock-cells = <0>;
   86                 compatible = "ti,composite-divider-clock";
   87                 clocks = <&core_ck>;
   88                 reg = <0x0c40>;
   89                 ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
   90         };
   91 
   92         mdm_ick: mdm_ick {
   93                 #clock-cells = <0>;
   94                 compatible = "ti,composite-clock";
   95                 clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
   96         };
   97 
   98         mdm_osc_ck: mdm_osc_ck@c00 {
   99                 #clock-cells = <0>;
  100                 compatible = "ti,omap3-interface-clock";
  101                 clocks = <&osc_ck>;
  102                 ti,bit-shift = <1>;
  103                 reg = <0x0c00>;
  104         };
  105 
  106         mcbsp3_ick: mcbsp3_ick@214 {
  107                 #clock-cells = <0>;
  108                 compatible = "ti,omap3-interface-clock";
  109                 clocks = <&l4_ck>;
  110                 ti,bit-shift = <3>;
  111                 reg = <0x0214>;
  112         };
  113 
  114         mcbsp3_gate_fck: mcbsp3_gate_fck@204 {
  115                 #clock-cells = <0>;
  116                 compatible = "ti,composite-gate-clock";
  117                 clocks = <&mcbsp_clks>;
  118                 ti,bit-shift = <3>;
  119                 reg = <0x0204>;
  120         };
  121 
  122         mcbsp4_ick: mcbsp4_ick@214 {
  123                 #clock-cells = <0>;
  124                 compatible = "ti,omap3-interface-clock";
  125                 clocks = <&l4_ck>;
  126                 ti,bit-shift = <4>;
  127                 reg = <0x0214>;
  128         };
  129 
  130         mcbsp4_gate_fck: mcbsp4_gate_fck@204 {
  131                 #clock-cells = <0>;
  132                 compatible = "ti,composite-gate-clock";
  133                 clocks = <&mcbsp_clks>;
  134                 ti,bit-shift = <4>;
  135                 reg = <0x0204>;
  136         };
  137 
  138         mcbsp5_ick: mcbsp5_ick@214 {
  139                 #clock-cells = <0>;
  140                 compatible = "ti,omap3-interface-clock";
  141                 clocks = <&l4_ck>;
  142                 ti,bit-shift = <5>;
  143                 reg = <0x0214>;
  144         };
  145 
  146         mcbsp5_gate_fck: mcbsp5_gate_fck@204 {
  147                 #clock-cells = <0>;
  148                 compatible = "ti,composite-gate-clock";
  149                 clocks = <&mcbsp_clks>;
  150                 ti,bit-shift = <5>;
  151                 reg = <0x0204>;
  152         };
  153 
  154         mcspi3_ick: mcspi3_ick@214 {
  155                 #clock-cells = <0>;
  156                 compatible = "ti,omap3-interface-clock";
  157                 clocks = <&l4_ck>;
  158                 ti,bit-shift = <9>;
  159                 reg = <0x0214>;
  160         };
  161 
  162         mcspi3_fck: mcspi3_fck@204 {
  163                 #clock-cells = <0>;
  164                 compatible = "ti,wait-gate-clock";
  165                 clocks = <&func_48m_ck>;
  166                 ti,bit-shift = <9>;
  167                 reg = <0x0204>;
  168         };
  169 
  170         icr_ick: icr_ick@410 {
  171                 #clock-cells = <0>;
  172                 compatible = "ti,omap3-interface-clock";
  173                 clocks = <&sys_ck>;
  174                 ti,bit-shift = <6>;
  175                 reg = <0x0410>;
  176         };
  177 
  178         i2chs1_fck: i2chs1_fck@204 {
  179                 #clock-cells = <0>;
  180                 compatible = "ti,omap2430-interface-clock";
  181                 clocks = <&func_96m_ck>;
  182                 ti,bit-shift = <19>;
  183                 reg = <0x0204>;
  184         };
  185 
  186         i2chs2_fck: i2chs2_fck@204 {
  187                 #clock-cells = <0>;
  188                 compatible = "ti,omap2430-interface-clock";
  189                 clocks = <&func_96m_ck>;
  190                 ti,bit-shift = <20>;
  191                 reg = <0x0204>;
  192         };
  193 
  194         usbhs_ick: usbhs_ick@214 {
  195                 #clock-cells = <0>;
  196                 compatible = "ti,omap3-interface-clock";
  197                 clocks = <&core_l3_ck>;
  198                 ti,bit-shift = <6>;
  199                 reg = <0x0214>;
  200         };
  201 
  202         mmchs1_ick: mmchs1_ick@214 {
  203                 #clock-cells = <0>;
  204                 compatible = "ti,omap3-interface-clock";
  205                 clocks = <&l4_ck>;
  206                 ti,bit-shift = <7>;
  207                 reg = <0x0214>;
  208         };
  209 
  210         mmchs1_fck: mmchs1_fck@204 {
  211                 #clock-cells = <0>;
  212                 compatible = "ti,wait-gate-clock";
  213                 clocks = <&func_96m_ck>;
  214                 ti,bit-shift = <7>;
  215                 reg = <0x0204>;
  216         };
  217 
  218         mmchs2_ick: mmchs2_ick@214 {
  219                 #clock-cells = <0>;
  220                 compatible = "ti,omap3-interface-clock";
  221                 clocks = <&l4_ck>;
  222                 ti,bit-shift = <8>;
  223                 reg = <0x0214>;
  224         };
  225 
  226         mmchs2_fck: mmchs2_fck@204 {
  227                 #clock-cells = <0>;
  228                 compatible = "ti,wait-gate-clock";
  229                 clocks = <&func_96m_ck>;
  230                 ti,bit-shift = <8>;
  231                 reg = <0x0204>;
  232         };
  233 
  234         gpio5_ick: gpio5_ick@214 {
  235                 #clock-cells = <0>;
  236                 compatible = "ti,omap3-interface-clock";
  237                 clocks = <&l4_ck>;
  238                 ti,bit-shift = <10>;
  239                 reg = <0x0214>;
  240         };
  241 
  242         gpio5_fck: gpio5_fck@204 {
  243                 #clock-cells = <0>;
  244                 compatible = "ti,wait-gate-clock";
  245                 clocks = <&func_32k_ck>;
  246                 ti,bit-shift = <10>;
  247                 reg = <0x0204>;
  248         };
  249 
  250         mdm_intc_ick: mdm_intc_ick@214 {
  251                 #clock-cells = <0>;
  252                 compatible = "ti,omap3-interface-clock";
  253                 clocks = <&l4_ck>;
  254                 ti,bit-shift = <11>;
  255                 reg = <0x0214>;
  256         };
  257 
  258         mmchsdb1_fck: mmchsdb1_fck@204 {
  259                 #clock-cells = <0>;
  260                 compatible = "ti,wait-gate-clock";
  261                 clocks = <&func_32k_ck>;
  262                 ti,bit-shift = <16>;
  263                 reg = <0x0204>;
  264         };
  265 
  266         mmchsdb2_fck: mmchsdb2_fck@204 {
  267                 #clock-cells = <0>;
  268                 compatible = "ti,wait-gate-clock";
  269                 clocks = <&func_32k_ck>;
  270                 ti,bit-shift = <17>;
  271                 reg = <0x0204>;
  272         };
  273 };
  274 
  275 &prcm_clockdomains {
  276         gfx_clkdm: gfx_clkdm {
  277                 compatible = "ti,clockdomain";
  278                 clocks = <&gfx_ick>;
  279         };
  280 
  281         core_l3_clkdm: core_l3_clkdm {
  282                 compatible = "ti,clockdomain";
  283                 clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>;
  284         };
  285 
  286         wkup_clkdm: wkup_clkdm {
  287                 compatible = "ti,clockdomain";
  288                 clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
  289                          <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
  290                          <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>,
  291                          <&icr_ick>;
  292         };
  293 
  294         dss_clkdm: dss_clkdm {
  295                 compatible = "ti,clockdomain";
  296                 clocks = <&dss_ick>, <&dss_54m_fck>;
  297         };
  298 
  299         core_l4_clkdm: core_l4_clkdm {
  300                 compatible = "ti,clockdomain";
  301                 clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
  302                          <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
  303                          <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
  304                          <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
  305                          <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>,
  306                          <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
  307                          <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>,
  308                          <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>,
  309                          <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>,
  310                          <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>,
  311                          <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>,
  312                          <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>,
  313                          <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
  314                          <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>,
  315                          <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>,
  316                          <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>,
  317                          <&mmchsdb2_fck>;
  318         };
  319 
  320         mdm_clkdm: mdm_clkdm {
  321                 compatible = "ti,clockdomain";
  322                 clocks = <&mdm_osc_ck>;
  323         };
  324 };
  325 
  326 &func_96m_ck {
  327         compatible = "ti,mux-clock";
  328         clocks = <&apll96_ck>, <&alt_ck>;
  329         ti,bit-shift = <4>;
  330         reg = <0x0540>;
  331 };
  332 
  333 &dsp_div_fck {
  334         ti,max-div = <4>;
  335         ti,index-starts-at-one;
  336 };
  337 
  338 &ssi_ssr_sst_div_fck {
  339         ti,max-div = <5>;
  340         ti,index-starts-at-one;
  341 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/omap2430-clocks.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/omap2430-clocks.dtsi
