Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/omap3-evm-processor-common.dtsi
Version:
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1 /* 2 * Common support for omap3 EVM 35xx/37xx processor modules 3 */ 4 5 / { 6 memory@80000000 { 7 device_type = "memory"; 8 reg = <0x80000000 0x10000000>; /* 256 MB */ 9 }; 10 11 wl12xx_vmmc: wl12xx_vmmc { 12 pinctrl-names = "default"; 13 pinctrl-0 = <&wl12xx_gpio>; 14 }; 15 }; 16 17 &dss { 18 vdds_dsi-supply = <&vpll2>; 19 vdda_video-supply = <&lcd_3v3>; 20 pinctrl-names = "default"; 21 pinctrl-0 = < 22 &dss_dpi_pins1 23 &dss_dpi_pins2 24 >; 25 }; 26 27 &hsusb2_phy { 28 pinctrl-names = "default"; 29 pinctrl-0 = <&ehci_phy_pins>; 30 }; 31 32 &omap3_pmx_core { 33 pinctrl-names = "default"; 34 pinctrl-0 = <&on_board_gpio_61 &hsusb2_pins>; 35 36 dss_dpi_pins1: pinmux_dss_dpi_pins2 { 37 pinctrl-single,pins = < 38 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 39 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 40 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 41 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 42 43 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ 44 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ 45 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ 46 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ 47 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ 48 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ 49 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ 50 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ 51 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ 52 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ 53 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ 54 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ 55 56 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ 57 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ 58 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ 59 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ 60 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ 61 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ 62 >; 63 }; 64 65 mmc1_pins: pinmux_mmc1_pins { 66 pinctrl-single,pins = < 67 OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ 68 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ 69 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ 70 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 71 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 72 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ 73 OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ 74 OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ 75 OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ 76 OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ 77 >; 78 }; 79 80 /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ 81 mmc2_pins: pinmux_mmc2_pins { 82 pinctrl-single,pins = < 83 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ 84 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ 85 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ 86 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ 87 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ 88 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ 89 OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat4.sdmmc2_dir_dat0 */ 90 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat5.sdmmc2_dir_dat1 */ 91 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* sdmmc2_dat6.sdmmc2_dir_cmd */ 92 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* sdmmc2_dat7.sdmmc2_clkin */ 93 >; 94 }; 95 96 uart3_pins: pinmux_uart3_pins { 97 pinctrl-single,pins = < 98 OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ 99 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ 100 >; 101 }; 102 103 /* Devices are routed with gpmc_nbe1.gpio_61 to on-board devices */ 104 on_board_gpio_61: pinmux_ehci_port_select_pins { 105 pinctrl-single,pins = < 106 OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) 107 >; 108 }; 109 110 /* Used by OHCI and EHCI. OHCI won't work without external phy */ 111 hsusb2_pins: pinmux_hsusb2_pins { 112 pinctrl-single,pins = < 113 114 /* mcspi1_cs3.hsusb2_data2 */ 115 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) 116 117 /* mcspi2_clk.hsusb2_data7 */ 118 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) 119 120 /* mcspi2_simo.hsusb2_data4 */ 121 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) 122 123 /* mcspi2_somi.hsusb2_data5 */ 124 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) 125 126 /* mcspi2_cs0.hsusb2_data6 */ 127 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) 128 129 /* mcspi2_cs1.hsusb2_data3 */ 130 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) 131 >; 132 }; 133 134 /* 135 * Note that gpio_150 pulled high with internal pull to prevent wlcore 136 * reset on return from off mode in idle. 137 */ 138 wl12xx_gpio: pinmux_wl12xx_gpio { 139 pinctrl-single,pins = < 140 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_cts.gpio_150 */ 141 OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ 142 >; 143 }; 144 145 smsc911x_pins: pinmux_smsc911x_pins { 146 pinctrl-single,pins = < 147 OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ 148 >; 149 }; 150 }; 151 152 &omap3_pmx_wkup { 153 dss_dpi_pins2: pinmux_dss_dpi_pins1 { 154 pinctrl-single,pins = < 155 OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ 156 OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ 157 OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ 158 OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ 159 OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ 160 OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ 161 >; 162 }; 163 }; 164 165 &mmc1 { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&mmc1_pins>; 168 }; 169 170 &mmc2 { 171 pinctrl-names = "default"; 172 pinctrl-0 = <&mmc2_pins>; 173 }; 174 175 &mmc3 { 176 status = "disabled"; 177 }; 178 179 &uart1 { 180 interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; 181 }; 182 183 &uart2 { 184 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; 185 }; 186 187 &uart3 { 188 interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; 189 pinctrl-names = "default"; 190 pinctrl-0 = <&uart3_pins>; 191 }; 192 193 /* 194 * GPIO_61 (nUSB2_EN_1V8) must be low to enable on-board EHCI USB2 interface 195 * for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V. 196 */ 197 &gpio2 { 198 en-usb2-port-hog { 199 gpio-hog; 200 gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */ 201 output-low; 202 line-name = "enable usb2 port"; 203 }; 204 }; 205 206 /* T2_GPIO_2 low to route GPIO_61 to on-board devices */ 207 &twl_gpio { 208 en_on_board_gpio_61 { 209 gpio-hog; 210 gpios = <2 GPIO_ACTIVE_HIGH>; 211 output-low; 212 line-name = "en_hsusb2_clk"; 213 }; 214 }; 215 216 &gpmc { 217 ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ 218 <5 0 0x2c000000 0x01000000>; /* CS5: 16MB for LAN9220 */ 219 220 ethernet@gpmc { 221 pinctrl-names = "default"; 222 pinctrl-0 = <&smsc911x_pins>; 223 }; 224 };
Cache object: f44732d7c69d5e58196739fd52cc87c7
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