omap3430es1-clocks.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0-only
    2 /*
    3  * Device Tree Source for OMAP3430 ES1 clock data
    4  *
    5  * Copyright (C) 2013 Texas Instruments, Inc.
    6  */
    7 &cm_clocks {
    8         gfx_l3_ck: gfx_l3_ck@b10 {
    9                 #clock-cells = <0>;
   10                 compatible = "ti,wait-gate-clock";
   11                 clocks = <&l3_ick>;
   12                 reg = <0x0b10>;
   13                 ti,bit-shift = <0>;
   14         };
   15 
   16         gfx_l3_fck: gfx_l3_fck@b40 {
   17                 #clock-cells = <0>;
   18                 compatible = "ti,divider-clock";
   19                 clocks = <&l3_ick>;
   20                 ti,max-div = <7>;
   21                 reg = <0x0b40>;
   22                 ti,index-starts-at-one;
   23         };
   24 
   25         gfx_l3_ick: gfx_l3_ick {
   26                 #clock-cells = <0>;
   27                 compatible = "fixed-factor-clock";
   28                 clocks = <&gfx_l3_ck>;
   29                 clock-mult = <1>;
   30                 clock-div = <1>;
   31         };
   32 
   33         gfx_cg1_ck: gfx_cg1_ck@b00 {
   34                 #clock-cells = <0>;
   35                 compatible = "ti,wait-gate-clock";
   36                 clocks = <&gfx_l3_fck>;
   37                 reg = <0x0b00>;
   38                 ti,bit-shift = <1>;
   39         };
   40 
   41         gfx_cg2_ck: gfx_cg2_ck@b00 {
   42                 #clock-cells = <0>;
   43                 compatible = "ti,wait-gate-clock";
   44                 clocks = <&gfx_l3_fck>;
   45                 reg = <0x0b00>;
   46                 ti,bit-shift = <2>;
   47         };
   48 
   49         clock@a00 {
   50                 compatible = "ti,clksel";
   51                 reg = <0xa00>;
   52                 #clock-cells = <2>;
   53                 #address-cells = <0>;
   54 
   55                 d2d_26m_fck: clock-d2d-26m-fck {
   56                         #clock-cells = <0>;
   57                         compatible = "ti,wait-gate-clock";
   58                         clock-output-names = "d2d_26m_fck";
   59                         clocks = <&sys_ck>;
   60                         ti,bit-shift = <3>;
   61                 };
   62 
   63                 fshostusb_fck: clock-fshostusb-fck {
   64                         #clock-cells = <0>;
   65                         compatible = "ti,wait-gate-clock";
   66                         clock-output-names = "fshostusb_fck";
   67                         clocks = <&core_48m_fck>;
   68                         ti,bit-shift = <5>;
   69                 };
   70 
   71                 ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 {
   72                         #clock-cells = <0>;
   73                         compatible = "ti,composite-no-wait-gate-clock";
   74                         clock-output-names = "ssi_ssr_gate_fck_3430es1";
   75                         clocks = <&corex2_fck>;
   76                         ti,bit-shift = <0>;
   77                 };
   78         };
   79 
   80         clock@a40 {
   81                 compatible = "ti,clksel";
   82                 reg = <0xa40>;
   83                 #clock-cells = <2>;
   84                 #address-cells = <0>;
   85 
   86                 ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1 {
   87                         #clock-cells = <0>;
   88                         compatible = "ti,composite-divider-clock";
   89                         clock-output-names = "ssi_ssr_div_fck_3430es1";
   90                         clocks = <&corex2_fck>;
   91                         ti,bit-shift = <8>;
   92                         ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
   93                 };
   94 
   95                 usb_l4_div_ick: clock-usb-l4-div-ick {
   96                         #clock-cells = <0>;
   97                         compatible = "ti,composite-divider-clock";
   98                         clock-output-names = "usb_l4_div_ick";
   99                         clocks = <&l4_ick>;
  100                         ti,bit-shift = <4>;
  101                         ti,max-div = <1>;
  102                         ti,index-starts-at-one;
  103                 };
  104         };
  105 
  106         ssi_ssr_fck: ssi_ssr_fck_3430es1 {
  107                 #clock-cells = <0>;
  108                 compatible = "ti,composite-clock";
  109                 clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
  110         };
  111 
  112         ssi_sst_fck: ssi_sst_fck_3430es1 {
  113                 #clock-cells = <0>;
  114                 compatible = "fixed-factor-clock";
  115                 clocks = <&ssi_ssr_fck>;
  116                 clock-mult = <1>;
  117                 clock-div = <2>;
  118         };
  119 
  120         clock@a10 {
  121                 compatible = "ti,clksel";
  122                 reg = <0xa10>;
  123                 #clock-cells = <2>;
  124                 #address-cells = <0>;
  125 
  126                 hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1 {
  127                         #clock-cells = <0>;
  128                         compatible = "ti,omap3-no-wait-interface-clock";
  129                         clock-output-names = "hsotgusb_ick_3430es1";
  130                         clocks = <&core_l3_ick>;
  131                         ti,bit-shift = <4>;
  132                 };
  133 
  134                 fac_ick: clock-fac-ick {
  135                         #clock-cells = <0>;
  136                         compatible = "ti,omap3-interface-clock";
  137                         clock-output-names = "fac_ick";
  138                         clocks = <&core_l4_ick>;
  139                         ti,bit-shift = <8>;
  140                 };
  141 
  142                 ssi_ick: clock-ssi-ick-3430es1 {
  143                         #clock-cells = <0>;
  144                         compatible = "ti,omap3-no-wait-interface-clock";
  145                         clock-output-names = "ssi_ick_3430es1";
  146                         clocks = <&ssi_l4_ick>;
  147                         ti,bit-shift = <0>;
  148                 };
  149 
  150                 usb_l4_gate_ick: clock-usb-l4-gate-ick {
  151                         #clock-cells = <0>;
  152                         compatible = "ti,composite-interface-clock";
  153                         clock-output-names = "usb_l4_gate_ick";
  154                         clocks = <&l4_ick>;
  155                         ti,bit-shift = <5>;
  156                 };
  157         };
  158 
  159         ssi_l4_ick: ssi_l4_ick {
  160                 #clock-cells = <0>;
  161                 compatible = "fixed-factor-clock";
  162                 clocks = <&l4_ick>;
  163                 clock-mult = <1>;
  164                 clock-div = <1>;
  165         };
  166 
  167         usb_l4_ick: usb_l4_ick {
  168                 #clock-cells = <0>;
  169                 compatible = "ti,composite-clock";
  170                 clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
  171         };
  172 
  173         clock@e00 {
  174                 compatible = "ti,clksel";
  175                 reg = <0xe00>;
  176                 #clock-cells = <2>;
  177                 #address-cells = <0>;
  178 
  179                 dss1_alwon_fck: clock-dss1-alwon-fck-3430es1 {
  180                         #clock-cells = <0>;
  181                         compatible = "ti,gate-clock";
  182                         clock-output-names = "dss1_alwon_fck_3430es1";
  183                         clocks = <&dpll4_m4x2_ck>;
  184                         ti,bit-shift = <0>;
  185                         ti,set-rate-parent;
  186                 };
  187         };
  188 
  189         dss_ick: dss_ick_3430es1@e10 {
  190                 #clock-cells = <0>;
  191                 compatible = "ti,omap3-no-wait-interface-clock";
  192                 clocks = <&l4_ick>;
  193                 reg = <0x0e10>;
  194                 ti,bit-shift = <0>;
  195         };
  196 };
  197 
  198 &cm_clockdomains {
  199         core_l3_clkdm: core_l3_clkdm {
  200                 compatible = "ti,clockdomain";
  201                 clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
  202         };
  203 
  204         gfx_3430es1_clkdm: gfx_3430es1_clkdm {
  205                 compatible = "ti,clockdomain";
  206                 clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
  207         };
  208 
  209         dss_clkdm: dss_clkdm {
  210                 compatible = "ti,clockdomain";
  211                 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
  212                          <&dss1_alwon_fck>, <&dss_ick>;
  213         };
  214 
  215         d2d_clkdm: d2d_clkdm {
  216                 compatible = "ti,clockdomain";
  217                 clocks = <&d2d_26m_fck>;
  218         };
  219 
  220         core_l4_clkdm: core_l4_clkdm {
  221                 compatible = "ti,clockdomain";
  222                 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
  223                          <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
  224                          <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
  225                          <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
  226                          <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
  227                          <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
  228                          <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
  229                          <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
  230                          <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
  231                          <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>;
  232         };
  233 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/omap3430es1-clocks.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/omap3430es1-clocks.dtsi