prima2.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0-or-later
    2 /*
    3  * DTS file for CSR SiRFprimaII SoC
    4  *
    5  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
    6  */
    7 
    8 / {
    9         compatible = "sirf,prima2";
   10         #address-cells = <1>;
   11         #size-cells = <1>;
   12         interrupt-parent = <&intc>;
   13 
   14         cpus {
   15                 #address-cells = <1>;
   16                 #size-cells = <0>;
   17 
   18                 cpu@0 {
   19                         compatible = "arm,cortex-a9";
   20                         device_type = "cpu";
   21                         reg = <0x0>;
   22                         d-cache-line-size = <32>;
   23                         i-cache-line-size = <32>;
   24                         d-cache-size = <32768>;
   25                         i-cache-size = <32768>;
   26                         /* from bootloader */
   27                         timebase-frequency = <0>;
   28                         bus-frequency = <0>;
   29                         clock-frequency = <0>;
   30                         clocks = <&clks 12>;
   31                         operating-points = <
   32                                 /* kHz    uV */
   33                                 200000  1025000
   34                                 400000  1025000
   35                                 664000  1050000
   36                                 800000  1100000
   37                         >;
   38                         clock-latency = <150000>;
   39                 };
   40         };
   41 
   42         arm-pmu {
   43                 compatible = "arm,cortex-a9-pmu";
   44                 interrupts = <29>;
   45         };
   46 
   47         axi {
   48                 compatible = "simple-bus";
   49                 #address-cells = <1>;
   50                 #size-cells = <1>;
   51                 ranges = <0x40000000 0x40000000 0x80000000>;
   52 
   53                 cache-controller@80040000 {
   54                         compatible = "arm,pl310-cache";
   55                         reg = <0x80040000 0x1000>;
   56                         interrupts = <59>;
   57                         arm,tag-latency = <1 1 1>;
   58                         arm,data-latency = <1 1 1>;
   59                         arm,filter-ranges = <0 0x40000000>;
   60                 };
   61 
   62                 intc: interrupt-controller@80020000 {
   63                         #interrupt-cells = <1>;
   64                         interrupt-controller;
   65                         compatible = "sirf,prima2-intc";
   66                         reg = <0x80020000 0x1000>;
   67                 };
   68 
   69                 sys-iobg {
   70                         compatible = "simple-bus";
   71                         #address-cells = <1>;
   72                         #size-cells = <1>;
   73                         ranges = <0x88000000 0x88000000 0x40000>;
   74 
   75                         clks: clock-controller@88000000 {
   76                                 compatible = "sirf,prima2-clkc";
   77                                 reg = <0x88000000 0x1000>;
   78                                 interrupts = <3>;
   79                                 #clock-cells = <1>;
   80                         };
   81 
   82                         rstc: reset-controller@88010000 {
   83                                 compatible = "sirf,prima2-rstc";
   84                                 reg = <0x88010000 0x1000>;
   85                                 #reset-cells = <1>;
   86                         };
   87 
   88                         rsc-controller@88020000 {
   89                                 compatible = "sirf,prima2-rsc";
   90                                 reg = <0x88020000 0x1000>;
   91                         };
   92 
   93                         cphifbg@88030000 {
   94                                 compatible = "sirf,prima2-cphifbg";
   95                                 reg = <0x88030000 0x1000>;
   96                                 clocks = <&clks 42>;
   97                         };
   98                 };
   99 
  100                 mem-iobg {
  101                         compatible = "simple-bus";
  102                         #address-cells = <1>;
  103                         #size-cells = <1>;
  104                         ranges = <0x90000000 0x90000000 0x10000>;
  105 
  106                         memory-controller@90000000 {
  107                                 compatible = "sirf,prima2-memc";
  108                                 reg = <0x90000000 0x2000>;
  109                                 interrupts = <27>;
  110                                 clocks = <&clks 5>;
  111                         };
  112 
  113                         memc-monitor {
  114                                 compatible = "sirf,prima2-memcmon";
  115                                 reg = <0x90002000 0x200>;
  116                                 interrupts = <4>;
  117                                 clocks = <&clks 32>;
  118                         };
  119                 };
  120 
  121                 disp-iobg {
  122                         compatible = "simple-bus";
  123                         #address-cells = <1>;
  124                         #size-cells = <1>;
  125                         ranges = <0x90010000 0x90010000 0x30000>;
  126 
  127                         display@90010000 {
  128                                 compatible = "sirf,prima2-lcd";
  129                                 reg = <0x90010000 0x20000>;
  130                                 interrupts = <30>;
  131                         };
  132 
  133                         vpp@90020000 {
  134                                 compatible = "sirf,prima2-vpp";
  135                                 reg = <0x90020000 0x10000>;
  136                                 interrupts = <31>;
  137                                 clocks = <&clks 35>;
  138                                 resets = <&rstc 6>;
  139                         };
  140                 };
  141 
  142                 graphics-iobg {
  143                         compatible = "simple-bus";
  144                         #address-cells = <1>;
  145                         #size-cells = <1>;
  146                         ranges = <0x98000000 0x98000000 0x8000000>;
  147 
  148                         graphics@98000000 {
  149                                 compatible = "powervr,sgx531";
  150                                 reg = <0x98000000 0x8000000>;
  151                                 interrupts = <6>;
  152                                 clocks = <&clks 32>;
  153                         };
  154                 };
  155 
  156                 multimedia-iobg {
  157                         compatible = "simple-bus";
  158                         #address-cells = <1>;
  159                         #size-cells = <1>;
  160                         ranges = <0xa0000000 0xa0000000 0x8000000>;
  161 
  162                         multimedia@a0000000 {
  163                                 compatible = "sirf,prima2-video-codec";
  164                                 reg = <0xa0000000 0x8000000>;
  165                                 interrupts = <5>;
  166                                 clocks = <&clks 33>;
  167                         };
  168                 };
  169 
  170                 dsp-iobg {
  171                         compatible = "simple-bus";
  172                         #address-cells = <1>;
  173                         #size-cells = <1>;
  174                         ranges = <0xa8000000 0xa8000000 0x2000000>;
  175 
  176                         dspif@a8000000 {
  177                                 compatible = "sirf,prima2-dspif";
  178                                 reg = <0xa8000000 0x10000>;
  179                                 interrupts = <9>;
  180                                 resets = <&rstc 1>;
  181                         };
  182 
  183                         gps@a8010000 {
  184                                 compatible = "sirf,prima2-gps";
  185                                 reg = <0xa8010000 0x10000>;
  186                                 interrupts = <7>;
  187                                 clocks = <&clks 9>;
  188                                 resets = <&rstc 2>;
  189                         };
  190 
  191                         dsp@a9000000 {
  192                                 compatible = "sirf,prima2-dsp";
  193                                 reg = <0xa9000000 0x1000000>;
  194                                 interrupts = <8>;
  195                                 clocks = <&clks 8>;
  196                                 resets = <&rstc 0>;
  197                         };
  198                 };
  199 
  200                 peri-iobg {
  201                         compatible = "simple-bus";
  202                         #address-cells = <1>;
  203                         #size-cells = <1>;
  204                         ranges = <0xb0000000 0xb0000000 0x180000>,
  205                                <0x56000000 0x56000000 0x1b00000>;
  206 
  207                         timer@b0020000 {
  208                                 compatible = "sirf,prima2-tick";
  209                                 reg = <0xb0020000 0x1000>;
  210                                 interrupts = <0>;
  211                                 clocks = <&clks 11>;
  212                         };
  213 
  214                         nand@b0030000 {
  215                                 compatible = "sirf,prima2-nand";
  216                                 reg = <0xb0030000 0x10000>;
  217                                 interrupts = <41>;
  218                                 clocks = <&clks 26>;
  219                         };
  220 
  221                         audio@b0040000 {
  222                                 compatible = "sirf,prima2-audio";
  223                                 reg = <0xb0040000 0x10000>;
  224                                 interrupts = <35>;
  225                                 clocks = <&clks 27>;
  226                         };
  227 
  228                         uart0: uart@b0050000 {
  229                                 cell-index = <0>;
  230                                 compatible = "sirf,prima2-uart";
  231                                 reg = <0xb0050000 0x1000>;
  232                                 interrupts = <17>;
  233                                 fifosize = <128>;
  234                                 clocks = <&clks 13>;
  235                                 dmas = <&dmac1 5>, <&dmac0 2>;
  236                                 dma-names = "rx", "tx";
  237                         };
  238 
  239                         uart1: uart@b0060000 {
  240                                 cell-index = <1>;
  241                                 compatible = "sirf,prima2-uart";
  242                                 reg = <0xb0060000 0x1000>;
  243                                 interrupts = <18>;
  244                                 fifosize = <32>;
  245                                 clocks = <&clks 14>;
  246                         };
  247 
  248                         uart2: uart@b0070000 {
  249                                 cell-index = <2>;
  250                                 compatible = "sirf,prima2-uart";
  251                                 reg = <0xb0070000 0x1000>;
  252                                 interrupts = <19>;
  253                                 fifosize = <128>;
  254                                 clocks = <&clks 15>;
  255                                 dmas = <&dmac0 6>, <&dmac0 7>;
  256                                 dma-names = "rx", "tx";
  257                         };
  258 
  259                         usp0: usp@b0080000 {
  260                                 cell-index = <0>;
  261                                 compatible = "sirf,prima2-usp";
  262                                 reg = <0xb0080000 0x10000>;
  263                                 interrupts = <20>;
  264                                 fifosize = <128>;
  265                                 clocks = <&clks 28>;
  266                                 dmas = <&dmac1 1>, <&dmac1 2>;
  267                                 dma-names = "rx", "tx";
  268                         };
  269 
  270                         usp1: usp@b0090000 {
  271                                 cell-index = <1>;
  272                                 compatible = "sirf,prima2-usp";
  273                                 reg = <0xb0090000 0x10000>;
  274                                 interrupts = <21>;
  275                                 fifosize = <128>;
  276                                 clocks = <&clks 29>;
  277                                 dmas = <&dmac0 14>, <&dmac0 15>;
  278                                 dma-names = "rx", "tx";
  279                         };
  280 
  281                         usp2: usp@b00a0000 {
  282                                 cell-index = <2>;
  283                                 compatible = "sirf,prima2-usp";
  284                                 reg = <0xb00a0000 0x10000>;
  285                                 interrupts = <22>;
  286                                 fifosize = <128>;
  287                                 clocks = <&clks 30>;
  288                                 dmas = <&dmac0 10>, <&dmac0 11>;
  289                                 dma-names = "rx", "tx";
  290                         };
  291 
  292                         dmac0: dma-controller@b00b0000 {
  293                                 cell-index = <0>;
  294                                 compatible = "sirf,prima2-dmac";
  295                                 reg = <0xb00b0000 0x10000>;
  296                                 interrupts = <12>;
  297                                 clocks = <&clks 24>;
  298                                 #dma-cells = <1>;
  299                         };
  300 
  301                         dmac1: dma-controller@b0160000 {
  302                                 cell-index = <1>;
  303                                 compatible = "sirf,prima2-dmac";
  304                                 reg = <0xb0160000 0x10000>;
  305                                 interrupts = <13>;
  306                                 clocks = <&clks 25>;
  307                                 #dma-cells = <1>;
  308                         };
  309 
  310                         vip@b00C0000 {
  311                                 compatible = "sirf,prima2-vip";
  312                                 reg = <0xb00C0000 0x10000>;
  313                                 clocks = <&clks 31>;
  314                                 interrupts = <14>;
  315                                 sirf,vip-dma-rx-channel = <16>;
  316                         };
  317 
  318                         spi0: spi@b00d0000 {
  319                                 cell-index = <0>;
  320                                 compatible = "sirf,prima2-spi";
  321                                 reg = <0xb00d0000 0x10000>;
  322                                 interrupts = <15>;
  323                                 sirf,spi-num-chipselects = <1>;
  324                                 dmas = <&dmac1 9>,
  325                                      <&dmac1 4>;
  326                                 dma-names = "rx", "tx";
  327                                 #address-cells = <1>;
  328                                 #size-cells = <0>;
  329                                 clocks = <&clks 19>;
  330                                 status = "disabled";
  331                         };
  332 
  333                         spi1: spi@b0170000 {
  334                                 cell-index = <1>;
  335                                 compatible = "sirf,prima2-spi";
  336                                 reg = <0xb0170000 0x10000>;
  337                                 interrupts = <16>;
  338                                 sirf,spi-num-chipselects = <1>;
  339                                 dmas = <&dmac0 12>,
  340                                      <&dmac0 13>;
  341                                 dma-names = "rx", "tx";
  342                                 #address-cells = <1>;
  343                                 #size-cells = <0>;
  344                                 clocks = <&clks 20>;
  345                                 status = "disabled";
  346                         };
  347 
  348                         i2c0: i2c@b00e0000 {
  349                                 cell-index = <0>;
  350                                 compatible = "sirf,prima2-i2c";
  351                                 reg = <0xb00e0000 0x10000>;
  352                                 interrupts = <24>;
  353                                 clocks = <&clks 17>;
  354                                 #address-cells = <1>;
  355                                 #size-cells = <0>;
  356                         };
  357 
  358                         i2c1: i2c@b00f0000 {
  359                                 cell-index = <1>;
  360                                 compatible = "sirf,prima2-i2c";
  361                                 reg = <0xb00f0000 0x10000>;
  362                                 interrupts = <25>;
  363                                 clocks = <&clks 18>;
  364                                 #address-cells = <1>;
  365                                 #size-cells = <0>;
  366                         };
  367 
  368                         tsc@b0110000 {
  369                                 compatible = "sirf,prima2-tsc";
  370                                 reg = <0xb0110000 0x10000>;
  371                                 interrupts = <33>;
  372                                 clocks = <&clks 16>;
  373                         };
  374 
  375                         gpio: pinctrl@b0120000 {
  376                                 #gpio-cells = <2>;
  377                                 #interrupt-cells = <2>;
  378                                 compatible = "sirf,prima2-pinctrl";
  379                                 reg = <0xb0120000 0x10000>;
  380                                 interrupts = <43 44 45 46 47>;
  381                                 gpio-controller;
  382                                 interrupt-controller;
  383 
  384                                 lcd_16pins_a: lcd0@0 {
  385                                         lcd {
  386                                                 sirf,pins = "lcd_16bitsgrp";
  387                                                 sirf,function = "lcd_16bits";
  388                                         };
  389                                 };
  390                                 lcd_18pins_a: lcd0@1 {
  391                                         lcd {
  392                                                 sirf,pins = "lcd_18bitsgrp";
  393                                                 sirf,function = "lcd_18bits";
  394                                         };
  395                                 };
  396                                 lcd_24pins_a: lcd0@2 {
  397                                         lcd {
  398                                                 sirf,pins = "lcd_24bitsgrp";
  399                                                 sirf,function = "lcd_24bits";
  400                                         };
  401                                 };
  402                                 lcdrom_pins_a: lcdrom0@0 {
  403                                         lcd {
  404                                                 sirf,pins = "lcdromgrp";
  405                                                 sirf,function = "lcdrom";
  406                                         };
  407                                 };
  408                                 uart0_pins_a: uart0@0 {
  409                                         uart {
  410                                                 sirf,pins = "uart0grp";
  411                                                 sirf,function = "uart0";
  412                                         };
  413                                 };
  414                                 uart0_noflow_pins_a: uart0@1 {
  415                                         uart {
  416                                                 sirf,pins = "uart0_nostreamctrlgrp";
  417                                                 sirf,function = "uart0_nostreamctrl";
  418                                         };
  419                                 };
  420                                 uart1_pins_a: uart1@0 {
  421                                         uart {
  422                                                 sirf,pins = "uart1grp";
  423                                                 sirf,function = "uart1";
  424                                         };
  425                                 };
  426                                 uart2_pins_a: uart2@0 {
  427                                         uart {
  428                                                 sirf,pins = "uart2grp";
  429                                                 sirf,function = "uart2";
  430                                         };
  431                                 };
  432                                 uart2_noflow_pins_a: uart2@1 {
  433                                         uart {
  434                                                 sirf,pins = "uart2_nostreamctrlgrp";
  435                                                 sirf,function = "uart2_nostreamctrl";
  436                                         };
  437                                 };
  438                                 spi0_pins_a: spi0@0 {
  439                                         spi {
  440                                                 sirf,pins = "spi0grp";
  441                                                 sirf,function = "spi0";
  442                                         };
  443                                 };
  444                                 spi1_pins_a: spi1@0 {
  445                                         spi {
  446                                                 sirf,pins = "spi1grp";
  447                                                 sirf,function = "spi1";
  448                                         };
  449                                 };
  450                                 i2c0_pins_a: i2c0@0 {
  451                                         i2c {
  452                                                 sirf,pins = "i2c0grp";
  453                                                 sirf,function = "i2c0";
  454                                         };
  455                                 };
  456                                 i2c1_pins_a: i2c1@0 {
  457                                         i2c {
  458                                                 sirf,pins = "i2c1grp";
  459                                                 sirf,function = "i2c1";
  460                                         };
  461                                 };
  462                                 pwm0_pins_a: pwm0@0 {
  463                                         pwm {
  464                                                 sirf,pins = "pwm0grp";
  465                                                 sirf,function = "pwm0";
  466                                         };
  467                                 };
  468                                 pwm1_pins_a: pwm1@0 {
  469                                         pwm {
  470                                                 sirf,pins = "pwm1grp";
  471                                                 sirf,function = "pwm1";
  472                                         };
  473                                 };
  474                                 pwm2_pins_a: pwm2@0 {
  475                                         pwm {
  476                                                 sirf,pins = "pwm2grp";
  477                                                 sirf,function = "pwm2";
  478                                         };
  479                                 };
  480                                 pwm3_pins_a: pwm3@0 {
  481                                         pwm {
  482                                                 sirf,pins = "pwm3grp";
  483                                                 sirf,function = "pwm3";
  484                                         };
  485                                 };
  486                                 gps_pins_a: gps@0 {
  487                                         gps {
  488                                                 sirf,pins = "gpsgrp";
  489                                                 sirf,function = "gps";
  490                                         };
  491                                 };
  492                                 vip_pins_a: vip@0 {
  493                                         vip {
  494                                                 sirf,pins = "vipgrp";
  495                                                 sirf,function = "vip";
  496                                         };
  497                                 };
  498                                 sdmmc0_pins_a: sdmmc0@0 {
  499                                         sdmmc0 {
  500                                                 sirf,pins = "sdmmc0grp";
  501                                                 sirf,function = "sdmmc0";
  502                                         };
  503                                 };
  504                                 sdmmc1_pins_a: sdmmc1@0 {
  505                                         sdmmc1 {
  506                                                 sirf,pins = "sdmmc1grp";
  507                                                 sirf,function = "sdmmc1";
  508                                         };
  509                                 };
  510                                 sdmmc2_pins_a: sdmmc2@0 {
  511                                         sdmmc2 {
  512                                                 sirf,pins = "sdmmc2grp";
  513                                                 sirf,function = "sdmmc2";
  514                                         };
  515                                 };
  516                                 sdmmc3_pins_a: sdmmc3@0 {
  517                                         sdmmc3 {
  518                                                 sirf,pins = "sdmmc3grp";
  519                                                 sirf,function = "sdmmc3";
  520                                         };
  521                                 };
  522                                 sdmmc4_pins_a: sdmmc4@0 {
  523                                         sdmmc4 {
  524                                                 sirf,pins = "sdmmc4grp";
  525                                                 sirf,function = "sdmmc4";
  526                                         };
  527                                 };
  528                                 sdmmc5_pins_a: sdmmc5@0 {
  529                                         sdmmc5 {
  530                                                 sirf,pins = "sdmmc5grp";
  531                                                 sirf,function = "sdmmc5";
  532                                         };
  533                                 };
  534                                 i2s_mclk_pins_a: i2s_mclk@0 {
  535                                         i2s_mclk {
  536                                                 sirf,pins = "i2smclkgrp";
  537                                                 sirf,function = "i2s_mclk";
  538                                         };
  539                                 };
  540                                 i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
  541                                         i2s_ext_clk_input {
  542                                                 sirf,pins = "i2s_ext_clk_inputgrp";
  543                                                 sirf,function = "i2s_ext_clk_input";
  544                                         };
  545                                 };
  546                                 i2s_pins_a: i2s@0 {
  547                                         i2s {
  548                                                 sirf,pins = "i2sgrp";
  549                                                 sirf,function = "i2s";
  550                                         };
  551                                 };
  552                                 i2s_no_din_pins_a: i2s_no_din@0 {
  553                                         i2s_no_din {
  554                                                 sirf,pins = "i2s_no_dingrp";
  555                                                 sirf,function = "i2s_no_din";
  556                                         };
  557                                 };
  558                                 i2s_6chn_pins_a: i2s_6chn@0 {
  559                                         i2s_6chn {
  560                                                 sirf,pins = "i2s_6chngrp";
  561                                                 sirf,function = "i2s_6chn";
  562                                         };
  563                                 };
  564                                 ac97_pins_a: ac97@0 {
  565                                         ac97 {
  566                                                 sirf,pins = "ac97grp";
  567                                                 sirf,function = "ac97";
  568                                         };
  569                                 };
  570                                 nand_pins_a: nand@0 {
  571                                         nand {
  572                                                 sirf,pins = "nandgrp";
  573                                                 sirf,function = "nand";
  574                                         };
  575                                 };
  576                                 usp0_pins_a: usp0@0 {
  577                                         usp0 {
  578                                                 sirf,pins = "usp0grp";
  579                                                 sirf,function = "usp0";
  580                                         };
  581                                 };
  582                                 usp0_uart_nostreamctrl_pins_a: usp0@1 {
  583                                         usp0 {
  584                                                 sirf,pins =
  585                                                         "usp0_uart_nostreamctrl_grp";
  586                                                 sirf,function =
  587                                                         "usp0_uart_nostreamctrl";
  588                                         };
  589                                 };
  590                                 usp0_only_utfs_pins_a: usp0@2 {
  591                                         usp0 {
  592                                                 sirf,pins = "usp0_only_utfs_grp";
  593                                                 sirf,function = "usp0_only_utfs";
  594                                         };
  595                                 };
  596                                 usp0_only_urfs_pins_a: usp0@3 {
  597                                         usp0 {
  598                                                 sirf,pins = "usp0_only_urfs_grp";
  599                                                 sirf,function = "usp0_only_urfs";
  600                                         };
  601                                 };
  602                                 usp1_pins_a: usp1@0 {
  603                                         usp1 {
  604                                                 sirf,pins = "usp1grp";
  605                                                 sirf,function = "usp1";
  606                                         };
  607                                 };
  608                                 usp1_uart_nostreamctrl_pins_a: usp1@1 {
  609                                         usp1 {
  610                                                 sirf,pins =
  611                                                         "usp1_uart_nostreamctrl_grp";
  612                                                 sirf,function =
  613                                                         "usp1_uart_nostreamctrl";
  614                                         };
  615                                 };
  616                                 usp2_pins_a: usp2@0 {
  617                                         usp2 {
  618                                                 sirf,pins = "usp2grp";
  619                                                 sirf,function = "usp2";
  620                                         };
  621                                 };
  622                                 usp2_uart_nostreamctrl_pins_a: usp2@1 {
  623                                         usp2 {
  624                                                 sirf,pins =
  625                                                         "usp2_uart_nostreamctrl_grp";
  626                                                 sirf,function =
  627                                                         "usp2_uart_nostreamctrl";
  628                                         };
  629                                 };
  630                                 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
  631                                         usb0_utmi_drvbus {
  632                                                 sirf,pins = "usb0_utmi_drvbusgrp";
  633                                                 sirf,function = "usb0_utmi_drvbus";
  634                                         };
  635                                 };
  636                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
  637                                         usb1_utmi_drvbus {
  638                                                 sirf,pins = "usb1_utmi_drvbusgrp";
  639                                                 sirf,function = "usb1_utmi_drvbus";
  640                                         };
  641                                 };
  642                                 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
  643                                         usb1_dp_dn {
  644                                                 sirf,pins = "usb1_dp_dngrp";
  645                                                 sirf,function = "usb1_dp_dn";
  646                                         };
  647                                 };
  648                                 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
  649                                         uart1_route_io_usb1 {
  650                                                 sirf,pins = "uart1_route_io_usb1grp";
  651                                                 sirf,function = "uart1_route_io_usb1";
  652                                         };
  653                                 };
  654                                 warm_rst_pins_a: warm_rst@0 {
  655                                         warm_rst {
  656                                                 sirf,pins = "warm_rstgrp";
  657                                                 sirf,function = "warm_rst";
  658                                         };
  659                                 };
  660                                 pulse_count_pins_a: pulse_count@0 {
  661                                         pulse_count {
  662                                                 sirf,pins = "pulse_countgrp";
  663                                                 sirf,function = "pulse_count";
  664                                         };
  665                                 };
  666                                 cko0_pins_a: cko0@0 {
  667                                         cko0 {
  668                                                 sirf,pins = "cko0grp";
  669                                                 sirf,function = "cko0";
  670                                         };
  671                                 };
  672                                 cko1_pins_a: cko1@0 {
  673                                         cko1 {
  674                                                 sirf,pins = "cko1grp";
  675                                                 sirf,function = "cko1";
  676                                         };
  677                                 };
  678                         };
  679 
  680                         pwm@b0130000 {
  681                                 compatible = "sirf,prima2-pwm";
  682                                 reg = <0xb0130000 0x10000>;
  683                                 clocks = <&clks 21>;
  684                         };
  685 
  686                         efusesys@b0140000 {
  687                                 compatible = "sirf,prima2-efuse";
  688                                 reg = <0xb0140000 0x10000>;
  689                                 clocks = <&clks 22>;
  690                         };
  691 
  692                         pulsec@b0150000 {
  693                                 compatible = "sirf,prima2-pulsec";
  694                                 reg = <0xb0150000 0x10000>;
  695                                 interrupts = <48>;
  696                                 clocks = <&clks 23>;
  697                         };
  698 
  699                         pci-iobg {
  700                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
  701                                 #address-cells = <1>;
  702                                 #size-cells = <1>;
  703                                 ranges = <0x56000000 0x56000000 0x1b00000>;
  704 
  705                                 sd0: sdhci@56000000 {
  706                                         cell-index = <0>;
  707                                         compatible = "sirf,prima2-sdhc";
  708                                         reg = <0x56000000 0x100000>;
  709                                         interrupts = <38>;
  710                                         status = "disabled";
  711                                         bus-width = <8>;
  712                                         clocks = <&clks 36>;
  713                                 };
  714 
  715                                 sd1: sdhci@56100000 {
  716                                         cell-index = <1>;
  717                                         compatible = "sirf,prima2-sdhc";
  718                                         reg = <0x56100000 0x100000>;
  719                                         interrupts = <38>;
  720                                         status = "disabled";
  721                                         bus-width = <4>;
  722                                         clocks = <&clks 36>;
  723                                 };
  724 
  725                                 sd2: sdhci@56200000 {
  726                                         cell-index = <2>;
  727                                         compatible = "sirf,prima2-sdhc";
  728                                         reg = <0x56200000 0x100000>;
  729                                         interrupts = <23>;
  730                                         status = "disabled";
  731                                         clocks = <&clks 37>;
  732                                 };
  733 
  734                                 sd3: sdhci@56300000 {
  735                                         cell-index = <3>;
  736                                         compatible = "sirf,prima2-sdhc";
  737                                         reg = <0x56300000 0x100000>;
  738                                         interrupts = <23>;
  739                                         status = "disabled";
  740                                         clocks = <&clks 37>;
  741                                 };
  742 
  743                                 sd4: sdhci@56400000 {
  744                                         cell-index = <4>;
  745                                         compatible = "sirf,prima2-sdhc";
  746                                         reg = <0x56400000 0x100000>;
  747                                         interrupts = <39>;
  748                                         status = "disabled";
  749                                         clocks = <&clks 38>;
  750                                 };
  751 
  752                                 sd5: sdhci@56500000 {
  753                                         cell-index = <5>;
  754                                         compatible = "sirf,prima2-sdhc";
  755                                         reg = <0x56500000 0x100000>;
  756                                         interrupts = <39>;
  757                                         clocks = <&clks 38>;
  758                                 };
  759 
  760                                 pci-copy@57900000 {
  761                                         compatible = "sirf,prima2-pcicp";
  762                                         reg = <0x57900000 0x100000>;
  763                                         interrupts = <40>;
  764                                 };
  765 
  766                                 rom-interface@57a00000 {
  767                                         compatible = "sirf,prima2-romif";
  768                                         reg = <0x57a00000 0x100000>;
  769                                 };
  770                         };
  771                 };
  772 
  773                 rtc-iobg {
  774                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
  775                         #address-cells = <1>;
  776                         #size-cells = <1>;
  777                         reg = <0x80030000 0x10000>;
  778 
  779                         gpsrtc@1000 {
  780                                 compatible = "sirf,prima2-gpsrtc";
  781                                 reg = <0x1000 0x1000>;
  782                                 interrupts = <55 56 57>;
  783                         };
  784 
  785                         sysrtc@2000 {
  786                                 compatible = "sirf,prima2-sysrtc";
  787                                 reg = <0x2000 0x1000>;
  788                                 interrupts = <52 53 54>;
  789                         };
  790 
  791                         minigpsrtc@2000 {
  792                                 compatible = "sirf,prima2-minigpsrtc";
  793                                 reg = <0x2000 0x1000>;
  794                                 interrupts = <54>;
  795                         };
  796 
  797                         pwrc@3000 {
  798                                 compatible = "sirf,prima2-pwrc";
  799                                 reg = <0x3000 0x1000>;
  800                                 interrupts = <32>;
  801                         };
  802                 };
  803 
  804                 uus-iobg {
  805                         compatible = "simple-bus";
  806                         #address-cells = <1>;
  807                         #size-cells = <1>;
  808                         ranges = <0xb8000000 0xb8000000 0x40000>;
  809 
  810                         usb0: usb@b00e0000 {
  811                                 compatible = "chipidea,ci13611a-prima2";
  812                                 reg = <0xb8000000 0x10000>;
  813                                 interrupts = <10>;
  814                                 clocks = <&clks 40>;
  815                         };
  816 
  817                         usb1: usb@b00f0000 {
  818                                 compatible = "chipidea,ci13611a-prima2";
  819                                 reg = <0xb8010000 0x10000>;
  820                                 interrupts = <11>;
  821                                 clocks = <&clks 41>;
  822                         };
  823 
  824                         sata@b00f0000 {
  825                                 compatible = "synopsys,dwc-ahsata";
  826                                 reg = <0xb8020000 0x10000>;
  827                                 interrupts = <37>;
  828                         };
  829 
  830                         security@b00f0000 {
  831                                 compatible = "sirf,prima2-security";
  832                                 reg = <0xb8030000 0x10000>;
  833                                 interrupts = <42>;
  834                                 clocks = <&clks 7>;
  835                         };
  836                 };
  837         };
  838 };
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sys/contrib/device-tree/src/arm/prima2.dtsi
