qcom-apq8064.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0
    2 /dts-v1/;
    3 
    4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
    5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
    6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
    7 #include <dt-bindings/clock/qcom,rpmcc.h>
    8 #include <dt-bindings/soc/qcom,gsbi.h>
    9 #include <dt-bindings/interrupt-controller/irq.h>
   10 #include <dt-bindings/interrupt-controller/arm-gic.h>
   11 / {
   12         #address-cells = <1>;
   13         #size-cells = <1>;
   14         model = "Qualcomm APQ8064";
   15         compatible = "qcom,apq8064";
   16         interrupt-parent = <&intc>;
   17 
   18         reserved-memory {
   19                 #address-cells = <1>;
   20                 #size-cells = <1>;
   21                 ranges;
   22 
   23                 smem_region: smem@80000000 {
   24                         reg = <0x80000000 0x200000>;
   25                         no-map;
   26                 };
   27 
   28                 wcnss_mem: wcnss@8f000000 {
   29                         reg = <0x8f000000 0x700000>;
   30                         no-map;
   31                 };
   32         };
   33 
   34         cpus {
   35                 #address-cells = <1>;
   36                 #size-cells = <0>;
   37 
   38                 CPU0: cpu@0 {
   39                         compatible = "qcom,krait";
   40                         enable-method = "qcom,kpss-acc-v1";
   41                         device_type = "cpu";
   42                         reg = <0>;
   43                         next-level-cache = <&L2>;
   44                         qcom,acc = <&acc0>;
   45                         qcom,saw = <&saw0>;
   46                         cpu-idle-states = <&CPU_SPC>;
   47                 };
   48 
   49                 CPU1: cpu@1 {
   50                         compatible = "qcom,krait";
   51                         enable-method = "qcom,kpss-acc-v1";
   52                         device_type = "cpu";
   53                         reg = <1>;
   54                         next-level-cache = <&L2>;
   55                         qcom,acc = <&acc1>;
   56                         qcom,saw = <&saw1>;
   57                         cpu-idle-states = <&CPU_SPC>;
   58                 };
   59 
   60                 CPU2: cpu@2 {
   61                         compatible = "qcom,krait";
   62                         enable-method = "qcom,kpss-acc-v1";
   63                         device_type = "cpu";
   64                         reg = <2>;
   65                         next-level-cache = <&L2>;
   66                         qcom,acc = <&acc2>;
   67                         qcom,saw = <&saw2>;
   68                         cpu-idle-states = <&CPU_SPC>;
   69                 };
   70 
   71                 CPU3: cpu@3 {
   72                         compatible = "qcom,krait";
   73                         enable-method = "qcom,kpss-acc-v1";
   74                         device_type = "cpu";
   75                         reg = <3>;
   76                         next-level-cache = <&L2>;
   77                         qcom,acc = <&acc3>;
   78                         qcom,saw = <&saw3>;
   79                         cpu-idle-states = <&CPU_SPC>;
   80                 };
   81 
   82                 L2: l2-cache {
   83                         compatible = "cache";
   84                         cache-level = <2>;
   85                 };
   86 
   87                 idle-states {
   88                         CPU_SPC: spc {
   89                                 compatible = "qcom,idle-state-spc",
   90                                                 "arm,idle-state";
   91                                 entry-latency-us = <400>;
   92                                 exit-latency-us = <900>;
   93                                 min-residency-us = <3000>;
   94                         };
   95                 };
   96         };
   97 
   98         memory@0 {
   99                 device_type = "memory";
  100                 reg = <0x0 0x0>;
  101         };
  102 
  103         thermal-zones {
  104                 cpu0-thermal {
  105                         polling-delay-passive = <250>;
  106                         polling-delay = <1000>;
  107 
  108                         thermal-sensors = <&tsens 7>;
  109                         coefficients = <1199 0>;
  110 
  111                         trips {
  112                                 cpu_alert0: trip0 {
  113                                         temperature = <75000>;
  114                                         hysteresis = <2000>;
  115                                         type = "passive";
  116                                 };
  117                                 cpu_crit0: trip1 {
  118                                         temperature = <110000>;
  119                                         hysteresis = <2000>;
  120                                         type = "critical";
  121                                 };
  122                         };
  123                 };
  124 
  125                 cpu1-thermal {
  126                         polling-delay-passive = <250>;
  127                         polling-delay = <1000>;
  128 
  129                         thermal-sensors = <&tsens 8>;
  130                         coefficients = <1132 0>;
  131 
  132                         trips {
  133                                 cpu_alert1: trip0 {
  134                                         temperature = <75000>;
  135                                         hysteresis = <2000>;
  136                                         type = "passive";
  137                                 };
  138                                 cpu_crit1: trip1 {
  139                                         temperature = <110000>;
  140                                         hysteresis = <2000>;
  141                                         type = "critical";
  142                                 };
  143                         };
  144                 };
  145 
  146                 cpu2-thermal {
  147                         polling-delay-passive = <250>;
  148                         polling-delay = <1000>;
  149 
  150                         thermal-sensors = <&tsens 9>;
  151                         coefficients = <1199 0>;
  152 
  153                         trips {
  154                                 cpu_alert2: trip0 {
  155                                         temperature = <75000>;
  156                                         hysteresis = <2000>;
  157                                         type = "passive";
  158                                 };
  159                                 cpu_crit2: trip1 {
  160                                         temperature = <110000>;
  161                                         hysteresis = <2000>;
  162                                         type = "critical";
  163                                 };
  164                         };
  165                 };
  166 
  167                 cpu3-thermal {
  168                         polling-delay-passive = <250>;
  169                         polling-delay = <1000>;
  170 
  171                         thermal-sensors = <&tsens 10>;
  172                         coefficients = <1132 0>;
  173 
  174                         trips {
  175                                 cpu_alert3: trip0 {
  176                                         temperature = <75000>;
  177                                         hysteresis = <2000>;
  178                                         type = "passive";
  179                                 };
  180                                 cpu_crit3: trip1 {
  181                                         temperature = <110000>;
  182                                         hysteresis = <2000>;
  183                                         type = "critical";
  184                                 };
  185                         };
  186                 };
  187         };
  188 
  189         cpu-pmu {
  190                 compatible = "qcom,krait-pmu";
  191                 interrupts = <1 10 0x304>;
  192         };
  193 
  194         clocks {
  195                 cxo_board: cxo_board {
  196                         compatible = "fixed-clock";
  197                         #clock-cells = <0>;
  198                         clock-frequency = <19200000>;
  199                 };
  200 
  201                 pxo_board: pxo_board {
  202                         compatible = "fixed-clock";
  203                         #clock-cells = <0>;
  204                         clock-frequency = <27000000>;
  205                 };
  206 
  207                 sleep_clk: sleep_clk {
  208                         compatible = "fixed-clock";
  209                         #clock-cells = <0>;
  210                         clock-frequency = <32768>;
  211                 };
  212         };
  213 
  214         sfpb_mutex: hwmutex {
  215                 compatible = "qcom,sfpb-mutex";
  216                 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
  217                 #hwlock-cells = <1>;
  218         };
  219 
  220         smem {
  221                 compatible = "qcom,smem";
  222                 memory-region = <&smem_region>;
  223 
  224                 hwlocks = <&sfpb_mutex 3>;
  225         };
  226 
  227         smd {
  228                 compatible = "qcom,smd";
  229 
  230                 modem-edge {
  231                         interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
  232 
  233                         qcom,ipc = <&l2cc 8 3>;
  234                         qcom,smd-edge = <0>;
  235 
  236                         status = "disabled";
  237                 };
  238 
  239                 q6-edge {
  240                         interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
  241 
  242                         qcom,ipc = <&l2cc 8 15>;
  243                         qcom,smd-edge = <1>;
  244 
  245                         status = "disabled";
  246                 };
  247 
  248                 dsps-edge {
  249                         interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
  250 
  251                         qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
  252                         qcom,smd-edge = <3>;
  253 
  254                         status = "disabled";
  255                 };
  256 
  257                 riva-edge {
  258                         interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
  259 
  260                         qcom,ipc = <&l2cc 8 25>;
  261                         qcom,smd-edge = <6>;
  262 
  263                         status = "disabled";
  264                 };
  265         };
  266 
  267         smsm {
  268                 compatible = "qcom,smsm";
  269 
  270                 #address-cells = <1>;
  271                 #size-cells = <0>;
  272 
  273                 qcom,ipc-1 = <&l2cc 8 4>;
  274                 qcom,ipc-2 = <&l2cc 8 14>;
  275                 qcom,ipc-3 = <&l2cc 8 23>;
  276                 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
  277 
  278                 apps_smsm: apps@0 {
  279                         reg = <0>;
  280                         #qcom,smem-state-cells = <1>;
  281                 };
  282 
  283                 modem_smsm: modem@1 {
  284                         reg = <1>;
  285                         interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
  286 
  287                         interrupt-controller;
  288                         #interrupt-cells = <2>;
  289                 };
  290 
  291                 q6_smsm: q6@2 {
  292                         reg = <2>;
  293                         interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
  294 
  295                         interrupt-controller;
  296                         #interrupt-cells = <2>;
  297                 };
  298 
  299                 wcnss_smsm: wcnss@3 {
  300                         reg = <3>;
  301                         interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
  302 
  303                         interrupt-controller;
  304                         #interrupt-cells = <2>;
  305                 };
  306 
  307                 dsps_smsm: dsps@4 {
  308                         reg = <4>;
  309                         interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
  310 
  311                         interrupt-controller;
  312                         #interrupt-cells = <2>;
  313                 };
  314         };
  315 
  316         firmware {
  317                 scm {
  318                         compatible = "qcom,scm-apq8064", "qcom,scm";
  319 
  320                         clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
  321                         clock-names = "core";
  322                 };
  323         };
  324 
  325 
  326         /*
  327          * These channels from the ADC are simply hardware monitors.
  328          * That is why the ADC is referred to as "HKADC" - HouseKeeping
  329          * ADC.
  330          */
  331         iio-hwmon {
  332                 compatible = "iio-hwmon";
  333                 io-channels = <&xoadc 0x00 0x01>, /* Battery */
  334                             <&xoadc 0x00 0x02>, /* DC in (charger) */
  335                             <&xoadc 0x00 0x04>, /* VPH the main system voltage */
  336                             <&xoadc 0x00 0x0b>, /* Die temperature */
  337                             <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
  338                             <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
  339                             <&xoadc 0x00 0x0e>; /* Charger temperature */
  340         };
  341 
  342         soc: soc {
  343                 #address-cells = <1>;
  344                 #size-cells = <1>;
  345                 ranges;
  346                 compatible = "simple-bus";
  347 
  348                 tlmm_pinmux: pinctrl@800000 {
  349                         compatible = "qcom,apq8064-pinctrl";
  350                         reg = <0x800000 0x4000>;
  351 
  352                         gpio-controller;
  353                         gpio-ranges = <&tlmm_pinmux 0 0 90>;
  354                         #gpio-cells = <2>;
  355                         interrupt-controller;
  356                         #interrupt-cells = <2>;
  357                         interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
  358 
  359                         pinctrl-names = "default";
  360                         pinctrl-0 = <&ps_hold>;
  361                 };
  362 
  363                 sfpb_wrapper_mutex: syscon@1200000 {
  364                         compatible = "syscon";
  365                         reg = <0x01200000 0x8000>;
  366                 };
  367 
  368                 intc: interrupt-controller@2000000 {
  369                         compatible = "qcom,msm-qgic2";
  370                         interrupt-controller;
  371                         #interrupt-cells = <3>;
  372                         reg = <0x02000000 0x1000>,
  373                               <0x02002000 0x1000>;
  374                 };
  375 
  376                 timer@200a000 {
  377                         compatible = "qcom,kpss-timer",
  378                                      "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
  379                         interrupts = <1 1 0x301>,
  380                                      <1 2 0x301>,
  381                                      <1 3 0x301>;
  382                         reg = <0x0200a000 0x100>;
  383                         clock-frequency = <27000000>,
  384                                           <32768>;
  385                         cpu-offset = <0x80000>;
  386                 };
  387 
  388                 acc0: clock-controller@2088000 {
  389                         compatible = "qcom,kpss-acc-v1";
  390                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
  391                 };
  392 
  393                 acc1: clock-controller@2098000 {
  394                         compatible = "qcom,kpss-acc-v1";
  395                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
  396                 };
  397 
  398                 acc2: clock-controller@20a8000 {
  399                         compatible = "qcom,kpss-acc-v1";
  400                         reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
  401                 };
  402 
  403                 acc3: clock-controller@20b8000 {
  404                         compatible = "qcom,kpss-acc-v1";
  405                         reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
  406                 };
  407 
  408                 saw0: power-controller@2089000 {
  409                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
  410                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
  411                         regulator;
  412                 };
  413 
  414                 saw1: power-controller@2099000 {
  415                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
  416                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
  417                         regulator;
  418                 };
  419 
  420                 saw2: power-controller@20a9000 {
  421                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
  422                         reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
  423                         regulator;
  424                 };
  425 
  426                 saw3: power-controller@20b9000 {
  427                         compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
  428                         reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
  429                         regulator;
  430                 };
  431 
  432                 sps_sic_non_secure: sps-sic-non-secure@12100000 {
  433                         compatible = "syscon";
  434                         reg = <0x12100000 0x10000>;
  435                 };
  436 
  437                 gsbi1: gsbi@12440000 {
  438                         status = "disabled";
  439                         compatible = "qcom,gsbi-v1.0.0";
  440                         cell-index = <1>;
  441                         reg = <0x12440000 0x100>;
  442                         clocks = <&gcc GSBI1_H_CLK>;
  443                         clock-names = "iface";
  444                         #address-cells = <1>;
  445                         #size-cells = <1>;
  446                         ranges;
  447 
  448                         syscon-tcsr = <&tcsr>;
  449 
  450                         gsbi1_serial: serial@12450000 {
  451                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  452                                 reg = <0x12450000 0x100>,
  453                                       <0x12400000 0x03>;
  454                                 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
  455                                 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
  456                                 clock-names = "core", "iface";
  457                                 status = "disabled";
  458                         };
  459 
  460                         gsbi1_i2c: i2c@12460000 {
  461                                 compatible = "qcom,i2c-qup-v1.1.1";
  462                                 pinctrl-0 = <&i2c1_pins>;
  463                                 pinctrl-1 = <&i2c1_pins_sleep>;
  464                                 pinctrl-names = "default", "sleep";
  465                                 reg = <0x12460000 0x1000>;
  466                                 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
  467                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
  468                                 clock-names = "core", "iface";
  469                                 #address-cells = <1>;
  470                                 #size-cells = <0>;
  471                                 status = "disabled";
  472                         };
  473 
  474                 };
  475 
  476                 gsbi2: gsbi@12480000 {
  477                         status = "disabled";
  478                         compatible = "qcom,gsbi-v1.0.0";
  479                         cell-index = <2>;
  480                         reg = <0x12480000 0x100>;
  481                         clocks = <&gcc GSBI2_H_CLK>;
  482                         clock-names = "iface";
  483                         #address-cells = <1>;
  484                         #size-cells = <1>;
  485                         ranges;
  486 
  487                         syscon-tcsr = <&tcsr>;
  488 
  489                         gsbi2_i2c: i2c@124a0000 {
  490                                 compatible = "qcom,i2c-qup-v1.1.1";
  491                                 reg = <0x124a0000 0x1000>;
  492                                 pinctrl-0 = <&i2c2_pins>;
  493                                 pinctrl-1 = <&i2c2_pins_sleep>;
  494                                 pinctrl-names = "default", "sleep";
  495                                 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
  496                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
  497                                 clock-names = "core", "iface";
  498                                 #address-cells = <1>;
  499                                 #size-cells = <0>;
  500                                 status = "disabled";
  501                         };
  502                 };
  503 
  504                 gsbi3: gsbi@16200000 {
  505                         status = "disabled";
  506                         compatible = "qcom,gsbi-v1.0.0";
  507                         cell-index = <3>;
  508                         reg = <0x16200000 0x100>;
  509                         clocks = <&gcc GSBI3_H_CLK>;
  510                         clock-names = "iface";
  511                         #address-cells = <1>;
  512                         #size-cells = <1>;
  513                         ranges;
  514                         gsbi3_i2c: i2c@16280000 {
  515                                 compatible = "qcom,i2c-qup-v1.1.1";
  516                                 pinctrl-0 = <&i2c3_pins>;
  517                                 pinctrl-1 = <&i2c3_pins_sleep>;
  518                                 pinctrl-names = "default", "sleep";
  519                                 reg = <0x16280000 0x1000>;
  520                                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
  521                                 clocks = <&gcc GSBI3_QUP_CLK>,
  522                                          <&gcc GSBI3_H_CLK>;
  523                                 clock-names = "core", "iface";
  524                                 #address-cells = <1>;
  525                                 #size-cells = <0>;
  526                                 status = "disabled";
  527                         };
  528                 };
  529 
  530                 gsbi4: gsbi@16300000 {
  531                         status = "disabled";
  532                         compatible = "qcom,gsbi-v1.0.0";
  533                         cell-index = <4>;
  534                         reg = <0x16300000 0x03>;
  535                         clocks = <&gcc GSBI4_H_CLK>;
  536                         clock-names = "iface";
  537                         #address-cells = <1>;
  538                         #size-cells = <1>;
  539                         ranges;
  540 
  541                         gsbi4_i2c: i2c@16380000 {
  542                                 compatible = "qcom,i2c-qup-v1.1.1";
  543                                 pinctrl-0 = <&i2c4_pins>;
  544                                 pinctrl-1 = <&i2c4_pins_sleep>;
  545                                 pinctrl-names = "default", "sleep";
  546                                 reg = <0x16380000 0x1000>;
  547                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
  548                                 clocks = <&gcc GSBI4_QUP_CLK>,
  549                                          <&gcc GSBI4_H_CLK>;
  550                                 clock-names = "core", "iface";
  551                                 status = "disabled";
  552                         };
  553                 };
  554 
  555                 gsbi5: gsbi@1a200000 {
  556                         status = "disabled";
  557                         compatible = "qcom,gsbi-v1.0.0";
  558                         cell-index = <5>;
  559                         reg = <0x1a200000 0x03>;
  560                         clocks = <&gcc GSBI5_H_CLK>;
  561                         clock-names = "iface";
  562                         #address-cells = <1>;
  563                         #size-cells = <1>;
  564                         ranges;
  565 
  566                         gsbi5_serial: serial@1a240000 {
  567                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  568                                 reg = <0x1a240000 0x100>,
  569                                       <0x1a200000 0x03>;
  570                                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
  571                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
  572                                 clock-names = "core", "iface";
  573                                 status = "disabled";
  574                         };
  575 
  576                         gsbi5_spi: spi@1a280000 {
  577                                 compatible = "qcom,spi-qup-v1.1.1";
  578                                 reg = <0x1a280000 0x1000>;
  579                                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
  580                                 pinctrl-0 = <&spi5_default>;
  581                                 pinctrl-1 = <&spi5_sleep>;
  582                                 pinctrl-names = "default", "sleep";
  583                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
  584                                 clock-names = "core", "iface";
  585                                 status = "disabled";
  586                                 #address-cells = <1>;
  587                                 #size-cells = <0>;
  588                         };
  589                 };
  590 
  591                 gsbi6: gsbi@16500000 {
  592                         status = "disabled";
  593                         compatible = "qcom,gsbi-v1.0.0";
  594                         cell-index = <6>;
  595                         reg = <0x16500000 0x03>;
  596                         clocks = <&gcc GSBI6_H_CLK>;
  597                         clock-names = "iface";
  598                         #address-cells = <1>;
  599                         #size-cells = <1>;
  600                         ranges;
  601 
  602                         gsbi6_serial: serial@16540000 {
  603                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  604                                 reg = <0x16540000 0x100>,
  605                                       <0x16500000 0x03>;
  606                                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
  607                                 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
  608                                 clock-names = "core", "iface";
  609                                 status = "disabled";
  610                         };
  611 
  612                         gsbi6_i2c: i2c@16580000 {
  613                                 compatible = "qcom,i2c-qup-v1.1.1";
  614                                 pinctrl-0 = <&i2c6_pins>;
  615                                 pinctrl-1 = <&i2c6_pins_sleep>;
  616                                 pinctrl-names = "default", "sleep";
  617                                 reg = <0x16580000 0x1000>;
  618                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
  619                                 clocks = <&gcc GSBI6_QUP_CLK>,
  620                                          <&gcc GSBI6_H_CLK>;
  621                                 clock-names = "core", "iface";
  622                                 status = "disabled";
  623                         };
  624                 };
  625 
  626                 gsbi7: gsbi@16600000 {
  627                         status = "disabled";
  628                         compatible = "qcom,gsbi-v1.0.0";
  629                         cell-index = <7>;
  630                         reg = <0x16600000 0x100>;
  631                         clocks = <&gcc GSBI7_H_CLK>;
  632                         clock-names = "iface";
  633                         #address-cells = <1>;
  634                         #size-cells = <1>;
  635                         ranges;
  636                         syscon-tcsr = <&tcsr>;
  637 
  638                         gsbi7_serial: serial@16640000 {
  639                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  640                                 reg = <0x16640000 0x1000>,
  641                                       <0x16600000 0x1000>;
  642                                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
  643                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
  644                                 clock-names = "core", "iface";
  645                                 status = "disabled";
  646                         };
  647 
  648                         gsbi7_i2c: i2c@16680000 {
  649                                 compatible = "qcom,i2c-qup-v1.1.1";
  650                                 pinctrl-0 = <&i2c7_pins>;
  651                                 pinctrl-1 = <&i2c7_pins_sleep>;
  652                                 pinctrl-names = "default", "sleep";
  653                                 reg = <0x16680000 0x1000>;
  654                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
  655                                 clocks = <&gcc GSBI7_QUP_CLK>,
  656                                          <&gcc GSBI7_H_CLK>;
  657                                 clock-names = "core", "iface";
  658                                 status = "disabled";
  659                         };
  660                 };
  661 
  662                 rng@1a500000 {
  663                         compatible = "qcom,prng";
  664                         reg = <0x1a500000 0x200>;
  665                         clocks = <&gcc PRNG_CLK>;
  666                         clock-names = "core";
  667                 };
  668 
  669                 ssbi@c00000 {
  670                         compatible = "qcom,ssbi";
  671                         reg = <0x00c00000 0x1000>;
  672                         qcom,controller-type = "pmic-arbiter";
  673 
  674                         pm8821: pmic@1 {
  675                                 compatible = "qcom,pm8821";
  676                                 interrupt-parent = <&tlmm_pinmux>;
  677                                 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
  678                                 #interrupt-cells = <2>;
  679                                 interrupt-controller;
  680                                 #address-cells = <1>;
  681                                 #size-cells = <0>;
  682 
  683                                 pm8821_mpps: mpps@50 {
  684                                         compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
  685                                         reg = <0x50>;
  686                                         interrupt-controller;
  687                                         #interrupt-cells = <2>;
  688                                         gpio-controller;
  689                                         #gpio-cells = <2>;
  690                                         gpio-ranges = <&pm8821_mpps 0 0 4>;
  691                                 };
  692                         };
  693                 };
  694 
  695                 qcom,ssbi@500000 {
  696                         compatible = "qcom,ssbi";
  697                         reg = <0x00500000 0x1000>;
  698                         qcom,controller-type = "pmic-arbiter";
  699 
  700                         pmicintc: pmic@0 {
  701                                 compatible = "qcom,pm8921";
  702                                 interrupt-parent = <&tlmm_pinmux>;
  703                                 interrupts = <74 8>;
  704                                 #interrupt-cells = <2>;
  705                                 interrupt-controller;
  706                                 #address-cells = <1>;
  707                                 #size-cells = <0>;
  708 
  709                                 pm8921_gpio: gpio@150 {
  710 
  711                                         compatible = "qcom,pm8921-gpio",
  712                                                      "qcom,ssbi-gpio";
  713                                         reg = <0x150>;
  714                                         interrupt-controller;
  715                                         #interrupt-cells = <2>;
  716                                         gpio-controller;
  717                                         gpio-ranges = <&pm8921_gpio 0 0 44>;
  718                                         #gpio-cells = <2>;
  719 
  720                                 };
  721 
  722                                 pm8921_mpps: mpps@50 {
  723                                         compatible = "qcom,pm8921-mpp",
  724                                                      "qcom,ssbi-mpp";
  725                                         reg = <0x50>;
  726                                         gpio-controller;
  727                                         #gpio-cells = <2>;
  728                                         gpio-ranges = <&pm8921_mpps 0 0 12>;
  729                                         interrupt-controller;
  730                                         #interrupt-cells = <2>;
  731                                 };
  732 
  733                                 rtc@11d {
  734                                         compatible = "qcom,pm8921-rtc";
  735                                         interrupt-parent = <&pmicintc>;
  736                                         interrupts = <39 1>;
  737                                         reg = <0x11d>;
  738                                         allow-set-time;
  739                                 };
  740 
  741                                 pwrkey@1c {
  742                                         compatible = "qcom,pm8921-pwrkey";
  743                                         reg = <0x1c>;
  744                                         interrupt-parent = <&pmicintc>;
  745                                         interrupts = <50 1>, <51 1>;
  746                                         debounce = <15625>;
  747                                         pull-up;
  748                                 };
  749 
  750                                 xoadc: xoadc@197 {
  751                                         compatible = "qcom,pm8921-adc";
  752                                         reg = <197>;
  753                                         interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
  754                                         #address-cells = <2>;
  755                                         #size-cells = <0>;
  756                                         #io-channel-cells = <2>;
  757 
  758                                         vcoin: adc-channel@0 {
  759                                                 reg = <0x00 0x00>;
  760                                         };
  761                                         vbat: adc-channel@1 {
  762                                                 reg = <0x00 0x01>;
  763                                         };
  764                                         dcin: adc-channel@2 {
  765                                                 reg = <0x00 0x02>;
  766                                         };
  767                                         vph_pwr: adc-channel@4 {
  768                                                 reg = <0x00 0x04>;
  769                                         };
  770                                         batt_therm: adc-channel@8 {
  771                                                 reg = <0x00 0x08>;
  772                                         };
  773                                         batt_id: adc-channel@9 {
  774                                                 reg = <0x00 0x09>;
  775                                         };
  776                                         usb_vbus: adc-channel@a {
  777                                                 reg = <0x00 0x0a>;
  778                                         };
  779                                         die_temp: adc-channel@b {
  780                                                 reg = <0x00 0x0b>;
  781                                         };
  782                                         ref_625mv: adc-channel@c {
  783                                                 reg = <0x00 0x0c>;
  784                                         };
  785                                         ref_1250mv: adc-channel@d {
  786                                                 reg = <0x00 0x0d>;
  787                                         };
  788                                         chg_temp: adc-channel@e {
  789                                                 reg = <0x00 0x0e>;
  790                                         };
  791                                         ref_muxoff: adc-channel@f {
  792                                                 reg = <0x00 0x0f>;
  793                                         };
  794                                 };
  795                         };
  796                 };
  797 
  798                 qfprom: qfprom@700000 {
  799                         compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
  800                         reg = <0x00700000 0x1000>;
  801                         #address-cells = <1>;
  802                         #size-cells = <1>;
  803                         ranges;
  804                         tsens_calib: calib@404 {
  805                                 reg = <0x404 0x10>;
  806                         };
  807                         tsens_backup: backup_calib@414 {
  808                                 reg = <0x414 0x10>;
  809                         };
  810                 };
  811 
  812                 gcc: clock-controller@900000 {
  813                         compatible = "qcom,gcc-apq8064", "syscon";
  814                         reg = <0x00900000 0x4000>;
  815                         #clock-cells = <1>;
  816                         #power-domain-cells = <1>;
  817                         #reset-cells = <1>;
  818 
  819                         tsens: thermal-sensor {
  820                                 compatible = "qcom,msm8960-tsens";
  821 
  822                                 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
  823                                 nvmem-cell-names = "calib", "calib_backup";
  824                                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
  825                                 interrupt-names = "uplow";
  826 
  827                                 #qcom,sensors = <11>;
  828                                 #thermal-sensor-cells = <1>;
  829                         };
  830                 };
  831 
  832                 lcc: clock-controller@28000000 {
  833                         compatible = "qcom,lcc-apq8064";
  834                         reg = <0x28000000 0x1000>;
  835                         #clock-cells = <1>;
  836                         #reset-cells = <1>;
  837                 };
  838 
  839                 mmcc: clock-controller@4000000 {
  840                         compatible = "qcom,mmcc-apq8064";
  841                         reg = <0x4000000 0x1000>;
  842                         #clock-cells = <1>;
  843                         #power-domain-cells = <1>;
  844                         #reset-cells = <1>;
  845                 };
  846 
  847                 l2cc: clock-controller@2011000 {
  848                         compatible = "qcom,kpss-gcc", "syscon";
  849                         reg = <0x2011000 0x1000>;
  850                 };
  851 
  852                 rpm@108000 {
  853                         compatible = "qcom,rpm-apq8064";
  854                         reg = <0x108000 0x1000>;
  855                         qcom,ipc = <&l2cc 0x8 2>;
  856 
  857                         interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
  858                                      <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
  859                                      <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
  860                         interrupt-names = "ack", "err", "wakeup";
  861 
  862                         rpmcc: clock-controller {
  863                                 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
  864                                 #clock-cells = <1>;
  865                                 clocks = <&pxo_board>, <&cxo_board>;
  866                                 clock-names = "pxo", "cxo";
  867                         };
  868 
  869                         regulators {
  870                                 compatible = "qcom,rpm-pm8921-regulators";
  871 
  872                                 pm8921_s1: s1 {};
  873                                 pm8921_s2: s2 {};
  874                                 pm8921_s3: s3 {};
  875                                 pm8921_s4: s4 {};
  876                                 pm8921_s7: s7 {};
  877                                 pm8921_s8: s8 {};
  878 
  879                                 pm8921_l1: l1 {};
  880                                 pm8921_l2: l2 {};
  881                                 pm8921_l3: l3 {};
  882                                 pm8921_l4: l4 {};
  883                                 pm8921_l5: l5 {};
  884                                 pm8921_l6: l6 {};
  885                                 pm8921_l7: l7 {};
  886                                 pm8921_l8: l8 {};
  887                                 pm8921_l9: l9 {};
  888                                 pm8921_l10: l10 {};
  889                                 pm8921_l11: l11 {};
  890                                 pm8921_l12: l12 {};
  891                                 pm8921_l14: l14 {};
  892                                 pm8921_l15: l15 {};
  893                                 pm8921_l16: l16 {};
  894                                 pm8921_l17: l17 {};
  895                                 pm8921_l18: l18 {};
  896                                 pm8921_l21: l21 {};
  897                                 pm8921_l22: l22 {};
  898                                 pm8921_l23: l23 {};
  899                                 pm8921_l24: l24 {};
  900                                 pm8921_l25: l25 {};
  901                                 pm8921_l26: l26 {};
  902                                 pm8921_l27: l27 {};
  903                                 pm8921_l28: l28 {};
  904                                 pm8921_l29: l29 {};
  905 
  906                                 pm8921_lvs1: lvs1 {};
  907                                 pm8921_lvs2: lvs2 {};
  908                                 pm8921_lvs3: lvs3 {};
  909                                 pm8921_lvs4: lvs4 {};
  910                                 pm8921_lvs5: lvs5 {};
  911                                 pm8921_lvs6: lvs6 {};
  912                                 pm8921_lvs7: lvs7 {};
  913 
  914                                 pm8921_usb_switch: usb-switch {};
  915 
  916                                 pm8921_hdmi_switch: hdmi-switch {
  917                                         bias-pull-down;
  918                                 };
  919 
  920                                 pm8921_ncp: ncp {};
  921                         };
  922                 };
  923 
  924                 usb1: usb@12500000 {
  925                         compatible = "qcom,ci-hdrc";
  926                         reg = <0x12500000 0x200>,
  927                               <0x12500200 0x200>;
  928                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
  929                         clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
  930                         clock-names = "core", "iface";
  931                         assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
  932                         assigned-clock-rates = <60000000>;
  933                         resets = <&gcc USB_HS1_RESET>;
  934                         reset-names = "core";
  935                         phy_type = "ulpi";
  936                         ahb-burst-config = <0>;
  937                         phys = <&usb_hs1_phy>;
  938                         phy-names = "usb-phy";
  939                         status = "disabled";
  940                         #reset-cells = <1>;
  941 
  942                         ulpi {
  943                                 usb_hs1_phy: phy {
  944                                         compatible = "qcom,usb-hs-phy-apq8064",
  945                                                      "qcom,usb-hs-phy";
  946                                         clocks = <&sleep_clk>, <&cxo_board>;
  947                                         clock-names = "sleep", "ref";
  948                                         resets = <&usb1 0>;
  949                                         reset-names = "por";
  950                                         #phy-cells = <0>;
  951                                 };
  952                         };
  953                 };
  954 
  955                 usb3: usb@12520000 {
  956                         compatible = "qcom,ci-hdrc";
  957                         reg = <0x12520000 0x200>,
  958                               <0x12520200 0x200>;
  959                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
  960                         clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
  961                         clock-names = "core", "iface";
  962                         assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
  963                         assigned-clock-rates = <60000000>;
  964                         resets = <&gcc USB_HS3_RESET>;
  965                         reset-names = "core";
  966                         phy_type = "ulpi";
  967                         ahb-burst-config = <0>;
  968                         phys = <&usb_hs3_phy>;
  969                         phy-names = "usb-phy";
  970                         status = "disabled";
  971                         #reset-cells = <1>;
  972 
  973                         ulpi {
  974                                 usb_hs3_phy: phy {
  975                                         compatible = "qcom,usb-hs-phy-apq8064",
  976                                                      "qcom,usb-hs-phy";
  977                                         #phy-cells = <0>;
  978                                         clocks = <&sleep_clk>, <&cxo_board>;
  979                                         clock-names = "sleep", "ref";
  980                                         resets = <&usb3 0>;
  981                                         reset-names = "por";
  982                                 };
  983                         };
  984                 };
  985 
  986                 usb4: usb@12530000 {
  987                         compatible = "qcom,ci-hdrc";
  988                         reg = <0x12530000 0x200>,
  989                               <0x12530200 0x200>;
  990                         interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
  991                         clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
  992                         clock-names = "core", "iface";
  993                         assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
  994                         assigned-clock-rates = <60000000>;
  995                         resets = <&gcc USB_HS4_RESET>;
  996                         reset-names = "core";
  997                         phy_type = "ulpi";
  998                         ahb-burst-config = <0>;
  999                         phys = <&usb_hs4_phy>;
 1000                         phy-names = "usb-phy";
 1001                         status = "disabled";
 1002                         #reset-cells = <1>;
 1003 
 1004                         ulpi {
 1005                                 usb_hs4_phy: phy {
 1006                                         compatible = "qcom,usb-hs-phy-apq8064",
 1007                                                      "qcom,usb-hs-phy";
 1008                                         #phy-cells = <0>;
 1009                                         clocks = <&sleep_clk>, <&cxo_board>;
 1010                                         clock-names = "sleep", "ref";
 1011                                         resets = <&usb4 0>;
 1012                                         reset-names = "por";
 1013                                 };
 1014                         };
 1015                 };
 1016 
 1017                 sata_phy0: phy@1b400000 {
 1018                         compatible = "qcom,apq8064-sata-phy";
 1019                         status = "disabled";
 1020                         reg = <0x1b400000 0x200>;
 1021                         reg-names = "phy_mem";
 1022                         clocks = <&gcc SATA_PHY_CFG_CLK>;
 1023                         clock-names = "cfg";
 1024                         #phy-cells = <0>;
 1025                 };
 1026 
 1027                 sata0: sata@29000000 {
 1028                         compatible = "qcom,apq8064-ahci", "generic-ahci";
 1029                         status   = "disabled";
 1030                         reg      = <0x29000000 0x180>;
 1031                         interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 1032 
 1033                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
 1034                                  <&gcc SATA_H_CLK>,
 1035                                  <&gcc SATA_A_CLK>,
 1036                                  <&gcc SATA_RXOOB_CLK>,
 1037                                  <&gcc SATA_PMALIVE_CLK>;
 1038                         clock-names = "slave_iface",
 1039                                       "iface",
 1040                                       "bus",
 1041                                       "rxoob",
 1042                                       "core_pmalive";
 1043 
 1044                         assigned-clocks = <&gcc SATA_RXOOB_CLK>,
 1045                                           <&gcc SATA_PMALIVE_CLK>;
 1046                         assigned-clock-rates = <100000000>, <100000000>;
 1047 
 1048                         phys = <&sata_phy0>;
 1049                         phy-names = "sata-phy";
 1050                         ports-implemented = <0x1>;
 1051                 };
 1052 
 1053                 /* Temporary fixed regulator */
 1054                 sdcc1bam: dma-controller@12402000{
 1055                         compatible = "qcom,bam-v1.3.0";
 1056                         reg = <0x12402000 0x8000>;
 1057                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 1058                         clocks = <&gcc SDC1_H_CLK>;
 1059                         clock-names = "bam_clk";
 1060                         #dma-cells = <1>;
 1061                         qcom,ee = <0>;
 1062                 };
 1063 
 1064                 sdcc3bam: dma-controller@12182000{
 1065                         compatible = "qcom,bam-v1.3.0";
 1066                         reg = <0x12182000 0x8000>;
 1067                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
 1068                         clocks = <&gcc SDC3_H_CLK>;
 1069                         clock-names = "bam_clk";
 1070                         #dma-cells = <1>;
 1071                         qcom,ee = <0>;
 1072                 };
 1073 
 1074                 sdcc4bam: dma-controller@121c2000{
 1075                         compatible = "qcom,bam-v1.3.0";
 1076                         reg = <0x121c2000 0x8000>;
 1077                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
 1078                         clocks = <&gcc SDC4_H_CLK>;
 1079                         clock-names = "bam_clk";
 1080                         #dma-cells = <1>;
 1081                         qcom,ee = <0>;
 1082                 };
 1083 
 1084                 amba {
 1085                         compatible = "simple-bus";
 1086                         #address-cells = <1>;
 1087                         #size-cells = <1>;
 1088                         ranges;
 1089                         sdcc1: mmc@12400000 {
 1090                                 status = "disabled";
 1091                                 compatible = "arm,pl18x", "arm,primecell";
 1092                                 pinctrl-names = "default";
 1093                                 pinctrl-0 = <&sdcc1_pins>;
 1094                                 arm,primecell-periphid = <0x00051180>;
 1095                                 reg = <0x12400000 0x2000>;
 1096                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 1097                                 interrupt-names = "cmd_irq";
 1098                                 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 1099                                 clock-names = "mclk", "apb_pclk";
 1100                                 bus-width = <8>;
 1101                                 max-frequency = <96000000>;
 1102                                 non-removable;
 1103                                 cap-sd-highspeed;
 1104                                 cap-mmc-highspeed;
 1105                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 1106                                 dma-names = "tx", "rx";
 1107                         };
 1108 
 1109                         sdcc3: mmc@12180000 {
 1110                                 compatible = "arm,pl18x", "arm,primecell";
 1111                                 arm,primecell-periphid = <0x00051180>;
 1112                                 status = "disabled";
 1113                                 reg = <0x12180000 0x2000>;
 1114                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 1115                                 interrupt-names = "cmd_irq";
 1116                                 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 1117                                 clock-names = "mclk", "apb_pclk";
 1118                                 bus-width = <4>;
 1119                                 cap-sd-highspeed;
 1120                                 cap-mmc-highspeed;
 1121                                 max-frequency = <192000000>;
 1122                                 no-1-8-v;
 1123                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 1124                                 dma-names = "tx", "rx";
 1125                         };
 1126 
 1127                         sdcc4: mmc@121c0000 {
 1128                                 compatible = "arm,pl18x", "arm,primecell";
 1129                                 arm,primecell-periphid = <0x00051180>;
 1130                                 status = "disabled";
 1131                                 reg = <0x121c0000 0x2000>;
 1132                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 1133                                 interrupt-names = "cmd_irq";
 1134                                 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
 1135                                 clock-names = "mclk", "apb_pclk";
 1136                                 bus-width = <4>;
 1137                                 cap-sd-highspeed;
 1138                                 cap-mmc-highspeed;
 1139                                 max-frequency = <48000000>;
 1140                                 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
 1141                                 dma-names = "tx", "rx";
 1142                                 pinctrl-names = "default";
 1143                                 pinctrl-0 = <&sdc4_gpios>;
 1144                         };
 1145                 };
 1146 
 1147                 tcsr: syscon@1a400000 {
 1148                         compatible = "qcom,tcsr-apq8064", "syscon";
 1149                         reg = <0x1a400000 0x100>;
 1150                 };
 1151 
 1152                 gpu: adreno-3xx@4300000 {
 1153                         compatible = "qcom,adreno-320.2", "qcom,adreno";
 1154                         reg = <0x04300000 0x20000>;
 1155                         reg-names = "kgsl_3d0_reg_memory";
 1156                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 1157                         interrupt-names = "kgsl_3d0_irq";
 1158                         clock-names =
 1159                             "core",
 1160                             "iface",
 1161                             "mem",
 1162                             "mem_iface";
 1163                         clocks =
 1164                             <&mmcc GFX3D_CLK>,
 1165                             <&mmcc GFX3D_AHB_CLK>,
 1166                             <&mmcc GFX3D_AXI_CLK>,
 1167                             <&mmcc MMSS_IMEM_AHB_CLK>;
 1168 
 1169                         iommus = <&gfx3d 0
 1170                                   &gfx3d 1
 1171                                   &gfx3d 2
 1172                                   &gfx3d 3
 1173                                   &gfx3d 4
 1174                                   &gfx3d 5
 1175                                   &gfx3d 6
 1176                                   &gfx3d 7
 1177                                   &gfx3d 8
 1178                                   &gfx3d 9
 1179                                   &gfx3d 10
 1180                                   &gfx3d 11
 1181                                   &gfx3d 12
 1182                                   &gfx3d 13
 1183                                   &gfx3d 14
 1184                                   &gfx3d 15
 1185                                   &gfx3d 16
 1186                                   &gfx3d 17
 1187                                   &gfx3d 18
 1188                                   &gfx3d 19
 1189                                   &gfx3d 20
 1190                                   &gfx3d 21
 1191                                   &gfx3d 22
 1192                                   &gfx3d 23
 1193                                   &gfx3d 24
 1194                                   &gfx3d 25
 1195                                   &gfx3d 26
 1196                                   &gfx3d 27
 1197                                   &gfx3d 28
 1198                                   &gfx3d 29
 1199                                   &gfx3d 30
 1200                                   &gfx3d 31
 1201                                   &gfx3d1 0
 1202                                   &gfx3d1 1
 1203                                   &gfx3d1 2
 1204                                   &gfx3d1 3
 1205                                   &gfx3d1 4
 1206                                   &gfx3d1 5
 1207                                   &gfx3d1 6
 1208                                   &gfx3d1 7
 1209                                   &gfx3d1 8
 1210                                   &gfx3d1 9
 1211                                   &gfx3d1 10
 1212                                   &gfx3d1 11
 1213                                   &gfx3d1 12
 1214                                   &gfx3d1 13
 1215                                   &gfx3d1 14
 1216                                   &gfx3d1 15
 1217                                   &gfx3d1 16
 1218                                   &gfx3d1 17
 1219                                   &gfx3d1 18
 1220                                   &gfx3d1 19
 1221                                   &gfx3d1 20
 1222                                   &gfx3d1 21
 1223                                   &gfx3d1 22
 1224                                   &gfx3d1 23
 1225                                   &gfx3d1 24
 1226                                   &gfx3d1 25
 1227                                   &gfx3d1 26
 1228                                   &gfx3d1 27
 1229                                   &gfx3d1 28
 1230                                   &gfx3d1 29
 1231                                   &gfx3d1 30
 1232                                   &gfx3d1 31>;
 1233 
 1234                         operating-points-v2 = <&gpu_opp_table>;
 1235 
 1236                         gpu_opp_table: opp-table {
 1237                                 compatible = "operating-points-v2";
 1238 
 1239                                 opp-320000000 {
 1240                                         opp-hz = /bits/ 64 <450000000>;
 1241                                 };
 1242 
 1243                                 opp-27000000 {
 1244                                         opp-hz = /bits/ 64 <27000000>;
 1245                                 };
 1246                         };
 1247                 };
 1248 
 1249                 mmss_sfpb: syscon@5700000 {
 1250                         compatible = "syscon";
 1251                         reg = <0x5700000 0x70>;
 1252                 };
 1253 
 1254                 dsi0: dsi@4700000 {
 1255                         compatible = "qcom,mdss-dsi-ctrl";
 1256                         label = "MDSS DSI CTRL->0";
 1257                         #address-cells = <1>;
 1258                         #size-cells = <0>;
 1259                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 1260                         reg = <0x04700000 0x200>;
 1261                         reg-names = "dsi_ctrl";
 1262 
 1263                         clocks = <&mmcc DSI_M_AHB_CLK>,
 1264                                 <&mmcc DSI_S_AHB_CLK>,
 1265                                 <&mmcc AMP_AHB_CLK>,
 1266                                 <&mmcc DSI_CLK>,
 1267                                 <&mmcc DSI1_BYTE_CLK>,
 1268                                 <&mmcc DSI_PIXEL_CLK>,
 1269                                 <&mmcc DSI1_ESC_CLK>;
 1270                         clock-names = "iface", "bus", "core_mmss",
 1271                                         "src", "byte", "pixel",
 1272                                         "core";
 1273 
 1274                         assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
 1275                                         <&mmcc DSI1_ESC_SRC>,
 1276                                         <&mmcc DSI_SRC>,
 1277                                         <&mmcc DSI_PIXEL_SRC>;
 1278                         assigned-clock-parents = <&dsi0_phy 0>,
 1279                                                 <&dsi0_phy 0>,
 1280                                                 <&dsi0_phy 1>,
 1281                                                 <&dsi0_phy 1>;
 1282                         syscon-sfpb = <&mmss_sfpb>;
 1283                         phys = <&dsi0_phy>;
 1284                         phy-names = "dsi";
 1285                         status = "disabled";
 1286 
 1287                         ports {
 1288                                 #address-cells = <1>;
 1289                                 #size-cells = <0>;
 1290 
 1291                                 port@0 {
 1292                                         reg = <0>;
 1293                                         dsi0_in: endpoint {
 1294                                         };
 1295                                 };
 1296 
 1297                                 port@1 {
 1298                                         reg = <1>;
 1299                                         dsi0_out: endpoint {
 1300                                         };
 1301                                 };
 1302                         };
 1303                 };
 1304 
 1305 
 1306                 dsi0_phy: dsi-phy@4700200 {
 1307                         compatible = "qcom,dsi-phy-28nm-8960";
 1308                         #clock-cells = <1>;
 1309                         #phy-cells = <0>;
 1310 
 1311                         reg = <0x04700200 0x100>,
 1312                                 <0x04700300 0x200>,
 1313                                 <0x04700500 0x5c>;
 1314                         reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
 1315                         clock-names = "iface", "ref";
 1316                         clocks = <&mmcc DSI_M_AHB_CLK>,
 1317                                  <&pxo_board>;
 1318                         status = "disabled";
 1319                 };
 1320 
 1321 
 1322                 mdp_port0: iommu@7500000 {
 1323                         compatible = "qcom,apq8064-iommu";
 1324                         #iommu-cells = <1>;
 1325                         clock-names =
 1326                             "smmu_pclk",
 1327                             "iommu_clk";
 1328                         clocks =
 1329                             <&mmcc SMMU_AHB_CLK>,
 1330                             <&mmcc MDP_AXI_CLK>;
 1331                         reg = <0x07500000 0x100000>;
 1332                         interrupts =
 1333                             <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
 1334                             <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 1335                         qcom,ncb = <2>;
 1336                 };
 1337 
 1338                 mdp_port1: iommu@7600000 {
 1339                         compatible = "qcom,apq8064-iommu";
 1340                         #iommu-cells = <1>;
 1341                         clock-names =
 1342                             "smmu_pclk",
 1343                             "iommu_clk";
 1344                         clocks =
 1345                             <&mmcc SMMU_AHB_CLK>,
 1346                             <&mmcc MDP_AXI_CLK>;
 1347                         reg = <0x07600000 0x100000>;
 1348                         interrupts =
 1349                             <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 1350                             <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 1351                         qcom,ncb = <2>;
 1352                 };
 1353 
 1354                 gfx3d: iommu@7c00000 {
 1355                         compatible = "qcom,apq8064-iommu";
 1356                         #iommu-cells = <1>;
 1357                         clock-names =
 1358                             "smmu_pclk",
 1359                             "iommu_clk";
 1360                         clocks =
 1361                             <&mmcc SMMU_AHB_CLK>,
 1362                             <&mmcc GFX3D_AXI_CLK>;
 1363                         reg = <0x07c00000 0x100000>;
 1364                         interrupts =
 1365                             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 1366                             <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 1367                         qcom,ncb = <3>;
 1368                 };
 1369 
 1370                 gfx3d1: iommu@7d00000 {
 1371                         compatible = "qcom,apq8064-iommu";
 1372                         #iommu-cells = <1>;
 1373                         clock-names =
 1374                             "smmu_pclk",
 1375                             "iommu_clk";
 1376                         clocks =
 1377                             <&mmcc SMMU_AHB_CLK>,
 1378                             <&mmcc GFX3D_AXI_CLK>;
 1379                         reg = <0x07d00000 0x100000>;
 1380                         interrupts =
 1381                             <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 1382                             <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
 1383                         qcom,ncb = <3>;
 1384                 };
 1385 
 1386                 pcie: pci@1b500000 {
 1387                         compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
 1388                         reg = <0x1b500000 0x1000>,
 1389                               <0x1b502000 0x80>,
 1390                               <0x1b600000 0x100>,
 1391                               <0x0ff00000 0x100000>;
 1392                         reg-names = "dbi", "elbi", "parf", "config";
 1393                         device_type = "pci";
 1394                         linux,pci-domain = <0>;
 1395                         bus-range = <0x00 0xff>;
 1396                         num-lanes = <1>;
 1397                         #address-cells = <3>;
 1398                         #size-cells = <2>;
 1399                         ranges = <0x81000000 0 0          0x0fe00000 0 0x00100000>, /* I/O */
 1400                                  <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */
 1401                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 1402                         interrupt-names = "msi";
 1403                         #interrupt-cells = <1>;
 1404                         interrupt-map-mask = <0 0 0 0x7>;
 1405                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 1406                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 1407                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 1408                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 1409                         clocks = <&gcc PCIE_A_CLK>,
 1410                                  <&gcc PCIE_H_CLK>,
 1411                                  <&gcc PCIE_PHY_REF_CLK>;
 1412                         clock-names = "core", "iface", "phy";
 1413                         resets = <&gcc PCIE_ACLK_RESET>,
 1414                                  <&gcc PCIE_HCLK_RESET>,
 1415                                  <&gcc PCIE_POR_RESET>,
 1416                                  <&gcc PCIE_PCI_RESET>,
 1417                                  <&gcc PCIE_PHY_RESET>;
 1418                         reset-names = "axi", "ahb", "por", "pci", "phy";
 1419                         status = "disabled";
 1420                 };
 1421 
 1422                 hdmi: hdmi-tx@4a00000 {
 1423                         compatible = "qcom,hdmi-tx-8960";
 1424                         pinctrl-names = "default";
 1425                         pinctrl-0 = <&hdmi_pinctrl>;
 1426                         reg = <0x04a00000 0x2f0>;
 1427                         reg-names = "core_physical";
 1428                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 1429                         clocks = <&mmcc HDMI_APP_CLK>,
 1430                                  <&mmcc HDMI_M_AHB_CLK>,
 1431                                  <&mmcc HDMI_S_AHB_CLK>;
 1432                         clock-names = "core",
 1433                                       "master_iface",
 1434                                       "slave_iface";
 1435 
 1436                         phys = <&hdmi_phy>;
 1437 
 1438                         ports {
 1439                                 #address-cells = <1>;
 1440                                 #size-cells = <0>;
 1441 
 1442                                 port@0 {
 1443                                         reg = <0>;
 1444                                         hdmi_in: endpoint {
 1445                                         };
 1446                                 };
 1447 
 1448                                 port@1 {
 1449                                         reg = <1>;
 1450                                         hdmi_out: endpoint {
 1451                                         };
 1452                                 };
 1453                         };
 1454                 };
 1455 
 1456                 hdmi_phy: hdmi-phy@4a00400 {
 1457                         compatible = "qcom,hdmi-phy-8960";
 1458                         reg = <0x4a00400 0x60>,
 1459                               <0x4a00500 0x100>;
 1460                         reg-names = "hdmi_phy",
 1461                                     "hdmi_pll";
 1462 
 1463                         clocks = <&mmcc HDMI_S_AHB_CLK>;
 1464                         clock-names = "slave_iface";
 1465                         #phy-cells = <0>;
 1466                 };
 1467 
 1468                 mdp: mdp@5100000 {
 1469                         compatible = "qcom,mdp4";
 1470                         reg = <0x05100000 0xf0000>;
 1471                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 1472                         clocks = <&mmcc MDP_CLK>,
 1473                                  <&mmcc MDP_AHB_CLK>,
 1474                                  <&mmcc MDP_AXI_CLK>,
 1475                                  <&mmcc MDP_LUT_CLK>,
 1476                                  <&mmcc HDMI_TV_CLK>,
 1477                                  <&mmcc MDP_TV_CLK>;
 1478                         clock-names = "core_clk",
 1479                                       "iface_clk",
 1480                                       "bus_clk",
 1481                                       "lut_clk",
 1482                                       "hdmi_clk",
 1483                                       "tv_clk";
 1484 
 1485                         iommus = <&mdp_port0 0
 1486                                   &mdp_port0 2
 1487                                   &mdp_port1 0
 1488                                   &mdp_port1 2>;
 1489 
 1490                         ports {
 1491                                 #address-cells = <1>;
 1492                                 #size-cells = <0>;
 1493 
 1494                                 port@0 {
 1495                                         reg = <0>;
 1496                                         mdp_lvds_out: endpoint {
 1497                                         };
 1498                                 };
 1499 
 1500                                 port@1 {
 1501                                         reg = <1>;
 1502                                         mdp_dsi1_out: endpoint {
 1503                                         };
 1504                                 };
 1505 
 1506                                 port@2 {
 1507                                         reg = <2>;
 1508                                         mdp_dsi2_out: endpoint {
 1509                                         };
 1510                                 };
 1511 
 1512                                 port@3 {
 1513                                         reg = <3>;
 1514                                         mdp_dtv_out: endpoint {
 1515                                         };
 1516                                 };
 1517                         };
 1518                 };
 1519 
 1520                 riva: riva-pil@3204000 {
 1521                         compatible = "qcom,riva-pil";
 1522 
 1523                         reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
 1524                         reg-names = "ccu", "dxe", "pmu";
 1525 
 1526                         interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
 1527                                               <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
 1528                         interrupt-names = "wdog", "fatal";
 1529 
 1530                         memory-region = <&wcnss_mem>;
 1531 
 1532                         vddcx-supply = <&pm8921_s3>;
 1533                         vddmx-supply = <&pm8921_l24>;
 1534                         vddpx-supply = <&pm8921_s4>;
 1535 
 1536                         status = "disabled";
 1537 
 1538                         iris {
 1539                                 compatible = "qcom,wcn3660";
 1540 
 1541                                 clocks = <&cxo_board>;
 1542                                 clock-names = "xo";
 1543 
 1544                                 vddxo-supply = <&pm8921_l4>;
 1545                                 vddrfa-supply = <&pm8921_s2>;
 1546                                 vddpa-supply = <&pm8921_l10>;
 1547                                 vdddig-supply = <&pm8921_lvs2>;
 1548                         };
 1549 
 1550                         smd-edge {
 1551                                 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
 1552 
 1553                                 qcom,ipc = <&l2cc 8 25>;
 1554                                 qcom,smd-edge = <6>;
 1555 
 1556                                 label = "riva";
 1557 
 1558                                 wcnss {
 1559                                         compatible = "qcom,wcnss";
 1560                                         qcom,smd-channels = "WCNSS_CTRL";
 1561 
 1562                                         qcom,mmio = <&riva>;
 1563 
 1564                                         bluetooth {
 1565                                                 compatible = "qcom,wcnss-bt";
 1566                                         };
 1567 
 1568                                         wifi {
 1569                                                 compatible = "qcom,wcnss-wlan";
 1570 
 1571                                                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 1572                                                              <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 1573                                                 interrupt-names = "tx", "rx";
 1574 
 1575                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
 1576                                                 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
 1577                                         };
 1578                                 };
 1579                         };
 1580                 };
 1581 
 1582                 etb@1a01000 {
 1583                         compatible = "coresight-etb10", "arm,primecell";
 1584                         reg = <0x1a01000 0x1000>;
 1585 
 1586                         clocks = <&rpmcc RPM_QDSS_CLK>;
 1587                         clock-names = "apb_pclk";
 1588 
 1589                         in-ports {
 1590                                 port {
 1591                                         etb_in: endpoint {
 1592                                                 remote-endpoint = <&replicator_out0>;
 1593                                         };
 1594                                 };
 1595                         };
 1596                 };
 1597 
 1598                 tpiu@1a03000 {
 1599                         compatible = "arm,coresight-tpiu", "arm,primecell";
 1600                         reg = <0x1a03000 0x1000>;
 1601 
 1602                         clocks = <&rpmcc RPM_QDSS_CLK>;
 1603                         clock-names = "apb_pclk";
 1604 
 1605                         in-ports {
 1606                                 port {
 1607                                         tpiu_in: endpoint {
 1608                                                 remote-endpoint = <&replicator_out1>;
 1609                                         };
 1610                                 };
 1611                         };
 1612                 };
 1613 
 1614                 replicator {
 1615                         compatible = "arm,coresight-static-replicator";
 1616 
 1617                         clocks = <&rpmcc RPM_QDSS_CLK>;
 1618                         clock-names = "apb_pclk";
 1619 
 1620                         out-ports {
 1621                                 #address-cells = <1>;
 1622                                 #size-cells = <0>;
 1623 
 1624                                 port@0 {
 1625                                         reg = <0>;
 1626                                         replicator_out0: endpoint {
 1627                                                 remote-endpoint = <&etb_in>;
 1628                                         };
 1629                                 };
 1630                                 port@1 {
 1631                                         reg = <1>;
 1632                                         replicator_out1: endpoint {
 1633                                                 remote-endpoint = <&tpiu_in>;
 1634                                         };
 1635                                 };
 1636                         };
 1637 
 1638                         in-ports {
 1639                                 port {
 1640                                         replicator_in: endpoint {
 1641                                                 remote-endpoint = <&funnel_out>;
 1642                                         };
 1643                                 };
 1644                         };
 1645                 };
 1646 
 1647                 funnel@1a04000 {
 1648                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 1649                         reg = <0x1a04000 0x1000>;
 1650 
 1651                         clocks = <&rpmcc RPM_QDSS_CLK>;
 1652                         clock-names = "apb_pclk";
 1653 
 1654                         in-ports {
 1655                                 #address-cells = <1>;
 1656                                 #size-cells = <0>;
 1657 
 1658                                 /*
 1659                                  * Not described input ports:
 1660                                  * 2 - connected to STM component
 1661                                  * 3 - not-connected
 1662                                  * 6 - not-connected
 1663                                  * 7 - not-connected
 1664                                  */
 1665                                 port@0 {
 1666                                         reg = <0>;
 1667                                         funnel_in0: endpoint {
 1668                                                 remote-endpoint = <&etm0_out>;
 1669                                         };
 1670                                 };
 1671                                 port@1 {
 1672                                         reg = <1>;
 1673                                         funnel_in1: endpoint {
 1674                                                 remote-endpoint = <&etm1_out>;
 1675                                         };
 1676                                 };
 1677                                 port@4 {
 1678                                         reg = <4>;
 1679                                         funnel_in4: endpoint {
 1680                                                 remote-endpoint = <&etm2_out>;
 1681                                         };
 1682                                 };
 1683                                 port@5 {
 1684                                         reg = <5>;
 1685                                         funnel_in5: endpoint {
 1686                                                 remote-endpoint = <&etm3_out>;
 1687                                         };
 1688                                 };
 1689                         };
 1690 
 1691                         out-ports {
 1692                                 port {
 1693                                         funnel_out: endpoint {
 1694                                                 remote-endpoint = <&replicator_in>;
 1695                                         };
 1696                                 };
 1697                         };
 1698                 };
 1699 
 1700                 etm@1a1c000 {
 1701                         compatible = "arm,coresight-etm3x", "arm,primecell";
 1702                         reg = <0x1a1c000 0x1000>;
 1703 
 1704                         clocks = <&rpmcc RPM_QDSS_CLK>;
 1705                         clock-names = "apb_pclk";
 1706 
 1707                         cpu = <&CPU0>;
 1708 
 1709                         out-ports {
 1710                                 port {
 1711                                         etm0_out: endpoint {
 1712                                                 remote-endpoint = <&funnel_in0>;
 1713                                         };
 1714                                 };
 1715                         };
 1716                 };
 1717 
 1718                 etm@1a1d000 {
 1719                         compatible = "arm,coresight-etm3x", "arm,primecell";
 1720                         reg = <0x1a1d000 0x1000>;
 1721 
 1722                         clocks = <&rpmcc RPM_QDSS_CLK>;
 1723                         clock-names = "apb_pclk";
 1724 
 1725                         cpu = <&CPU1>;
 1726 
 1727                         out-ports {
 1728                                 port {
 1729                                         etm1_out: endpoint {
 1730                                                 remote-endpoint = <&funnel_in1>;
 1731                                         };
 1732                                 };
 1733                         };
 1734                 };
 1735 
 1736                 etm@1a1e000 {
 1737                         compatible = "arm,coresight-etm3x", "arm,primecell";
 1738                         reg = <0x1a1e000 0x1000>;
 1739 
 1740                         clocks = <&rpmcc RPM_QDSS_CLK>;
 1741                         clock-names = "apb_pclk";
 1742 
 1743                         cpu = <&CPU2>;
 1744 
 1745                         out-ports {
 1746                                 port {
 1747                                         etm2_out: endpoint {
 1748                                                 remote-endpoint = <&funnel_in4>;
 1749                                         };
 1750                                 };
 1751                         };
 1752                 };
 1753 
 1754                 etm@1a1f000 {
 1755                         compatible = "arm,coresight-etm3x", "arm,primecell";
 1756                         reg = <0x1a1f000 0x1000>;
 1757 
 1758                         clocks = <&rpmcc RPM_QDSS_CLK>;
 1759                         clock-names = "apb_pclk";
 1760 
 1761                         cpu = <&CPU3>;
 1762 
 1763                         out-ports {
 1764                                 port {
 1765                                         etm3_out: endpoint {
 1766                                                 remote-endpoint = <&funnel_in5>;
 1767                                         };
 1768                                 };
 1769                         };
 1770                 };
 1771         };
 1772 };
 1773 #include "qcom-apq8064-pins.dtsi"
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/qcom-apq8064.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/qcom-apq8064.dtsi
