qcom-ipq8064.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0
    2 /dts-v1/;
    3 
    4 #include <dt-bindings/interrupt-controller/arm-gic.h>
    5 #include <dt-bindings/mfd/qcom-rpm.h>
    6 #include <dt-bindings/clock/qcom,rpmcc.h>
    7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
    8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
    9 #include <dt-bindings/gpio/gpio.h>
   10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
   11 #include <dt-bindings/soc/qcom,gsbi.h>
   12 #include <dt-bindings/interrupt-controller/arm-gic.h>
   13 
   14 / {
   15         #address-cells = <1>;
   16         #size-cells = <1>;
   17         model = "Qualcomm IPQ8064";
   18         compatible = "qcom,ipq8064";
   19         interrupt-parent = <&intc>;
   20 
   21         cpus {
   22                 #address-cells = <1>;
   23                 #size-cells = <0>;
   24 
   25                 cpu0: cpu@0 {
   26                         compatible = "qcom,krait";
   27                         enable-method = "qcom,kpss-acc-v1";
   28                         device_type = "cpu";
   29                         reg = <0>;
   30                         next-level-cache = <&L2>;
   31                         qcom,acc = <&acc0>;
   32                         qcom,saw = <&saw0>;
   33                 };
   34 
   35                 cpu1: cpu@1 {
   36                         compatible = "qcom,krait";
   37                         enable-method = "qcom,kpss-acc-v1";
   38                         device_type = "cpu";
   39                         reg = <1>;
   40                         next-level-cache = <&L2>;
   41                         qcom,acc = <&acc1>;
   42                         qcom,saw = <&saw1>;
   43                 };
   44 
   45                 L2: l2-cache {
   46                         compatible = "cache";
   47                         cache-level = <2>;
   48                 };
   49         };
   50 
   51         thermal-zones {
   52                 sensor0-thermal {
   53                         polling-delay-passive = <0>;
   54                         polling-delay = <0>;
   55                         thermal-sensors = <&tsens 0>;
   56 
   57                         trips {
   58                                 cpu-critical {
   59                                         temperature = <105000>;
   60                                         hysteresis = <2000>;
   61                                         type = "critical";
   62                                 };
   63 
   64                                 cpu-hot {
   65                                         temperature = <95000>;
   66                                         hysteresis = <2000>;
   67                                         type = "hot";
   68                                 };
   69                         };
   70                 };
   71 
   72                 sensor1-thermal {
   73                         polling-delay-passive = <0>;
   74                         polling-delay = <0>;
   75                         thermal-sensors = <&tsens 1>;
   76 
   77                         trips {
   78                                 cpu-critical {
   79                                         temperature = <105000>;
   80                                         hysteresis = <2000>;
   81                                         type = "critical";
   82                                 };
   83 
   84                                 cpu-hot {
   85                                         temperature = <95000>;
   86                                         hysteresis = <2000>;
   87                                         type = "hot";
   88                                 };
   89                         };
   90                 };
   91 
   92                 sensor2-thermal {
   93                         polling-delay-passive = <0>;
   94                         polling-delay = <0>;
   95                         thermal-sensors = <&tsens 2>;
   96 
   97                         trips {
   98                                 cpu-critical {
   99                                         temperature = <105000>;
  100                                         hysteresis = <2000>;
  101                                         type = "critical";
  102                                 };
  103 
  104                                 cpu-hot {
  105                                         temperature = <95000>;
  106                                         hysteresis = <2000>;
  107                                         type = "hot";
  108                                 };
  109                         };
  110                 };
  111 
  112                 sensor3-thermal {
  113                         polling-delay-passive = <0>;
  114                         polling-delay = <0>;
  115                         thermal-sensors = <&tsens 3>;
  116 
  117                         trips {
  118                                 cpu-critical {
  119                                         temperature = <105000>;
  120                                         hysteresis = <2000>;
  121                                         type = "critical";
  122                                 };
  123 
  124                                 cpu-hot {
  125                                         temperature = <95000>;
  126                                         hysteresis = <2000>;
  127                                         type = "hot";
  128                                 };
  129                         };
  130                 };
  131 
  132                 sensor4-thermal {
  133                         polling-delay-passive = <0>;
  134                         polling-delay = <0>;
  135                         thermal-sensors = <&tsens 4>;
  136 
  137                         trips {
  138                                 cpu-critical {
  139                                         temperature = <105000>;
  140                                         hysteresis = <2000>;
  141                                         type = "critical";
  142                                 };
  143 
  144                                 cpu-hot {
  145                                         temperature = <95000>;
  146                                         hysteresis = <2000>;
  147                                         type = "hot";
  148                                 };
  149                         };
  150                 };
  151 
  152                 sensor5-thermal {
  153                         polling-delay-passive = <0>;
  154                         polling-delay = <0>;
  155                         thermal-sensors = <&tsens 5>;
  156 
  157                         trips {
  158                                 cpu-critical {
  159                                         temperature = <105000>;
  160                                         hysteresis = <2000>;
  161                                         type = "critical";
  162                                 };
  163 
  164                                 cpu-hot {
  165                                         temperature = <95000>;
  166                                         hysteresis = <2000>;
  167                                         type = "hot";
  168                                 };
  169                         };
  170                 };
  171 
  172                 sensor6-thermal {
  173                         polling-delay-passive = <0>;
  174                         polling-delay = <0>;
  175                         thermal-sensors = <&tsens 6>;
  176 
  177                         trips {
  178                                 cpu-critical {
  179                                         temperature = <105000>;
  180                                         hysteresis = <2000>;
  181                                         type = "critical";
  182                                 };
  183 
  184                                 cpu-hot {
  185                                         temperature = <95000>;
  186                                         hysteresis = <2000>;
  187                                         type = "hot";
  188                                 };
  189                         };
  190                 };
  191 
  192                 sensor7-thermal {
  193                         polling-delay-passive = <0>;
  194                         polling-delay = <0>;
  195                         thermal-sensors = <&tsens 7>;
  196 
  197                         trips {
  198                                 cpu-critical {
  199                                         temperature = <105000>;
  200                                         hysteresis = <2000>;
  201                                         type = "critical";
  202                                 };
  203 
  204                                 cpu-hot {
  205                                         temperature = <95000>;
  206                                         hysteresis = <2000>;
  207                                         type = "hot";
  208                                 };
  209                         };
  210                 };
  211 
  212                 sensor8-thermal {
  213                         polling-delay-passive = <0>;
  214                         polling-delay = <0>;
  215                         thermal-sensors = <&tsens 8>;
  216 
  217                         trips {
  218                                 cpu-critical {
  219                                         temperature = <105000>;
  220                                         hysteresis = <2000>;
  221                                         type = "critical";
  222                                 };
  223 
  224                                 cpu-hot {
  225                                         temperature = <95000>;
  226                                         hysteresis = <2000>;
  227                                         type = "hot";
  228                                 };
  229                         };
  230                 };
  231 
  232                 sensor9-thermal {
  233                         polling-delay-passive = <0>;
  234                         polling-delay = <0>;
  235                         thermal-sensors = <&tsens 9>;
  236 
  237                         trips {
  238                                 cpu-critical {
  239                                         temperature = <105000>;
  240                                         hysteresis = <2000>;
  241                                         type = "critical";
  242                                 };
  243 
  244                                 cpu-hot {
  245                                         temperature = <95000>;
  246                                         hysteresis = <2000>;
  247                                         type = "hot";
  248                                 };
  249                         };
  250                 };
  251 
  252                 sensor10-thermal {
  253                         polling-delay-passive = <0>;
  254                         polling-delay = <0>;
  255                         thermal-sensors = <&tsens 10>;
  256 
  257                         trips {
  258                                 cpu-critical {
  259                                         temperature = <105000>;
  260                                         hysteresis = <2000>;
  261                                         type = "critical";
  262                                 };
  263 
  264                                 cpu-hot {
  265                                         temperature = <95000>;
  266                                         hysteresis = <2000>;
  267                                         type = "hot";
  268                                 };
  269                         };
  270                 };
  271         };
  272 
  273         memory {
  274                 device_type = "memory";
  275                 reg = <0x0 0x0>;
  276         };
  277 
  278         cpu-pmu {
  279                 compatible = "qcom,krait-pmu";
  280                 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  281                                           IRQ_TYPE_LEVEL_HIGH)>;
  282         };
  283 
  284         reserved-memory {
  285                 #address-cells = <1>;
  286                 #size-cells = <1>;
  287                 ranges;
  288 
  289                 nss@40000000 {
  290                         reg = <0x40000000 0x1000000>;
  291                         no-map;
  292                 };
  293 
  294                 smem: smem@41000000 {
  295                         compatible = "qcom,smem";
  296                         reg = <0x41000000 0x200000>;
  297                         no-map;
  298 
  299                         hwlocks = <&sfpb_mutex 3>;
  300                 };
  301         };
  302 
  303         clocks {
  304                 cxo_board: cxo_board {
  305                         compatible = "fixed-clock";
  306                         #clock-cells = <0>;
  307                         clock-frequency = <25000000>;
  308                 };
  309 
  310                 pxo_board: pxo_board {
  311                         compatible = "fixed-clock";
  312                         #clock-cells = <0>;
  313                         clock-frequency = <25000000>;
  314                 };
  315 
  316                 sleep_clk: sleep_clk {
  317                         compatible = "fixed-clock";
  318                         clock-frequency = <32768>;
  319                         #clock-cells = <0>;
  320                 };
  321         };
  322 
  323         firmware {
  324                 scm {
  325                         compatible = "qcom,scm-ipq806x", "qcom,scm";
  326                 };
  327         };
  328 
  329         soc: soc {
  330                 #address-cells = <1>;
  331                 #size-cells = <1>;
  332                 ranges;
  333                 compatible = "simple-bus";
  334 
  335                 lpass@28100000 {
  336                         compatible = "qcom,lpass-cpu";
  337                         status = "disabled";
  338                         clocks = <&lcc AHBIX_CLK>,
  339                                         <&lcc MI2S_OSR_CLK>,
  340                                         <&lcc MI2S_BIT_CLK>;
  341                         clock-names = "ahbix-clk",
  342                                         "mi2s-osr-clk",
  343                                         "mi2s-bit-clk";
  344                         interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
  345                         interrupt-names = "lpass-irq-lpaif";
  346                         reg = <0x28100000 0x10000>;
  347                         reg-names = "lpass-lpaif";
  348                 };
  349 
  350                 qcom_pinmux: pinmux@800000 {
  351                         compatible = "qcom,ipq8064-pinctrl";
  352                         reg = <0x800000 0x4000>;
  353 
  354                         gpio-controller;
  355                         gpio-ranges = <&qcom_pinmux 0 0 69>;
  356                         #gpio-cells = <2>;
  357                         interrupt-controller;
  358                         #interrupt-cells = <2>;
  359                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  360 
  361                         pcie0_pins: pcie0_pinmux {
  362                                 mux {
  363                                         pins = "gpio3";
  364                                         function = "pcie1_rst";
  365                                         drive-strength = <12>;
  366                                         bias-disable;
  367                                 };
  368                         };
  369 
  370                         pcie1_pins: pcie1_pinmux {
  371                                 mux {
  372                                         pins = "gpio48";
  373                                         function = "pcie2_rst";
  374                                         drive-strength = <12>;
  375                                         bias-disable;
  376                                 };
  377                         };
  378 
  379                         pcie2_pins: pcie2_pinmux {
  380                                 mux {
  381                                         pins = "gpio63";
  382                                         function = "pcie3_rst";
  383                                         drive-strength = <12>;
  384                                         bias-disable;
  385                                 };
  386                         };
  387 
  388                         i2c4_pins: i2c4-default {
  389                                 pins = "gpio12", "gpio13";
  390                                 function = "gsbi4";
  391                                 drive-strength = <12>;
  392                                 bias-disable;
  393                         };
  394 
  395                         spi_pins: spi_pins {
  396                                 mux {
  397                                         pins = "gpio18", "gpio19", "gpio21";
  398                                         function = "gsbi5";
  399                                         drive-strength = <10>;
  400                                         bias-none;
  401                                 };
  402                         };
  403 
  404                         leds_pins: leds_pins {
  405                                 mux {
  406                                         pins = "gpio7", "gpio8", "gpio9",
  407                                                "gpio26", "gpio53";
  408                                         function = "gpio";
  409                                         drive-strength = <2>;
  410                                         bias-pull-down;
  411                                         output-low;
  412                                 };
  413                         };
  414 
  415                         buttons_pins: buttons_pins {
  416                                 mux {
  417                                         pins = "gpio54";
  418                                         drive-strength = <2>;
  419                                         bias-pull-up;
  420                                 };
  421                         };
  422 
  423                         nand_pins: nand_pins {
  424                                 mux {
  425                                         pins = "gpio34", "gpio35", "gpio36",
  426                                                "gpio37", "gpio38", "gpio39",
  427                                                "gpio40", "gpio41", "gpio42",
  428                                                "gpio43", "gpio44", "gpio45",
  429                                                "gpio46", "gpio47";
  430                                         function = "nand";
  431                                         drive-strength = <10>;
  432                                         bias-disable;
  433                                 };
  434 
  435                                 pullups {
  436                                         pins = "gpio39";
  437                                         function = "nand";
  438                                         drive-strength = <10>;
  439                                         bias-pull-up;
  440                                 };
  441 
  442                                 hold {
  443                                         pins = "gpio40", "gpio41", "gpio42",
  444                                                "gpio43", "gpio44", "gpio45",
  445                                                "gpio46", "gpio47";
  446                                         function = "nand";
  447                                         drive-strength = <10>;
  448                                         bias-bus-hold;
  449                                 };
  450                         };
  451 
  452                         mdio0_pins: mdio0-pins {
  453                                 mux {
  454                                         pins = "gpio0", "gpio1";
  455                                         function = "mdio";
  456                                         drive-strength = <8>;
  457                                         bias-disable;
  458                                 };
  459                         };
  460 
  461                         rgmii2_pins: rgmii2-pins {
  462                                 mux {
  463                                         pins = "gpio27", "gpio28", "gpio29",
  464                                                "gpio30", "gpio31", "gpio32",
  465                                                "gpio51", "gpio52", "gpio59",
  466                                                "gpio60", "gpio61", "gpio62";
  467                                         function = "rgmii2";
  468                                         drive-strength = <8>;
  469                                         bias-disable;
  470                                 };
  471                         };
  472                 };
  473 
  474                 intc: interrupt-controller@2000000 {
  475                         compatible = "qcom,msm-qgic2";
  476                         interrupt-controller;
  477                         #interrupt-cells = <3>;
  478                         reg = <0x02000000 0x1000>,
  479                               <0x02002000 0x1000>;
  480                 };
  481 
  482                 timer@200a000 {
  483                         compatible = "qcom,kpss-timer",
  484                                      "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
  485                         interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
  486                                                  IRQ_TYPE_EDGE_RISING)>,
  487                                      <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
  488                                                  IRQ_TYPE_EDGE_RISING)>,
  489                                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
  490                                                  IRQ_TYPE_EDGE_RISING)>,
  491                                      <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
  492                                                  IRQ_TYPE_EDGE_RISING)>,
  493                                      <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
  494                                                  IRQ_TYPE_EDGE_RISING)>;
  495                         reg = <0x0200a000 0x100>;
  496                         clock-frequency = <25000000>,
  497                                           <32768>;
  498                         clocks = <&sleep_clk>;
  499                         clock-names = "sleep";
  500                         cpu-offset = <0x80000>;
  501                 };
  502 
  503                 acc0: clock-controller@2088000 {
  504                         compatible = "qcom,kpss-acc-v1";
  505                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
  506                 };
  507 
  508                 acc1: clock-controller@2098000 {
  509                         compatible = "qcom,kpss-acc-v1";
  510                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
  511                 };
  512 
  513                 adm_dma: dma-controller@18300000 {
  514                         compatible = "qcom,adm";
  515                         reg = <0x18300000 0x100000>;
  516                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
  517                         #dma-cells = <1>;
  518 
  519                         clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
  520                         clock-names = "core", "iface";
  521 
  522                         resets = <&gcc ADM0_RESET>,
  523                                  <&gcc ADM0_PBUS_RESET>,
  524                                  <&gcc ADM0_C0_RESET>,
  525                                  <&gcc ADM0_C1_RESET>,
  526                                  <&gcc ADM0_C2_RESET>;
  527                         reset-names = "clk", "pbus", "c0", "c1", "c2";
  528                         qcom,ee = <0>;
  529 
  530                         status = "disabled";
  531                 };
  532 
  533                 saw0: regulator@2089000 {
  534                         compatible = "qcom,saw2";
  535                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
  536                         regulator;
  537                 };
  538 
  539                 saw1: regulator@2099000 {
  540                         compatible = "qcom,saw2";
  541                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
  542                         regulator;
  543                 };
  544 
  545                 gsbi1: gsbi@12440000 {
  546                         compatible = "qcom,gsbi-v1.0.0";
  547                         reg = <0x12440000 0x100>;
  548                         cell-index = <1>;
  549                         clocks = <&gcc GSBI1_H_CLK>;
  550                         clock-names = "iface";
  551                         #address-cells = <1>;
  552                         #size-cells = <1>;
  553                         ranges;
  554 
  555                         syscon-tcsr = <&tcsr>;
  556 
  557                         status = "disabled";
  558 
  559                         gsbi1_serial: serial@12450000 {
  560                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  561                                 reg = <0x12450000 0x100>,
  562                                       <0x12400000 0x03>;
  563                                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
  564                                 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
  565                                 clock-names = "core", "iface";
  566 
  567                                 status = "disabled";
  568                         };
  569 
  570                         gsbi1_i2c: i2c@12460000 {
  571                                 compatible = "qcom,i2c-qup-v1.1.1";
  572                                 reg = <0x12460000 0x1000>;
  573                                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
  574                                 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
  575                                 clock-names = "core", "iface";
  576                                 #address-cells = <1>;
  577                                 #size-cells = <0>;
  578 
  579                                 status = "disabled";
  580                         };
  581                 };
  582 
  583                 gsbi2: gsbi@12480000 {
  584                         compatible = "qcom,gsbi-v1.0.0";
  585                         cell-index = <2>;
  586                         reg = <0x12480000 0x100>;
  587                         clocks = <&gcc GSBI2_H_CLK>;
  588                         clock-names = "iface";
  589                         #address-cells = <1>;
  590                         #size-cells = <1>;
  591                         ranges;
  592                         status = "disabled";
  593 
  594                         syscon-tcsr = <&tcsr>;
  595 
  596                         gsbi2_serial: serial@12490000 {
  597                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  598                                 reg = <0x12490000 0x1000>,
  599                                       <0x12480000 0x1000>;
  600                                 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
  601                                 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
  602                                 clock-names = "core", "iface";
  603                                 status = "disabled";
  604                         };
  605 
  606                         gsbi2_i2c: i2c@124a0000 {
  607                                 compatible = "qcom,i2c-qup-v1.1.1";
  608                                 reg = <0x124a0000 0x1000>;
  609                                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
  610 
  611                                 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
  612                                 clock-names = "core", "iface";
  613                                 status = "disabled";
  614 
  615                                 #address-cells = <1>;
  616                                 #size-cells = <0>;
  617                         };
  618                 };
  619 
  620                 gsbi4: gsbi@16300000 {
  621                         compatible = "qcom,gsbi-v1.0.0";
  622                         cell-index = <4>;
  623                         reg = <0x16300000 0x100>;
  624                         clocks = <&gcc GSBI4_H_CLK>;
  625                         clock-names = "iface";
  626                         #address-cells = <1>;
  627                         #size-cells = <1>;
  628                         ranges;
  629                         status = "disabled";
  630 
  631                         syscon-tcsr = <&tcsr>;
  632 
  633                         gsbi4_serial: serial@16340000 {
  634                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  635                                 reg = <0x16340000 0x1000>,
  636                                       <0x16300000 0x1000>;
  637                                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
  638                                 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
  639                                 clock-names = "core", "iface";
  640                                 status = "disabled";
  641                         };
  642 
  643                         i2c@16380000 {
  644                                 compatible = "qcom,i2c-qup-v1.1.1";
  645                                 reg = <0x16380000 0x1000>;
  646                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
  647 
  648                                 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
  649                                 clock-names = "core", "iface";
  650                                 status = "disabled";
  651 
  652                                 #address-cells = <1>;
  653                                 #size-cells = <0>;
  654                         };
  655                 };
  656 
  657                 gsbi5: gsbi@1a200000 {
  658                         compatible = "qcom,gsbi-v1.0.0";
  659                         cell-index = <5>;
  660                         reg = <0x1a200000 0x100>;
  661                         clocks = <&gcc GSBI5_H_CLK>;
  662                         clock-names = "iface";
  663                         #address-cells = <1>;
  664                         #size-cells = <1>;
  665                         ranges;
  666                         status = "disabled";
  667 
  668                         syscon-tcsr = <&tcsr>;
  669 
  670                         gsbi5_serial: serial@1a240000 {
  671                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  672                                 reg = <0x1a240000 0x1000>,
  673                                       <0x1a200000 0x1000>;
  674                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  675                                 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
  676                                 clock-names = "core", "iface";
  677                                 status = "disabled";
  678                         };
  679 
  680                         i2c@1a280000 {
  681                                 compatible = "qcom,i2c-qup-v1.1.1";
  682                                 reg = <0x1a280000 0x1000>;
  683                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
  684 
  685                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
  686                                 clock-names = "core", "iface";
  687                                 status = "disabled";
  688 
  689                                 #address-cells = <1>;
  690                                 #size-cells = <0>;
  691                         };
  692 
  693                         spi@1a280000 {
  694                                 compatible = "qcom,spi-qup-v1.1.1";
  695                                 reg = <0x1a280000 0x1000>;
  696                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
  697 
  698                                 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
  699                                 clock-names = "core", "iface";
  700                                 status = "disabled";
  701 
  702                                 #address-cells = <1>;
  703                                 #size-cells = <0>;
  704                         };
  705                 };
  706 
  707                 gsbi6: gsbi@16500000 {
  708                         compatible = "qcom,gsbi-v1.0.0";
  709                         reg = <0x16500000 0x100>;
  710                         cell-index = <6>;
  711                         clocks = <&gcc GSBI6_H_CLK>;
  712                         clock-names = "iface";
  713                         #address-cells = <1>;
  714                         #size-cells = <1>;
  715                         ranges;
  716 
  717                         syscon-tcsr = <&tcsr>;
  718 
  719                         status = "disabled";
  720 
  721                         gsbi6_i2c: i2c@16580000 {
  722                                 compatible = "qcom,i2c-qup-v1.1.1";
  723                                 reg = <0x16580000 0x1000>;
  724                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
  725 
  726                                 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
  727                                 clock-names = "core", "iface";
  728 
  729                                 #address-cells = <1>;
  730                                 #size-cells = <0>;
  731 
  732                                 status = "disabled";
  733                         };
  734 
  735                         gsbi6_spi: spi@16580000 {
  736                                 compatible = "qcom,spi-qup-v1.1.1";
  737                                 reg = <0x16580000 0x1000>;
  738                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
  739 
  740                                 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
  741                                 clock-names = "core", "iface";
  742 
  743                                 #address-cells = <1>;
  744                                 #size-cells = <0>;
  745 
  746                                 status = "disabled";
  747                         };
  748                 };
  749 
  750                 gsbi7: gsbi@16600000 {
  751                         status = "disabled";
  752                         compatible = "qcom,gsbi-v1.0.0";
  753                         cell-index = <7>;
  754                         reg = <0x16600000 0x100>;
  755                         clocks = <&gcc GSBI7_H_CLK>;
  756                         clock-names = "iface";
  757                         #address-cells = <1>;
  758                         #size-cells = <1>;
  759                         ranges;
  760                         syscon-tcsr = <&tcsr>;
  761 
  762                         gsbi7_serial: serial@16640000 {
  763                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  764                                 reg = <0x16640000 0x1000>,
  765                                       <0x16600000 0x1000>;
  766                                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
  767                                 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
  768                                 clock-names = "core", "iface";
  769                                 status = "disabled";
  770                         };
  771 
  772                         gsbi7_i2c: i2c@16680000 {
  773                                 compatible = "qcom,i2c-qup-v1.1.1";
  774                                 reg = <0x16680000 0x1000>;
  775                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
  776 
  777                                 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
  778                                 clock-names = "core", "iface";
  779 
  780                                 #address-cells = <1>;
  781                                 #size-cells = <0>;
  782 
  783                                 status = "disabled";
  784                         };
  785                 };
  786 
  787                 rng@1a500000 {
  788                         compatible = "qcom,prng";
  789                         reg = <0x1a500000 0x200>;
  790                         clocks = <&gcc PRNG_CLK>;
  791                         clock-names = "core";
  792                 };
  793 
  794                 sata_phy: sata-phy@1b400000 {
  795                         compatible = "qcom,ipq806x-sata-phy";
  796                         reg = <0x1b400000 0x200>;
  797 
  798                         clocks = <&gcc SATA_PHY_CFG_CLK>;
  799                         clock-names = "cfg";
  800 
  801                         #phy-cells = <0>;
  802                         status = "disabled";
  803                 };
  804 
  805                 nand: nand-controller@1ac00000 {
  806                         compatible = "qcom,ipq806x-nand";
  807                         reg = <0x1ac00000 0x800>;
  808 
  809                         pinctrl-0 = <&nand_pins>;
  810                         pinctrl-names = "default";
  811 
  812                         clocks = <&gcc EBI2_CLK>,
  813                                  <&gcc EBI2_AON_CLK>;
  814                         clock-names = "core", "aon";
  815 
  816                         dmas = <&adm_dma 3>;
  817                         dma-names = "rxtx";
  818                         qcom,cmd-crci = <15>;
  819                         qcom,data-crci = <3>;
  820 
  821                         #address-cells = <1>;
  822                         #size-cells = <0>;
  823 
  824                         status = "disabled";
  825                 };
  826 
  827                 sata: sata@29000000 {
  828                         compatible = "qcom,ipq806x-ahci", "generic-ahci";
  829                         reg = <0x29000000 0x180>;
  830 
  831                         interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
  832 
  833                         clocks = <&gcc SFAB_SATA_S_H_CLK>,
  834                                  <&gcc SATA_H_CLK>,
  835                                  <&gcc SATA_A_CLK>,
  836                                  <&gcc SATA_RXOOB_CLK>,
  837                                  <&gcc SATA_PMALIVE_CLK>;
  838                         clock-names = "slave_face", "iface", "core",
  839                                         "rxoob", "pmalive";
  840 
  841                         assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
  842                         assigned-clock-rates = <100000000>, <100000000>;
  843 
  844                         phys = <&sata_phy>;
  845                         phy-names = "sata-phy";
  846                         status = "disabled";
  847                 };
  848 
  849                 qcom,ssbi@500000 {
  850                         compatible = "qcom,ssbi";
  851                         reg = <0x00500000 0x1000>;
  852                         qcom,controller-type = "pmic-arbiter";
  853                 };
  854 
  855                 qfprom: qfprom@700000 {
  856                         compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
  857                         reg = <0x00700000 0x1000>;
  858                         #address-cells = <1>;
  859                         #size-cells = <1>;
  860                         speedbin_efuse: speedbin@c0 {
  861                                 reg = <0xc0 0x4>;
  862                         };
  863                         tsens_calib: calib@400 {
  864                                 reg = <0x400 0xb>;
  865                         };
  866                         tsens_calib_backup: calib_backup@410 {
  867                                 reg = <0x410 0xb>;
  868                         };
  869                 };
  870 
  871                 gcc: clock-controller@900000 {
  872                         compatible = "qcom,gcc-ipq8064", "syscon";
  873                         clocks = <&pxo_board>, <&cxo_board>;
  874                         clock-names = "pxo", "cxo";
  875                         reg = <0x00900000 0x4000>;
  876                         #clock-cells = <1>;
  877                         #reset-cells = <1>;
  878                         #power-domain-cells = <1>;
  879 
  880                         tsens: thermal-sensor@900000 {
  881                                 compatible = "qcom,ipq8064-tsens";
  882 
  883                                 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
  884                                 nvmem-cell-names = "calib", "calib_backup";
  885                                 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
  886                                 interrupt-names = "uplow";
  887 
  888                                 #qcom,sensors = <11>;
  889                                 #thermal-sensor-cells = <1>;
  890                         };
  891                 };
  892 
  893                 rpm: rpm@108000 {
  894                         compatible = "qcom,rpm-ipq8064";
  895                         reg = <0x108000 0x1000>;
  896                         qcom,ipc = <&l2cc 0x8 2>;
  897 
  898                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
  899                                         <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
  900                                         <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
  901                         interrupt-names = "ack", "err", "wakeup";
  902 
  903                         clocks = <&gcc RPM_MSG_RAM_H_CLK>;
  904                         clock-names = "ram";
  905 
  906                         rpmcc: clock-controller {
  907                                 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
  908                                 #clock-cells = <1>;
  909                                 clocks = <&pxo_board>;
  910                                 clock-names = "pxo";
  911                         };
  912                 };
  913 
  914                 tcsr: syscon@1a400000 {
  915                         compatible = "qcom,tcsr-ipq8064", "syscon";
  916                         reg = <0x1a400000 0x100>;
  917                 };
  918 
  919                 l2cc: clock-controller@2011000 {
  920                         compatible = "qcom,kpss-gcc", "syscon";
  921                         reg = <0x2011000 0x1000>;
  922                         clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
  923                         clock-names = "pll8_vote", "pxo";
  924                         clock-output-names = "acpu_l2_aux";
  925                 };
  926 
  927                 lcc: clock-controller@28000000 {
  928                         compatible = "qcom,lcc-ipq8064";
  929                         reg = <0x28000000 0x1000>;
  930                         #clock-cells = <1>;
  931                         #reset-cells = <1>;
  932                 };
  933 
  934                 pcie0: pci@1b500000 {
  935                         compatible = "qcom,pcie-ipq8064";
  936                         reg = <0x1b500000 0x1000
  937                                0x1b502000 0x80
  938                                0x1b600000 0x100
  939                                0x0ff00000 0x100000>;
  940                         reg-names = "dbi", "elbi", "parf", "config";
  941                         device_type = "pci";
  942                         linux,pci-domain = <0>;
  943                         bus-range = <0x00 0xff>;
  944                         num-lanes = <1>;
  945                         #address-cells = <3>;
  946                         #size-cells = <2>;
  947 
  948                         ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000   /* downstream I/O */
  949                                   0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
  950 
  951                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  952                         interrupt-names = "msi";
  953                         #interrupt-cells = <1>;
  954                         interrupt-map-mask = <0 0 0 0x7>;
  955                         interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
  956                                         <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
  957                                         <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
  958                                         <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
  959 
  960                         clocks = <&gcc PCIE_A_CLK>,
  961                                  <&gcc PCIE_H_CLK>,
  962                                  <&gcc PCIE_PHY_CLK>,
  963                                  <&gcc PCIE_AUX_CLK>,
  964                                  <&gcc PCIE_ALT_REF_CLK>;
  965                         clock-names = "core", "iface", "phy", "aux", "ref";
  966 
  967                         assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
  968                         assigned-clock-rates = <100000000>;
  969 
  970                         resets = <&gcc PCIE_ACLK_RESET>,
  971                                  <&gcc PCIE_HCLK_RESET>,
  972                                  <&gcc PCIE_POR_RESET>,
  973                                  <&gcc PCIE_PCI_RESET>,
  974                                  <&gcc PCIE_PHY_RESET>,
  975                                  <&gcc PCIE_EXT_RESET>;
  976                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
  977 
  978                         pinctrl-0 = <&pcie0_pins>;
  979                         pinctrl-names = "default";
  980 
  981                         status = "disabled";
  982                         perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
  983                 };
  984 
  985                 pcie1: pci@1b700000 {
  986                         compatible = "qcom,pcie-ipq8064";
  987                         reg = <0x1b700000 0x1000
  988                                0x1b702000 0x80
  989                                0x1b800000 0x100
  990                                0x31f00000 0x100000>;
  991                         reg-names = "dbi", "elbi", "parf", "config";
  992                         device_type = "pci";
  993                         linux,pci-domain = <1>;
  994                         bus-range = <0x00 0xff>;
  995                         num-lanes = <1>;
  996                         #address-cells = <3>;
  997                         #size-cells = <2>;
  998 
  999                         ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000   /* downstream I/O */
 1000                                   0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
 1001 
 1002                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 1003                         interrupt-names = "msi";
 1004                         #interrupt-cells = <1>;
 1005                         interrupt-map-mask = <0 0 0 0x7>;
 1006                         interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 1007                                         <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 1008                                         <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 1009                                         <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 1010 
 1011                         clocks = <&gcc PCIE_1_A_CLK>,
 1012                                  <&gcc PCIE_1_H_CLK>,
 1013                                  <&gcc PCIE_1_PHY_CLK>,
 1014                                  <&gcc PCIE_1_AUX_CLK>,
 1015                                  <&gcc PCIE_1_ALT_REF_CLK>;
 1016                         clock-names = "core", "iface", "phy", "aux", "ref";
 1017 
 1018                         assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
 1019                         assigned-clock-rates = <100000000>;
 1020 
 1021                         resets = <&gcc PCIE_1_ACLK_RESET>,
 1022                                  <&gcc PCIE_1_HCLK_RESET>,
 1023                                  <&gcc PCIE_1_POR_RESET>,
 1024                                  <&gcc PCIE_1_PCI_RESET>,
 1025                                  <&gcc PCIE_1_PHY_RESET>,
 1026                                  <&gcc PCIE_1_EXT_RESET>;
 1027                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 1028 
 1029                         pinctrl-0 = <&pcie1_pins>;
 1030                         pinctrl-names = "default";
 1031 
 1032                         status = "disabled";
 1033                         perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
 1034                 };
 1035 
 1036                 pcie2: pci@1b900000 {
 1037                         compatible = "qcom,pcie-ipq8064";
 1038                         reg = <0x1b900000 0x1000
 1039                                0x1b902000 0x80
 1040                                0x1ba00000 0x100
 1041                                0x35f00000 0x100000>;
 1042                         reg-names = "dbi", "elbi", "parf", "config";
 1043                         device_type = "pci";
 1044                         linux,pci-domain = <2>;
 1045                         bus-range = <0x00 0xff>;
 1046                         num-lanes = <1>;
 1047                         #address-cells = <3>;
 1048                         #size-cells = <2>;
 1049 
 1050                         ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000   /* downstream I/O */
 1051                                   0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
 1052 
 1053                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 1054                         interrupt-names = "msi";
 1055                         #interrupt-cells = <1>;
 1056                         interrupt-map-mask = <0 0 0 0x7>;
 1057                         interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 1058                                         <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 1059                                         <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 1060                                         <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 1061 
 1062                         clocks = <&gcc PCIE_2_A_CLK>,
 1063                                  <&gcc PCIE_2_H_CLK>,
 1064                                  <&gcc PCIE_2_PHY_CLK>,
 1065                                  <&gcc PCIE_2_AUX_CLK>,
 1066                                  <&gcc PCIE_2_ALT_REF_CLK>;
 1067                         clock-names = "core", "iface", "phy", "aux", "ref";
 1068 
 1069                         assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
 1070                         assigned-clock-rates = <100000000>;
 1071 
 1072                         resets = <&gcc PCIE_2_ACLK_RESET>,
 1073                                  <&gcc PCIE_2_HCLK_RESET>,
 1074                                  <&gcc PCIE_2_POR_RESET>,
 1075                                  <&gcc PCIE_2_PCI_RESET>,
 1076                                  <&gcc PCIE_2_PHY_RESET>,
 1077                                  <&gcc PCIE_2_EXT_RESET>;
 1078                         reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 1079 
 1080                         pinctrl-0 = <&pcie2_pins>;
 1081                         pinctrl-names = "default";
 1082 
 1083                         status = "disabled";
 1084                         perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
 1085                 };
 1086 
 1087                 nss_common: syscon@03000000 {
 1088                         compatible = "syscon";
 1089                         reg = <0x03000000 0x0000FFFF>;
 1090                 };
 1091 
 1092                 qsgmii_csr: syscon@1bb00000 {
 1093                         compatible = "syscon";
 1094                         reg = <0x1bb00000 0x000001FF>;
 1095                 };
 1096 
 1097                 stmmac_axi_setup: stmmac-axi-config {
 1098                         snps,wr_osr_lmt = <7>;
 1099                         snps,rd_osr_lmt = <7>;
 1100                         snps,blen = <16 0 0 0 0 0 0>;
 1101                 };
 1102 
 1103                 gmac0: ethernet@37000000 {
 1104                         device_type = "network";
 1105                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
 1106                         reg = <0x37000000 0x200000>;
 1107                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 1108                         interrupt-names = "macirq";
 1109 
 1110                         snps,axi-config = <&stmmac_axi_setup>;
 1111                         snps,pbl = <32>;
 1112                         snps,aal;
 1113 
 1114                         qcom,nss-common = <&nss_common>;
 1115                         qcom,qsgmii-csr = <&qsgmii_csr>;
 1116 
 1117                         clocks = <&gcc GMAC_CORE1_CLK>;
 1118                         clock-names = "stmmaceth";
 1119 
 1120                         resets = <&gcc GMAC_CORE1_RESET>,
 1121                                  <&gcc GMAC_AHB_RESET>;
 1122                         reset-names = "stmmaceth", "ahb";
 1123 
 1124                         status = "disabled";
 1125                 };
 1126 
 1127                 gmac1: ethernet@37200000 {
 1128                         device_type = "network";
 1129                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
 1130                         reg = <0x37200000 0x200000>;
 1131                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 1132                         interrupt-names = "macirq";
 1133 
 1134                         snps,axi-config = <&stmmac_axi_setup>;
 1135                         snps,pbl = <32>;
 1136                         snps,aal;
 1137 
 1138                         qcom,nss-common = <&nss_common>;
 1139                         qcom,qsgmii-csr = <&qsgmii_csr>;
 1140 
 1141                         clocks = <&gcc GMAC_CORE2_CLK>;
 1142                         clock-names = "stmmaceth";
 1143 
 1144                         resets = <&gcc GMAC_CORE2_RESET>,
 1145                                  <&gcc GMAC_AHB_RESET>;
 1146                         reset-names = "stmmaceth", "ahb";
 1147 
 1148                         status = "disabled";
 1149                 };
 1150 
 1151                 gmac2: ethernet@37400000 {
 1152                         device_type = "network";
 1153                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
 1154                         reg = <0x37400000 0x200000>;
 1155                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 1156                         interrupt-names = "macirq";
 1157 
 1158                         snps,axi-config = <&stmmac_axi_setup>;
 1159                         snps,pbl = <32>;
 1160                         snps,aal;
 1161 
 1162                         qcom,nss-common = <&nss_common>;
 1163                         qcom,qsgmii-csr = <&qsgmii_csr>;
 1164 
 1165                         clocks = <&gcc GMAC_CORE3_CLK>;
 1166                         clock-names = "stmmaceth";
 1167 
 1168                         resets = <&gcc GMAC_CORE3_RESET>,
 1169                                  <&gcc GMAC_AHB_RESET>;
 1170                         reset-names = "stmmaceth", "ahb";
 1171 
 1172                         status = "disabled";
 1173                 };
 1174 
 1175                 gmac3: ethernet@37600000 {
 1176                         device_type = "network";
 1177                         compatible = "qcom,ipq806x-gmac", "snps,dwmac";
 1178                         reg = <0x37600000 0x200000>;
 1179                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 1180                         interrupt-names = "macirq";
 1181 
 1182                         snps,axi-config = <&stmmac_axi_setup>;
 1183                         snps,pbl = <32>;
 1184                         snps,aal;
 1185 
 1186                         qcom,nss-common = <&nss_common>;
 1187                         qcom,qsgmii-csr = <&qsgmii_csr>;
 1188 
 1189                         clocks = <&gcc GMAC_CORE4_CLK>;
 1190                         clock-names = "stmmaceth";
 1191 
 1192                         resets = <&gcc GMAC_CORE4_RESET>,
 1193                                  <&gcc GMAC_AHB_RESET>;
 1194                         reset-names = "stmmaceth", "ahb";
 1195 
 1196                         status = "disabled";
 1197                 };
 1198 
 1199                 hs_phy_0: phy@100f8800 {
 1200                         compatible = "qcom,ipq806x-usb-phy-hs";
 1201                         reg = <0x100f8800 0x30>;
 1202                         clocks = <&gcc USB30_0_UTMI_CLK>;
 1203                         clock-names = "ref";
 1204                         #phy-cells = <0>;
 1205 
 1206                         status = "disabled";
 1207                 };
 1208 
 1209                 ss_phy_0: phy@100f8830 {
 1210                         compatible = "qcom,ipq806x-usb-phy-ss";
 1211                         reg = <0x100f8830 0x30>;
 1212                         clocks = <&gcc USB30_0_MASTER_CLK>;
 1213                         clock-names = "ref";
 1214                         #phy-cells = <0>;
 1215 
 1216                         status = "disabled";
 1217                 };
 1218 
 1219                 usb3_0: usb3@100f8800 {
 1220                         compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
 1221                         #address-cells = <1>;
 1222                         #size-cells = <1>;
 1223                         reg = <0x100f8800 0x8000>;
 1224                         clocks = <&gcc USB30_0_MASTER_CLK>;
 1225                         clock-names = "core";
 1226 
 1227                         ranges;
 1228 
 1229                         resets = <&gcc USB30_0_MASTER_RESET>;
 1230                         reset-names = "master";
 1231 
 1232                         status = "disabled";
 1233 
 1234                         dwc3_0: dwc3@10000000 {
 1235                                 compatible = "snps,dwc3";
 1236                                 reg = <0x10000000 0xcd00>;
 1237                                 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 1238                                 phys = <&hs_phy_0>, <&ss_phy_0>;
 1239                                 phy-names = "usb2-phy", "usb3-phy";
 1240                                 dr_mode = "host";
 1241                                 snps,dis_u3_susphy_quirk;
 1242                         };
 1243                 };
 1244 
 1245                 hs_phy_1: phy@110f8800 {
 1246                         compatible = "qcom,ipq806x-usb-phy-hs";
 1247                         reg = <0x110f8800 0x30>;
 1248                         clocks = <&gcc USB30_1_UTMI_CLK>;
 1249                         clock-names = "ref";
 1250                         #phy-cells = <0>;
 1251 
 1252                         status = "disabled";
 1253                 };
 1254 
 1255                 ss_phy_1: phy@110f8830 {
 1256                         compatible = "qcom,ipq806x-usb-phy-ss";
 1257                         reg = <0x110f8830 0x30>;
 1258                         clocks = <&gcc USB30_1_MASTER_CLK>;
 1259                         clock-names = "ref";
 1260                         #phy-cells = <0>;
 1261 
 1262                         status = "disabled";
 1263                 };
 1264 
 1265                 usb3_1: usb3@110f8800 {
 1266                         compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
 1267                         #address-cells = <1>;
 1268                         #size-cells = <1>;
 1269                         reg = <0x110f8800 0x8000>;
 1270                         clocks = <&gcc USB30_1_MASTER_CLK>;
 1271                         clock-names = "core";
 1272 
 1273                         ranges;
 1274 
 1275                         resets = <&gcc USB30_1_MASTER_RESET>;
 1276                         reset-names = "master";
 1277 
 1278                         status = "disabled";
 1279 
 1280                         dwc3_1: dwc3@11000000 {
 1281                                 compatible = "snps,dwc3";
 1282                                 reg = <0x11000000 0xcd00>;
 1283                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 1284                                 phys = <&hs_phy_1>, <&ss_phy_1>;
 1285                                 phy-names = "usb2-phy", "usb3-phy";
 1286                                 dr_mode = "host";
 1287                                 snps,dis_u3_susphy_quirk;
 1288                         };
 1289                 };
 1290 
 1291                 vsdcc_fixed: vsdcc-regulator {
 1292                         compatible = "regulator-fixed";
 1293                         regulator-name = "SDCC Power";
 1294                         regulator-min-microvolt = <3300000>;
 1295                         regulator-max-microvolt = <3300000>;
 1296                         regulator-always-on;
 1297                 };
 1298 
 1299                 sdcc1bam: dma-controller@12402000 {
 1300                         compatible = "qcom,bam-v1.3.0";
 1301                         reg = <0x12402000 0x8000>;
 1302                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 1303                         clocks = <&gcc SDC1_H_CLK>;
 1304                         clock-names = "bam_clk";
 1305                         #dma-cells = <1>;
 1306                         qcom,ee = <0>;
 1307                 };
 1308 
 1309                 sdcc3bam: dma-controller@12182000 {
 1310                         compatible = "qcom,bam-v1.3.0";
 1311                         reg = <0x12182000 0x8000>;
 1312                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 1313                         clocks = <&gcc SDC3_H_CLK>;
 1314                         clock-names = "bam_clk";
 1315                         #dma-cells = <1>;
 1316                         qcom,ee = <0>;
 1317                 };
 1318 
 1319                 amba: amba {
 1320                         compatible = "simple-bus";
 1321                         #address-cells = <1>;
 1322                         #size-cells = <1>;
 1323                         ranges;
 1324 
 1325                         sdcc1: mmc@12400000 {
 1326                                 status = "disabled";
 1327                                 compatible = "arm,pl18x", "arm,primecell";
 1328                                 arm,primecell-periphid = <0x00051180>;
 1329                                 reg = <0x12400000 0x2000>;
 1330                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 1331                                 interrupt-names = "cmd_irq";
 1332                                 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
 1333                                 clock-names = "mclk", "apb_pclk";
 1334                                 bus-width = <8>;
 1335                                 max-frequency = <96000000>;
 1336                                 non-removable;
 1337                                 cap-sd-highspeed;
 1338                                 cap-mmc-highspeed;
 1339                                 mmc-ddr-1_8v;
 1340                                 vmmc-supply = <&vsdcc_fixed>;
 1341                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 1342                                 dma-names = "tx", "rx";
 1343                         };
 1344 
 1345                         sdcc3: mmc@12180000 {
 1346                                 compatible = "arm,pl18x", "arm,primecell";
 1347                                 arm,primecell-periphid = <0x00051180>;
 1348                                 status = "disabled";
 1349                                 reg = <0x12180000 0x2000>;
 1350                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 1351                                 interrupt-names = "cmd_irq";
 1352                                 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
 1353                                 clock-names = "mclk", "apb_pclk";
 1354                                 bus-width = <8>;
 1355                                 cap-sd-highspeed;
 1356                                 cap-mmc-highspeed;
 1357                                 max-frequency = <192000000>;
 1358                                 sd-uhs-sdr104;
 1359                                 sd-uhs-ddr50;
 1360                                 vqmmc-supply = <&vsdcc_fixed>;
 1361                                 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
 1362                                 dma-names = "tx", "rx";
 1363                         };
 1364                 };
 1365 
 1366                 sfpb_mutex: hwlock@1200600 {
 1367                         compatible = "qcom,sfpb-mutex";
 1368                         reg = <0x01200600 0x100>;
 1369 
 1370                         #hwlock-cells = <1>;
 1371                 };
 1372         };
 1373 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/qcom-ipq8064.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/qcom-ipq8064.dtsi
