Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/qcom-msm8660.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 3 4 #include <dt-bindings/interrupt-controller/irq.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/clock/qcom,gcc-msm8660.h> 7 #include <dt-bindings/soc/qcom,gsbi.h> 8 9 / { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 model = "Qualcomm MSM8660"; 13 compatible = "qcom,msm8660"; 14 interrupt-parent = <&intc>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu@0 { 21 compatible = "qcom,scorpion"; 22 enable-method = "qcom,gcc-msm8660"; 23 device_type = "cpu"; 24 reg = <0>; 25 next-level-cache = <&L2>; 26 }; 27 28 cpu@1 { 29 compatible = "qcom,scorpion"; 30 enable-method = "qcom,gcc-msm8660"; 31 device_type = "cpu"; 32 reg = <1>; 33 next-level-cache = <&L2>; 34 }; 35 36 L2: l2-cache { 37 compatible = "cache"; 38 cache-level = <2>; 39 }; 40 }; 41 42 memory { 43 device_type = "memory"; 44 reg = <0x0 0x0>; 45 }; 46 47 cpu-pmu { 48 compatible = "qcom,scorpion-mp-pmu"; 49 interrupts = <1 9 0x304>; 50 }; 51 52 clocks { 53 cxo_board { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <19200000>; 57 }; 58 59 pxo_board: pxo_board { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <27000000>; 63 }; 64 65 sleep_clk { 66 compatible = "fixed-clock"; 67 #clock-cells = <0>; 68 clock-frequency = <32768>; 69 }; 70 }; 71 72 /* 73 * These channels from the ADC are simply hardware monitors. 74 * That is why the ADC is referred to as "HKADC" - HouseKeeping 75 * ADC. 76 */ 77 iio-hwmon { 78 compatible = "iio-hwmon"; 79 io-channels = <&xoadc 0x00 0x01>, /* Battery */ 80 <&xoadc 0x00 0x02>, /* DC in (charger) */ 81 <&xoadc 0x00 0x04>, /* VPH the main system voltage */ 82 <&xoadc 0x00 0x0b>, /* Die temperature */ 83 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ 84 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ 85 <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */ 86 }; 87 88 soc: soc { 89 #address-cells = <1>; 90 #size-cells = <1>; 91 ranges; 92 compatible = "simple-bus"; 93 94 intc: interrupt-controller@2080000 { 95 compatible = "qcom,msm-8660-qgic"; 96 interrupt-controller; 97 #interrupt-cells = <3>; 98 reg = < 0x02080000 0x1000 >, 99 < 0x02081000 0x1000 >; 100 }; 101 102 timer@2000000 { 103 compatible = "qcom,scss-timer", "qcom,msm-timer"; 104 interrupts = <1 0 0x301>, 105 <1 1 0x301>, 106 <1 2 0x301>; 107 reg = <0x02000000 0x100>; 108 clock-frequency = <27000000>, 109 <32768>; 110 cpu-offset = <0x40000>; 111 }; 112 113 tlmm: pinctrl@800000 { 114 compatible = "qcom,msm8660-pinctrl"; 115 reg = <0x800000 0x4000>; 116 117 gpio-controller; 118 gpio-ranges = <&tlmm 0 0 173>; 119 #gpio-cells = <2>; 120 interrupts = <0 16 0x4>; 121 interrupt-controller; 122 #interrupt-cells = <2>; 123 124 }; 125 126 gcc: clock-controller@900000 { 127 compatible = "qcom,gcc-msm8660"; 128 #clock-cells = <1>; 129 #power-domain-cells = <1>; 130 #reset-cells = <1>; 131 reg = <0x900000 0x4000>; 132 }; 133 134 gsbi6: gsbi@16500000 { 135 compatible = "qcom,gsbi-v1.0.0"; 136 cell-index = <12>; 137 reg = <0x16500000 0x100>; 138 clocks = <&gcc GSBI6_H_CLK>; 139 clock-names = "iface"; 140 #address-cells = <1>; 141 #size-cells = <1>; 142 ranges; 143 status = "disabled"; 144 145 syscon-tcsr = <&tcsr>; 146 147 gsbi6_serial: serial@16540000 { 148 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 149 reg = <0x16540000 0x1000>, 150 <0x16500000 0x1000>; 151 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 152 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 153 clock-names = "core", "iface"; 154 status = "disabled"; 155 }; 156 157 gsbi6_i2c: i2c@16580000 { 158 compatible = "qcom,i2c-qup-v1.1.1"; 159 reg = <0x16580000 0x1000>; 160 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 161 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 162 clock-names = "core", "iface"; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 status = "disabled"; 166 }; 167 }; 168 169 gsbi7: gsbi@16600000 { 170 compatible = "qcom,gsbi-v1.0.0"; 171 cell-index = <12>; 172 reg = <0x16600000 0x100>; 173 clocks = <&gcc GSBI7_H_CLK>; 174 clock-names = "iface"; 175 #address-cells = <1>; 176 #size-cells = <1>; 177 ranges; 178 status = "disabled"; 179 180 syscon-tcsr = <&tcsr>; 181 182 gsbi7_serial: serial@16640000 { 183 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 184 reg = <0x16640000 0x1000>, 185 <0x16600000 0x1000>; 186 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 188 clock-names = "core", "iface"; 189 status = "disabled"; 190 }; 191 192 gsbi7_i2c: i2c@16680000 { 193 compatible = "qcom,i2c-qup-v1.1.1"; 194 reg = <0x16680000 0x1000>; 195 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; 197 clock-names = "core", "iface"; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 status = "disabled"; 201 }; 202 }; 203 204 gsbi8: gsbi@19800000 { 205 compatible = "qcom,gsbi-v1.0.0"; 206 cell-index = <12>; 207 reg = <0x19800000 0x100>; 208 clocks = <&gcc GSBI8_H_CLK>; 209 clock-names = "iface"; 210 #address-cells = <1>; 211 #size-cells = <1>; 212 ranges; 213 214 syscon-tcsr = <&tcsr>; 215 status = "disabled"; 216 217 gsbi8_i2c: i2c@19880000 { 218 compatible = "qcom,i2c-qup-v1.1.1"; 219 reg = <0x19880000 0x1000>; 220 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; 222 clock-names = "core", "iface"; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 status = "disabled"; 226 }; 227 }; 228 229 gsbi12: gsbi@19c00000 { 230 compatible = "qcom,gsbi-v1.0.0"; 231 cell-index = <12>; 232 reg = <0x19c00000 0x100>; 233 clocks = <&gcc GSBI12_H_CLK>; 234 clock-names = "iface"; 235 #address-cells = <1>; 236 #size-cells = <1>; 237 ranges; 238 239 syscon-tcsr = <&tcsr>; 240 241 gsbi12_serial: serial@19c40000 { 242 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 243 reg = <0x19c40000 0x1000>, 244 <0x19c00000 0x1000>; 245 interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; 247 clock-names = "core", "iface"; 248 status = "disabled"; 249 }; 250 251 gsbi12_i2c: i2c@19c80000 { 252 compatible = "qcom,i2c-qup-v1.1.1"; 253 reg = <0x19c80000 0x1000>; 254 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; 256 clock-names = "core", "iface"; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 status = "disabled"; 260 }; 261 }; 262 263 external-bus@1a100000 { 264 compatible = "qcom,msm8660-ebi2"; 265 #address-cells = <2>; 266 #size-cells = <1>; 267 ranges = <0 0x0 0x1a800000 0x00800000>, 268 <1 0x0 0x1b000000 0x00800000>, 269 <2 0x0 0x1b800000 0x00800000>, 270 <3 0x0 0x1d000000 0x08000000>, 271 <4 0x0 0x1c800000 0x00800000>, 272 <5 0x0 0x1c000000 0x00800000>; 273 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; 274 reg-names = "ebi2", "xmem"; 275 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; 276 clock-names = "ebi2x", "ebi2"; 277 status = "disabled"; 278 }; 279 280 qcom,ssbi@500000 { 281 compatible = "qcom,ssbi"; 282 reg = <0x500000 0x1000>; 283 qcom,controller-type = "pmic-arbiter"; 284 285 pm8058: pmic@0 { 286 compatible = "qcom,pm8058"; 287 interrupt-parent = <&tlmm>; 288 interrupts = <88 8>; 289 #interrupt-cells = <2>; 290 interrupt-controller; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 294 pm8058_gpio: gpio@150 { 295 compatible = "qcom,pm8058-gpio", 296 "qcom,ssbi-gpio"; 297 reg = <0x150>; 298 interrupt-controller; 299 #interrupt-cells = <2>; 300 gpio-controller; 301 gpio-ranges = <&pm8058_gpio 0 0 44>; 302 #gpio-cells = <2>; 303 304 }; 305 306 pm8058_mpps: mpps@50 { 307 compatible = "qcom,pm8058-mpp", 308 "qcom,ssbi-mpp"; 309 reg = <0x50>; 310 gpio-controller; 311 #gpio-cells = <2>; 312 gpio-ranges = <&pm8058_mpps 0 0 12>; 313 interrupt-controller; 314 #interrupt-cells = <2>; 315 }; 316 317 pwrkey@1c { 318 compatible = "qcom,pm8058-pwrkey"; 319 reg = <0x1c>; 320 interrupt-parent = <&pm8058>; 321 interrupts = <50 1>, <51 1>; 322 debounce = <15625>; 323 pull-up; 324 }; 325 326 keypad@148 { 327 compatible = "qcom,pm8058-keypad"; 328 reg = <0x148>; 329 interrupt-parent = <&pm8058>; 330 interrupts = <74 1>, <75 1>; 331 debounce = <15>; 332 scan-delay = <32>; 333 row-hold = <91500>; 334 }; 335 336 xoadc: xoadc@197 { 337 compatible = "qcom,pm8058-adc"; 338 reg = <0x197>; 339 interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>; 340 #address-cells = <2>; 341 #size-cells = <0>; 342 #io-channel-cells = <2>; 343 344 vcoin: adc-channel@0 { 345 reg = <0x00 0x00>; 346 }; 347 vbat: adc-channel@1 { 348 reg = <0x00 0x01>; 349 }; 350 dcin: adc-channel@2 { 351 reg = <0x00 0x02>; 352 }; 353 ichg: adc-channel@3 { 354 reg = <0x00 0x03>; 355 }; 356 vph_pwr: adc-channel@4 { 357 reg = <0x00 0x04>; 358 }; 359 usb_vbus: adc-channel@a { 360 reg = <0x00 0x0a>; 361 }; 362 die_temp: adc-channel@b { 363 reg = <0x00 0x0b>; 364 }; 365 ref_625mv: adc-channel@c { 366 reg = <0x00 0x0c>; 367 }; 368 ref_1250mv: adc-channel@d { 369 reg = <0x00 0x0d>; 370 }; 371 ref_325mv: adc-channel@e { 372 reg = <0x00 0x0e>; 373 }; 374 ref_muxoff: adc-channel@f { 375 reg = <0x00 0x0f>; 376 }; 377 }; 378 379 rtc@1e8 { 380 compatible = "qcom,pm8058-rtc"; 381 reg = <0x1e8>; 382 interrupt-parent = <&pm8058>; 383 interrupts = <39 1>; 384 allow-set-time; 385 }; 386 387 vibrator@4a { 388 compatible = "qcom,pm8058-vib"; 389 reg = <0x4a>; 390 }; 391 }; 392 }; 393 394 l2cc: clock-controller@2082000 { 395 compatible = "qcom,kpss-gcc", "syscon"; 396 reg = <0x02082000 0x1000>; 397 }; 398 399 rpm: rpm@104000 { 400 compatible = "qcom,rpm-msm8660"; 401 reg = <0x00104000 0x1000>; 402 qcom,ipc = <&l2cc 0x8 2>; 403 404 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 405 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 406 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 407 interrupt-names = "ack", "err", "wakeup"; 408 clocks = <&gcc RPM_MSG_RAM_H_CLK>; 409 clock-names = "ram"; 410 411 rpmcc: clock-controller { 412 compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; 413 #clock-cells = <1>; 414 clocks = <&pxo_board>; 415 clock-names = "pxo"; 416 }; 417 418 pm8901-regulators { 419 compatible = "qcom,rpm-pm8901-regulators"; 420 421 pm8901_l0: l0 {}; 422 pm8901_l1: l1 {}; 423 pm8901_l2: l2 {}; 424 pm8901_l3: l3 {}; 425 pm8901_l4: l4 {}; 426 pm8901_l5: l5 {}; 427 pm8901_l6: l6 {}; 428 429 /* S0 and S1 Handled as SAW regulators by SPM */ 430 pm8901_s2: s2 {}; 431 pm8901_s3: s3 {}; 432 pm8901_s4: s4 {}; 433 434 pm8901_lvs0: lvs0 {}; 435 pm8901_lvs1: lvs1 {}; 436 pm8901_lvs2: lvs2 {}; 437 pm8901_lvs3: lvs3 {}; 438 439 pm8901_mvs: mvs {}; 440 }; 441 442 pm8058-regulators { 443 compatible = "qcom,rpm-pm8058-regulators"; 444 445 pm8058_l0: l0 {}; 446 pm8058_l1: l1 {}; 447 pm8058_l2: l2 {}; 448 pm8058_l3: l3 {}; 449 pm8058_l4: l4 {}; 450 pm8058_l5: l5 {}; 451 pm8058_l6: l6 {}; 452 pm8058_l7: l7 {}; 453 pm8058_l8: l8 {}; 454 pm8058_l9: l9 {}; 455 pm8058_l10: l10 {}; 456 pm8058_l11: l11 {}; 457 pm8058_l12: l12 {}; 458 pm8058_l13: l13 {}; 459 pm8058_l14: l14 {}; 460 pm8058_l15: l15 {}; 461 pm8058_l16: l16 {}; 462 pm8058_l17: l17 {}; 463 pm8058_l18: l18 {}; 464 pm8058_l19: l19 {}; 465 pm8058_l20: l20 {}; 466 pm8058_l21: l21 {}; 467 pm8058_l22: l22 {}; 468 pm8058_l23: l23 {}; 469 pm8058_l24: l24 {}; 470 pm8058_l25: l25 {}; 471 472 pm8058_s0: s0 {}; 473 pm8058_s1: s1 {}; 474 pm8058_s2: s2 {}; 475 pm8058_s3: s3 {}; 476 pm8058_s4: s4 {}; 477 478 pm8058_lvs0: lvs0 {}; 479 pm8058_lvs1: lvs1 {}; 480 481 pm8058_ncp: ncp {}; 482 }; 483 }; 484 485 amba { 486 compatible = "simple-bus"; 487 #address-cells = <1>; 488 #size-cells = <1>; 489 ranges; 490 sdcc1: mmc@12400000 { 491 status = "disabled"; 492 compatible = "arm,pl18x", "arm,primecell"; 493 arm,primecell-periphid = <0x00051180>; 494 reg = <0x12400000 0x8000>; 495 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 496 interrupt-names = "cmd_irq"; 497 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 498 clock-names = "mclk", "apb_pclk"; 499 bus-width = <8>; 500 max-frequency = <48000000>; 501 non-removable; 502 cap-sd-highspeed; 503 cap-mmc-highspeed; 504 }; 505 506 sdcc2: mmc@12140000 { 507 status = "disabled"; 508 compatible = "arm,pl18x", "arm,primecell"; 509 arm,primecell-periphid = <0x00051180>; 510 reg = <0x12140000 0x8000>; 511 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 512 interrupt-names = "cmd_irq"; 513 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; 514 clock-names = "mclk", "apb_pclk"; 515 bus-width = <8>; 516 max-frequency = <48000000>; 517 cap-sd-highspeed; 518 cap-mmc-highspeed; 519 }; 520 521 sdcc3: mmc@12180000 { 522 compatible = "arm,pl18x", "arm,primecell"; 523 arm,primecell-periphid = <0x00051180>; 524 status = "disabled"; 525 reg = <0x12180000 0x8000>; 526 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 527 interrupt-names = "cmd_irq"; 528 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 529 clock-names = "mclk", "apb_pclk"; 530 bus-width = <4>; 531 cap-sd-highspeed; 532 cap-mmc-highspeed; 533 max-frequency = <48000000>; 534 no-1-8-v; 535 }; 536 537 sdcc4: mmc@121c0000 { 538 compatible = "arm,pl18x", "arm,primecell"; 539 arm,primecell-periphid = <0x00051180>; 540 status = "disabled"; 541 reg = <0x121c0000 0x8000>; 542 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 543 interrupt-names = "cmd_irq"; 544 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 545 clock-names = "mclk", "apb_pclk"; 546 bus-width = <4>; 547 max-frequency = <48000000>; 548 cap-sd-highspeed; 549 cap-mmc-highspeed; 550 }; 551 552 sdcc5: mmc@12200000 { 553 compatible = "arm,pl18x", "arm,primecell"; 554 arm,primecell-periphid = <0x00051180>; 555 status = "disabled"; 556 reg = <0x12200000 0x8000>; 557 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 558 interrupt-names = "cmd_irq"; 559 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; 560 clock-names = "mclk", "apb_pclk"; 561 bus-width = <4>; 562 cap-sd-highspeed; 563 cap-mmc-highspeed; 564 max-frequency = <48000000>; 565 }; 566 }; 567 568 tcsr: syscon@1a400000 { 569 compatible = "qcom,tcsr-msm8660", "syscon"; 570 reg = <0x1a400000 0x100>; 571 }; 572 }; 573 574 };
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