qcom-msm8974.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0
    2 /dts-v1/;
    3 
    4 #include <dt-bindings/interconnect/qcom,msm8974.h>
    5 #include <dt-bindings/interrupt-controller/arm-gic.h>
    6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
    7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
    8 #include <dt-bindings/clock/qcom,rpmcc.h>
    9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
   10 #include <dt-bindings/gpio/gpio.h>
   11 
   12 / {
   13         #address-cells = <1>;
   14         #size-cells = <1>;
   15         interrupt-parent = <&intc>;
   16 
   17         clocks {
   18                 xo_board: xo_board {
   19                         compatible = "fixed-clock";
   20                         #clock-cells = <0>;
   21                         clock-frequency = <19200000>;
   22                 };
   23 
   24                 sleep_clk: sleep_clk {
   25                         compatible = "fixed-clock";
   26                         #clock-cells = <0>;
   27                         clock-frequency = <32768>;
   28                 };
   29         };
   30 
   31         cpus {
   32                 #address-cells = <1>;
   33                 #size-cells = <0>;
   34                 interrupts = <GIC_PPI 9 0xf04>;
   35 
   36                 CPU0: cpu@0 {
   37                         compatible = "qcom,krait";
   38                         enable-method = "qcom,kpss-acc-v2";
   39                         device_type = "cpu";
   40                         reg = <0>;
   41                         next-level-cache = <&L2>;
   42                         qcom,acc = <&acc0>;
   43                         qcom,saw = <&saw0>;
   44                         cpu-idle-states = <&CPU_SPC>;
   45                 };
   46 
   47                 CPU1: cpu@1 {
   48                         compatible = "qcom,krait";
   49                         enable-method = "qcom,kpss-acc-v2";
   50                         device_type = "cpu";
   51                         reg = <1>;
   52                         next-level-cache = <&L2>;
   53                         qcom,acc = <&acc1>;
   54                         qcom,saw = <&saw1>;
   55                         cpu-idle-states = <&CPU_SPC>;
   56                 };
   57 
   58                 CPU2: cpu@2 {
   59                         compatible = "qcom,krait";
   60                         enable-method = "qcom,kpss-acc-v2";
   61                         device_type = "cpu";
   62                         reg = <2>;
   63                         next-level-cache = <&L2>;
   64                         qcom,acc = <&acc2>;
   65                         qcom,saw = <&saw2>;
   66                         cpu-idle-states = <&CPU_SPC>;
   67                 };
   68 
   69                 CPU3: cpu@3 {
   70                         compatible = "qcom,krait";
   71                         enable-method = "qcom,kpss-acc-v2";
   72                         device_type = "cpu";
   73                         reg = <3>;
   74                         next-level-cache = <&L2>;
   75                         qcom,acc = <&acc3>;
   76                         qcom,saw = <&saw3>;
   77                         cpu-idle-states = <&CPU_SPC>;
   78                 };
   79 
   80                 L2: l2-cache {
   81                         compatible = "cache";
   82                         cache-level = <2>;
   83                         qcom,saw = <&saw_l2>;
   84                 };
   85 
   86                 idle-states {
   87                         CPU_SPC: spc {
   88                                 compatible = "qcom,idle-state-spc",
   89                                                 "arm,idle-state";
   90                                 entry-latency-us = <150>;
   91                                 exit-latency-us = <200>;
   92                                 min-residency-us = <2000>;
   93                         };
   94                 };
   95         };
   96 
   97         firmware {
   98                 scm {
   99                         compatible = "qcom,scm-msm8974", "qcom,scm";
  100                         clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
  101                         clock-names = "core", "bus", "iface";
  102                 };
  103         };
  104 
  105         memory {
  106                 device_type = "memory";
  107                 reg = <0x0 0x0>;
  108         };
  109 
  110         pmu {
  111                 compatible = "qcom,krait-pmu";
  112                 interrupts = <GIC_PPI 7 0xf04>;
  113         };
  114 
  115         reserved-memory {
  116                 #address-cells = <1>;
  117                 #size-cells = <1>;
  118                 ranges;
  119 
  120                 mpss_region: mpss@8000000 {
  121                         reg = <0x08000000 0x5100000>;
  122                         no-map;
  123                 };
  124 
  125                 mba_region: mba@d100000 {
  126                         reg = <0x0d100000 0x100000>;
  127                         no-map;
  128                 };
  129 
  130                 wcnss_region: wcnss@d200000 {
  131                         reg = <0x0d200000 0xa00000>;
  132                         no-map;
  133                 };
  134 
  135                 adsp_region: adsp@dc00000 {
  136                         reg = <0x0dc00000 0x1900000>;
  137                         no-map;
  138                 };
  139 
  140                 venus_region: memory@f500000 {
  141                         reg = <0x0f500000 0x500000>;
  142                         no-map;
  143                 };
  144 
  145                 smem_region: smem@fa00000 {
  146                         reg = <0xfa00000 0x200000>;
  147                         no-map;
  148                 };
  149 
  150                 tz_region: memory@fc00000 {
  151                         reg = <0x0fc00000 0x160000>;
  152                         no-map;
  153                 };
  154 
  155                 rfsa_mem: memory@fd60000 {
  156                         reg = <0x0fd60000 0x20000>;
  157                         no-map;
  158                 };
  159 
  160                 rmtfs@fd80000 {
  161                         compatible = "qcom,rmtfs-mem";
  162                         reg = <0x0fd80000 0x180000>;
  163                         no-map;
  164 
  165                         qcom,client-id = <1>;
  166                 };
  167         };
  168 
  169         smem {
  170                 compatible = "qcom,smem";
  171 
  172                 memory-region = <&smem_region>;
  173                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
  174 
  175                 hwlocks = <&tcsr_mutex 3>;
  176         };
  177 
  178         smp2p-adsp {
  179                 compatible = "qcom,smp2p";
  180                 qcom,smem = <443>, <429>;
  181 
  182                 interrupt-parent = <&intc>;
  183                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
  184 
  185                 qcom,ipc = <&apcs 8 10>;
  186 
  187                 qcom,local-pid = <0>;
  188                 qcom,remote-pid = <2>;
  189 
  190                 adsp_smp2p_out: master-kernel {
  191                         qcom,entry-name = "master-kernel";
  192                         #qcom,smem-state-cells = <1>;
  193                 };
  194 
  195                 adsp_smp2p_in: slave-kernel {
  196                         qcom,entry-name = "slave-kernel";
  197 
  198                         interrupt-controller;
  199                         #interrupt-cells = <2>;
  200                 };
  201         };
  202 
  203         smp2p-modem {
  204                 compatible = "qcom,smp2p";
  205                 qcom,smem = <435>, <428>;
  206 
  207                 interrupt-parent = <&intc>;
  208                 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
  209 
  210                 qcom,ipc = <&apcs 8 14>;
  211 
  212                 qcom,local-pid = <0>;
  213                 qcom,remote-pid = <1>;
  214 
  215                 modem_smp2p_out: master-kernel {
  216                         qcom,entry-name = "master-kernel";
  217                         #qcom,smem-state-cells = <1>;
  218                 };
  219 
  220                 modem_smp2p_in: slave-kernel {
  221                         qcom,entry-name = "slave-kernel";
  222 
  223                         interrupt-controller;
  224                         #interrupt-cells = <2>;
  225                 };
  226         };
  227 
  228         smp2p-wcnss {
  229                 compatible = "qcom,smp2p";
  230                 qcom,smem = <451>, <431>;
  231 
  232                 interrupt-parent = <&intc>;
  233                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
  234 
  235                 qcom,ipc = <&apcs 8 18>;
  236 
  237                 qcom,local-pid = <0>;
  238                 qcom,remote-pid = <4>;
  239 
  240                 wcnss_smp2p_out: master-kernel {
  241                         qcom,entry-name = "master-kernel";
  242 
  243                         #qcom,smem-state-cells = <1>;
  244                 };
  245 
  246                 wcnss_smp2p_in: slave-kernel {
  247                         qcom,entry-name = "slave-kernel";
  248 
  249                         interrupt-controller;
  250                         #interrupt-cells = <2>;
  251                 };
  252         };
  253 
  254         smsm {
  255                 compatible = "qcom,smsm";
  256 
  257                 #address-cells = <1>;
  258                 #size-cells = <0>;
  259 
  260                 qcom,ipc-1 = <&apcs 8 13>;
  261                 qcom,ipc-2 = <&apcs 8 9>;
  262                 qcom,ipc-3 = <&apcs 8 19>;
  263 
  264                 apps_smsm: apps@0 {
  265                         reg = <0>;
  266 
  267                         #qcom,smem-state-cells = <1>;
  268                 };
  269 
  270                 modem_smsm: modem@1 {
  271                         reg = <1>;
  272                         interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
  273 
  274                         interrupt-controller;
  275                         #interrupt-cells = <2>;
  276                 };
  277 
  278                 adsp_smsm: adsp@2 {
  279                         reg = <2>;
  280                         interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
  281 
  282                         interrupt-controller;
  283                         #interrupt-cells = <2>;
  284                 };
  285 
  286                 wcnss_smsm: wcnss@7 {
  287                         reg = <7>;
  288                         interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
  289 
  290                         interrupt-controller;
  291                         #interrupt-cells = <2>;
  292                 };
  293         };
  294 
  295         smd {
  296                 compatible = "qcom,smd";
  297 
  298                 rpm {
  299                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
  300                         qcom,ipc = <&apcs 8 0>;
  301                         qcom,smd-edge = <15>;
  302 
  303                         rpm_requests: rpm_requests {
  304                                 compatible = "qcom,rpm-msm8974";
  305                                 qcom,smd-channels = "rpm_requests";
  306 
  307                                 rpmcc: clock-controller {
  308                                         compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
  309                                         #clock-cells = <1>;
  310                                 };
  311                         };
  312                 };
  313         };
  314 
  315         soc: soc {
  316                 #address-cells = <1>;
  317                 #size-cells = <1>;
  318                 ranges;
  319                 compatible = "simple-bus";
  320 
  321                 intc: interrupt-controller@f9000000 {
  322                         compatible = "qcom,msm-qgic2";
  323                         interrupt-controller;
  324                         #interrupt-cells = <3>;
  325                         reg = <0xf9000000 0x1000>,
  326                               <0xf9002000 0x1000>;
  327                 };
  328 
  329                 apcs: syscon@f9011000 {
  330                         compatible = "syscon";
  331                         reg = <0xf9011000 0x1000>;
  332                 };
  333 
  334                 timer@f9020000 {
  335                         #address-cells = <1>;
  336                         #size-cells = <1>;
  337                         ranges;
  338                         compatible = "arm,armv7-timer-mem";
  339                         reg = <0xf9020000 0x1000>;
  340                         clock-frequency = <19200000>;
  341 
  342                         frame@f9021000 {
  343                                 frame-number = <0>;
  344                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  345                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  346                                 reg = <0xf9021000 0x1000>,
  347                                       <0xf9022000 0x1000>;
  348                         };
  349 
  350                         frame@f9023000 {
  351                                 frame-number = <1>;
  352                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  353                                 reg = <0xf9023000 0x1000>;
  354                                 status = "disabled";
  355                         };
  356 
  357                         frame@f9024000 {
  358                                 frame-number = <2>;
  359                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  360                                 reg = <0xf9024000 0x1000>;
  361                                 status = "disabled";
  362                         };
  363 
  364                         frame@f9025000 {
  365                                 frame-number = <3>;
  366                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  367                                 reg = <0xf9025000 0x1000>;
  368                                 status = "disabled";
  369                         };
  370 
  371                         frame@f9026000 {
  372                                 frame-number = <4>;
  373                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  374                                 reg = <0xf9026000 0x1000>;
  375                                 status = "disabled";
  376                         };
  377 
  378                         frame@f9027000 {
  379                                 frame-number = <5>;
  380                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  381                                 reg = <0xf9027000 0x1000>;
  382                                 status = "disabled";
  383                         };
  384 
  385                         frame@f9028000 {
  386                                 frame-number = <6>;
  387                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  388                                 reg = <0xf9028000 0x1000>;
  389                                 status = "disabled";
  390                         };
  391                 };
  392 
  393                 saw0: power-controller@f9089000 {
  394                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
  395                         reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
  396                 };
  397 
  398                 saw1: power-controller@f9099000 {
  399                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
  400                         reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
  401                 };
  402 
  403                 saw2: power-controller@f90a9000 {
  404                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
  405                         reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
  406                 };
  407 
  408                 saw3: power-controller@f90b9000 {
  409                         compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
  410                         reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
  411                 };
  412 
  413                 saw_l2: power-controller@f9012000 {
  414                         compatible = "qcom,saw2";
  415                         reg = <0xf9012000 0x1000>;
  416                         regulator;
  417                 };
  418 
  419                 acc0: clock-controller@f9088000 {
  420                         compatible = "qcom,kpss-acc-v2";
  421                         reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
  422                 };
  423 
  424                 acc1: clock-controller@f9098000 {
  425                         compatible = "qcom,kpss-acc-v2";
  426                         reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
  427                 };
  428 
  429                 acc2: clock-controller@f90a8000 {
  430                         compatible = "qcom,kpss-acc-v2";
  431                         reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
  432                 };
  433 
  434                 acc3: clock-controller@f90b8000 {
  435                         compatible = "qcom,kpss-acc-v2";
  436                         reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
  437                 };
  438 
  439                 sdhc_1: mmc@f9824900 {
  440                         compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
  441                         reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
  442                         reg-names = "hc_mem", "core_mem";
  443                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
  444                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
  445                         interrupt-names = "hc_irq", "pwr_irq";
  446                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
  447                                  <&gcc GCC_SDCC1_AHB_CLK>,
  448                                  <&xo_board>;
  449                         clock-names = "core", "iface", "xo";
  450                         bus-width = <8>;
  451                         non-removable;
  452 
  453                         status = "disabled";
  454                 };
  455 
  456                 sdhc_3: mmc@f9864900 {
  457                         compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
  458                         reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
  459                         reg-names = "hc_mem", "core_mem";
  460                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
  461                                      <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
  462                         interrupt-names = "hc_irq", "pwr_irq";
  463                         clocks = <&gcc GCC_SDCC3_APPS_CLK>,
  464                                  <&gcc GCC_SDCC3_AHB_CLK>,
  465                                  <&xo_board>;
  466                         clock-names = "core", "iface", "xo";
  467                         bus-width = <4>;
  468 
  469                         #address-cells = <1>;
  470                         #size-cells = <0>;
  471 
  472                         status = "disabled";
  473                 };
  474 
  475                 sdhc_2: mmc@f98a4900 {
  476                         compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
  477                         reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
  478                         reg-names = "hc_mem", "core_mem";
  479                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
  480                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
  481                         interrupt-names = "hc_irq", "pwr_irq";
  482                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
  483                                  <&gcc GCC_SDCC2_AHB_CLK>,
  484                                  <&xo_board>;
  485                         clock-names = "core", "iface", "xo";
  486                         bus-width = <4>;
  487 
  488                         #address-cells = <1>;
  489                         #size-cells = <0>;
  490 
  491                         status = "disabled";
  492                 };
  493 
  494                 blsp1_uart1: serial@f991d000 {
  495                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  496                         reg = <0xf991d000 0x1000>;
  497                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
  498                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
  499                         clock-names = "core", "iface";
  500                         status = "disabled";
  501                 };
  502 
  503                 blsp1_uart2: serial@f991e000 {
  504                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  505                         reg = <0xf991e000 0x1000>;
  506                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  507                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
  508                         clock-names = "core", "iface";
  509                         pinctrl-names = "default";
  510                         pinctrl-0 = <&blsp1_uart2_default>;
  511                         status = "disabled";
  512                 };
  513 
  514                 blsp1_i2c1: i2c@f9923000 {
  515                         status = "disabled";
  516                         compatible = "qcom,i2c-qup-v2.1.1";
  517                         reg = <0xf9923000 0x1000>;
  518                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
  519                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
  520                         clock-names = "core", "iface";
  521                         pinctrl-names = "default", "sleep";
  522                         pinctrl-0 = <&blsp1_i2c1_default>;
  523                         pinctrl-1 = <&blsp1_i2c1_sleep>;
  524                         #address-cells = <1>;
  525                         #size-cells = <0>;
  526                 };
  527 
  528                 blsp1_i2c2: i2c@f9924000 {
  529                         status = "disabled";
  530                         compatible = "qcom,i2c-qup-v2.1.1";
  531                         reg = <0xf9924000 0x1000>;
  532                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  533                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
  534                         clock-names = "core", "iface";
  535                         pinctrl-names = "default", "sleep";
  536                         pinctrl-0 = <&blsp1_i2c2_default>;
  537                         pinctrl-1 = <&blsp1_i2c2_sleep>;
  538                         #address-cells = <1>;
  539                         #size-cells = <0>;
  540                 };
  541 
  542                 blsp1_i2c3: i2c@f9925000 {
  543                         status = "disabled";
  544                         compatible = "qcom,i2c-qup-v2.1.1";
  545                         reg = <0xf9925000 0x1000>;
  546                         interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
  547                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
  548                         clock-names = "core", "iface";
  549                         pinctrl-names = "default", "sleep";
  550                         pinctrl-0 = <&blsp1_i2c3_default>;
  551                         pinctrl-1 = <&blsp1_i2c3_sleep>;
  552                         #address-cells = <1>;
  553                         #size-cells = <0>;
  554                 };
  555 
  556                 blsp1_i2c6: i2c@f9928000 {
  557                         status = "disabled";
  558                         compatible = "qcom,i2c-qup-v2.1.1";
  559                         reg = <0xf9928000 0x1000>;
  560                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
  561                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
  562                         clock-names = "core", "iface";
  563                         pinctrl-names = "default", "sleep";
  564                         pinctrl-0 = <&blsp1_i2c6_default>;
  565                         pinctrl-1 = <&blsp1_i2c6_sleep>;
  566                         #address-cells = <1>;
  567                         #size-cells = <0>;
  568                 };
  569 
  570                 blsp2_dma: dma-controller@f9944000 {
  571                         compatible = "qcom,bam-v1.4.0";
  572                         reg = <0xf9944000 0x19000>;
  573                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
  574                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
  575                         clock-names = "bam_clk";
  576                         #dma-cells = <1>;
  577                         qcom,ee = <0>;
  578                 };
  579 
  580                 blsp2_uart1: serial@f995d000 {
  581                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  582                         reg = <0xf995d000 0x1000>;
  583                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  584                         clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
  585                         clock-names = "core", "iface";
  586                         pinctrl-names = "default", "sleep";
  587                         pinctrl-0 = <&blsp2_uart1_default>;
  588                         pinctrl-1 = <&blsp2_uart1_sleep>;
  589                         status = "disabled";
  590                 };
  591 
  592                 blsp2_uart2: serial@f995e000 {
  593                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  594                         reg = <0xf995e000 0x1000>;
  595                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
  596                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
  597                         clock-names = "core", "iface";
  598                         status = "disabled";
  599                 };
  600 
  601                 blsp2_uart4: serial@f9960000 {
  602                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  603                         reg = <0xf9960000 0x1000>;
  604                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
  605                         clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
  606                         clock-names = "core", "iface";
  607                         pinctrl-names = "default";
  608                         pinctrl-0 = <&blsp2_uart4_default>;
  609                         status = "disabled";
  610                 };
  611 
  612                 blsp2_i2c2: i2c@f9964000 {
  613                         status = "disabled";
  614                         compatible = "qcom,i2c-qup-v2.1.1";
  615                         reg = <0xf9964000 0x1000>;
  616                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
  617                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
  618                         clock-names = "core", "iface";
  619                         pinctrl-names = "default", "sleep";
  620                         pinctrl-0 = <&blsp2_i2c2_default>;
  621                         pinctrl-1 = <&blsp2_i2c2_sleep>;
  622                         #address-cells = <1>;
  623                         #size-cells = <0>;
  624                 };
  625 
  626                 blsp2_i2c5: i2c@f9967000 {
  627                         status = "disabled";
  628                         compatible = "qcom,i2c-qup-v2.1.1";
  629                         reg = <0xf9967000 0x1000>;
  630                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
  631                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
  632                         clock-names = "core", "iface";
  633                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
  634                         dma-names = "tx", "rx";
  635                         pinctrl-names = "default", "sleep";
  636                         pinctrl-0 = <&blsp2_i2c5_default>;
  637                         pinctrl-1 = <&blsp2_i2c5_sleep>;
  638                         #address-cells = <1>;
  639                         #size-cells = <0>;
  640                 };
  641 
  642                 blsp2_i2c6: i2c@f9968000 {
  643                         status = "disabled";
  644                         compatible = "qcom,i2c-qup-v2.1.1";
  645                         reg = <0xf9968000 0x1000>;
  646                         interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
  647                         clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
  648                         clock-names = "core", "iface";
  649                         pinctrl-names = "default", "sleep";
  650                         pinctrl-0 = <&blsp2_i2c6_default>;
  651                         pinctrl-1 = <&blsp2_i2c6_sleep>;
  652                         #address-cells = <1>;
  653                         #size-cells = <0>;
  654                 };
  655 
  656                 otg: usb@f9a55000 {
  657                         compatible = "qcom,ci-hdrc";
  658                         reg = <0xf9a55000 0x200>,
  659                               <0xf9a55200 0x200>;
  660                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
  661                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
  662                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
  663                         clock-names = "iface", "core";
  664                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
  665                         assigned-clock-rates = <75000000>;
  666                         resets = <&gcc GCC_USB_HS_BCR>;
  667                         reset-names = "core";
  668                         phy_type = "ulpi";
  669                         dr_mode = "otg";
  670                         ahb-burst-config = <0>;
  671                         phy-names = "usb-phy";
  672                         status = "disabled";
  673                         #reset-cells = <1>;
  674 
  675                         ulpi {
  676                                 usb_hs1_phy: phy@a {
  677                                         compatible = "qcom,usb-hs-phy-msm8974",
  678                                                      "qcom,usb-hs-phy";
  679                                         #phy-cells = <0>;
  680                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
  681                                         clock-names = "ref", "sleep";
  682                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
  683                                         reset-names = "phy", "por";
  684                                         status = "disabled";
  685                                 };
  686 
  687                                 usb_hs2_phy: phy@b {
  688                                         compatible = "qcom,usb-hs-phy-msm8974",
  689                                                      "qcom,usb-hs-phy";
  690                                         #phy-cells = <0>;
  691                                         clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
  692                                         clock-names = "ref", "sleep";
  693                                         resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
  694                                         reset-names = "phy", "por";
  695                                         status = "disabled";
  696                                 };
  697                         };
  698                 };
  699 
  700                 rng@f9bff000 {
  701                         compatible = "qcom,prng";
  702                         reg = <0xf9bff000 0x200>;
  703                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
  704                         clock-names = "core";
  705                 };
  706 
  707                 pronto: remoteproc@fb21b000 {
  708                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
  709                         reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
  710                         reg-names = "ccu", "dxe", "pmu";
  711 
  712                         memory-region = <&wcnss_region>;
  713 
  714                         interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
  715                                               <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
  716                                               <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
  717                                               <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
  718                                               <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
  719                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
  720 
  721                         qcom,smem-states = <&wcnss_smp2p_out 0>;
  722                         qcom,smem-state-names = "stop";
  723 
  724                         status = "disabled";
  725 
  726                         iris {
  727                                 compatible = "qcom,wcn3680";
  728 
  729                                 clocks = <&rpmcc RPM_SMD_CXO_A2>;
  730                                 clock-names = "xo";
  731                         };
  732 
  733                         smd-edge {
  734                                 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
  735 
  736                                 qcom,ipc = <&apcs 8 17>;
  737                                 qcom,smd-edge = <6>;
  738 
  739                                 wcnss {
  740                                         compatible = "qcom,wcnss";
  741                                         qcom,smd-channels = "WCNSS_CTRL";
  742                                         status = "disabled";
  743 
  744                                         qcom,mmio = <&pronto>;
  745 
  746                                         bt {
  747                                                 compatible = "qcom,wcnss-bt";
  748                                         };
  749 
  750                                         wifi {
  751                                                 compatible = "qcom,wcnss-wlan";
  752 
  753                                                 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
  754                                                              <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
  755                                                 interrupt-names = "tx", "rx";
  756 
  757                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
  758                                                 qcom,smem-state-names = "tx-enable",
  759                                                                         "tx-rings-empty";
  760                                         };
  761                                 };
  762                         };
  763                 };
  764 
  765                 etf@fc307000 {
  766                         compatible = "arm,coresight-tmc", "arm,primecell";
  767                         reg = <0xfc307000 0x1000>;
  768 
  769                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
  770                         clock-names = "apb_pclk", "atclk";
  771 
  772                         out-ports {
  773                                 port {
  774                                         etf_out: endpoint {
  775                                                 remote-endpoint = <&replicator_in>;
  776                                         };
  777                                 };
  778                         };
  779 
  780                         in-ports {
  781                                 port {
  782                                         etf_in: endpoint {
  783                                                 remote-endpoint = <&merger_out>;
  784                                         };
  785                                 };
  786                         };
  787                 };
  788 
  789                 tpiu@fc318000 {
  790                         compatible = "arm,coresight-tpiu", "arm,primecell";
  791                         reg = <0xfc318000 0x1000>;
  792 
  793                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
  794                         clock-names = "apb_pclk", "atclk";
  795 
  796                         in-ports {
  797                                 port {
  798                                         tpiu_in: endpoint {
  799                                                 remote-endpoint = <&replicator_out1>;
  800                                         };
  801                                  };
  802                         };
  803                 };
  804 
  805                 funnel@fc31a000 {
  806                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
  807                         reg = <0xfc31a000 0x1000>;
  808 
  809                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
  810                         clock-names = "apb_pclk", "atclk";
  811 
  812                         in-ports {
  813                                 #address-cells = <1>;
  814                                 #size-cells = <0>;
  815 
  816                                 /*
  817                                  * Not described input ports:
  818                                  * 0 - not-connected
  819                                  * 1 - connected trought funnel to Multimedia CPU
  820                                  * 2 - connected to Wireless CPU
  821                                  * 3 - not-connected
  822                                  * 4 - not-connected
  823                                  * 6 - not-connected
  824                                  * 7 - connected to STM
  825                                  */
  826                                 port@5 {
  827                                         reg = <5>;
  828                                         funnel1_in5: endpoint {
  829                                                 remote-endpoint = <&kpss_out>;
  830                                         };
  831                                 };
  832                         };
  833 
  834                         out-ports {
  835                                 port {
  836                                         funnel1_out: endpoint {
  837                                                 remote-endpoint = <&merger_in1>;
  838                                         };
  839                                 };
  840                         };
  841                 };
  842 
  843                 funnel@fc31b000 {
  844                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
  845                         reg = <0xfc31b000 0x1000>;
  846 
  847                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
  848                         clock-names = "apb_pclk", "atclk";
  849 
  850                         in-ports {
  851                                 #address-cells = <1>;
  852                                 #size-cells = <0>;
  853 
  854                                 /*
  855                                  * Not described input ports:
  856                                  * 0 - connected trought funnel to Audio, Modem and
  857                                  *     Resource and Power Manager CPU's
  858                                  * 2...7 - not-connected
  859                                  */
  860                                 port@1 {
  861                                         reg = <1>;
  862                                         merger_in1: endpoint {
  863                                                 remote-endpoint = <&funnel1_out>;
  864                                         };
  865                                 };
  866                         };
  867 
  868                         out-ports {
  869                                 port {
  870                                         merger_out: endpoint {
  871                                                 remote-endpoint = <&etf_in>;
  872                                         };
  873                                 };
  874                         };
  875                 };
  876 
  877                 replicator@fc31c000 {
  878                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
  879                         reg = <0xfc31c000 0x1000>;
  880 
  881                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
  882                         clock-names = "apb_pclk", "atclk";
  883 
  884                         out-ports {
  885                                 #address-cells = <1>;
  886                                 #size-cells = <0>;
  887 
  888                                 port@0 {
  889                                         reg = <0>;
  890                                         replicator_out0: endpoint {
  891                                                 remote-endpoint = <&etr_in>;
  892                                         };
  893                                 };
  894                                 port@1 {
  895                                         reg = <1>;
  896                                         replicator_out1: endpoint {
  897                                                 remote-endpoint = <&tpiu_in>;
  898                                         };
  899                                 };
  900                         };
  901 
  902                         in-ports {
  903                                 port {
  904                                         replicator_in: endpoint {
  905                                                 remote-endpoint = <&etf_out>;
  906                                         };
  907                                 };
  908                         };
  909                 };
  910 
  911                 etr@fc322000 {
  912                         compatible = "arm,coresight-tmc", "arm,primecell";
  913                         reg = <0xfc322000 0x1000>;
  914 
  915                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
  916                         clock-names = "apb_pclk", "atclk";
  917 
  918                         in-ports {
  919                                 port {
  920                                         etr_in: endpoint {
  921                                                 remote-endpoint = <&replicator_out0>;
  922                                         };
  923                                 };
  924                         };
  925                 };
  926 
  927                 etm@fc33c000 {
  928                         compatible = "arm,coresight-etm4x", "arm,primecell";
  929                         reg = <0xfc33c000 0x1000>;
  930 
  931                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
  932                         clock-names = "apb_pclk", "atclk";
  933 
  934                         cpu = <&CPU0>;
  935 
  936                         out-ports {
  937                                 port {
  938                                         etm0_out: endpoint {
  939                                                 remote-endpoint = <&kpss_in0>;
  940                                         };
  941                                 };
  942                         };
  943                 };
  944 
  945                 etm@fc33d000 {
  946                         compatible = "arm,coresight-etm4x", "arm,primecell";
  947                         reg = <0xfc33d000 0x1000>;
  948 
  949                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
  950                         clock-names = "apb_pclk", "atclk";
  951 
  952                         cpu = <&CPU1>;
  953 
  954                         out-ports {
  955                                 port {
  956                                         etm1_out: endpoint {
  957                                                 remote-endpoint = <&kpss_in1>;
  958                                         };
  959                                 };
  960                         };
  961                 };
  962 
  963                 etm@fc33e000 {
  964                         compatible = "arm,coresight-etm4x", "arm,primecell";
  965                         reg = <0xfc33e000 0x1000>;
  966 
  967                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
  968                         clock-names = "apb_pclk", "atclk";
  969 
  970                         cpu = <&CPU2>;
  971 
  972                         out-ports {
  973                                 port {
  974                                         etm2_out: endpoint {
  975                                                 remote-endpoint = <&kpss_in2>;
  976                                         };
  977                                 };
  978                         };
  979                 };
  980 
  981                 etm@fc33f000 {
  982                         compatible = "arm,coresight-etm4x", "arm,primecell";
  983                         reg = <0xfc33f000 0x1000>;
  984 
  985                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
  986                         clock-names = "apb_pclk", "atclk";
  987 
  988                         cpu = <&CPU3>;
  989 
  990                         out-ports {
  991                                 port {
  992                                         etm3_out: endpoint {
  993                                                 remote-endpoint = <&kpss_in3>;
  994                                         };
  995                                 };
  996                         };
  997                 };
  998 
  999                 /* KPSS funnel, only 4 inputs are used */
 1000                 funnel@fc345000 {
 1001                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 1002                         reg = <0xfc345000 0x1000>;
 1003 
 1004                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1005                         clock-names = "apb_pclk", "atclk";
 1006 
 1007                         in-ports {
 1008                                 #address-cells = <1>;
 1009                                 #size-cells = <0>;
 1010 
 1011                                 port@0 {
 1012                                         reg = <0>;
 1013                                         kpss_in0: endpoint {
 1014                                                 remote-endpoint = <&etm0_out>;
 1015                                         };
 1016                                 };
 1017                                 port@1 {
 1018                                         reg = <1>;
 1019                                         kpss_in1: endpoint {
 1020                                                 remote-endpoint = <&etm1_out>;
 1021                                         };
 1022                                 };
 1023                                 port@2 {
 1024                                         reg = <2>;
 1025                                         kpss_in2: endpoint {
 1026                                                 remote-endpoint = <&etm2_out>;
 1027                                         };
 1028                                 };
 1029                                 port@3 {
 1030                                         reg = <3>;
 1031                                         kpss_in3: endpoint {
 1032                                                 remote-endpoint = <&etm3_out>;
 1033                                         };
 1034                                 };
 1035                         };
 1036 
 1037                         out-ports {
 1038                                 port {
 1039                                         kpss_out: endpoint {
 1040                                                 remote-endpoint = <&funnel1_in5>;
 1041                                         };
 1042                                 };
 1043                         };
 1044                 };
 1045 
 1046                 gcc: clock-controller@fc400000 {
 1047                         compatible = "qcom,gcc-msm8974";
 1048                         #clock-cells = <1>;
 1049                         #reset-cells = <1>;
 1050                         #power-domain-cells = <1>;
 1051                         reg = <0xfc400000 0x4000>;
 1052                 };
 1053 
 1054                 rpm_msg_ram: memory@fc428000 {
 1055                         compatible = "qcom,rpm-msg-ram";
 1056                         reg = <0xfc428000 0x4000>;
 1057                 };
 1058 
 1059                 bimc: interconnect@fc380000 {
 1060                         reg = <0xfc380000 0x6a000>;
 1061                         compatible = "qcom,msm8974-bimc";
 1062                         #interconnect-cells = <1>;
 1063                         clock-names = "bus", "bus_a";
 1064                         clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
 1065                                  <&rpmcc RPM_SMD_BIMC_A_CLK>;
 1066                 };
 1067 
 1068                 snoc: interconnect@fc460000 {
 1069                         reg = <0xfc460000 0x4000>;
 1070                         compatible = "qcom,msm8974-snoc";
 1071                         #interconnect-cells = <1>;
 1072                         clock-names = "bus", "bus_a";
 1073                         clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
 1074                                  <&rpmcc RPM_SMD_SNOC_A_CLK>;
 1075                 };
 1076 
 1077                 pnoc: interconnect@fc468000 {
 1078                         reg = <0xfc468000 0x4000>;
 1079                         compatible = "qcom,msm8974-pnoc";
 1080                         #interconnect-cells = <1>;
 1081                         clock-names = "bus", "bus_a";
 1082                         clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
 1083                                  <&rpmcc RPM_SMD_PNOC_A_CLK>;
 1084                 };
 1085 
 1086                 ocmemnoc: interconnect@fc470000 {
 1087                         reg = <0xfc470000 0x4000>;
 1088                         compatible = "qcom,msm8974-ocmemnoc";
 1089                         #interconnect-cells = <1>;
 1090                         clock-names = "bus", "bus_a";
 1091                         clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
 1092                                  <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
 1093                 };
 1094 
 1095                 mmssnoc: interconnect@fc478000 {
 1096                         reg = <0xfc478000 0x4000>;
 1097                         compatible = "qcom,msm8974-mmssnoc";
 1098                         #interconnect-cells = <1>;
 1099                         clock-names = "bus", "bus_a";
 1100                         clocks = <&mmcc MMSS_S0_AXI_CLK>,
 1101                                  <&mmcc MMSS_S0_AXI_CLK>;
 1102                 };
 1103 
 1104                 cnoc: interconnect@fc480000 {
 1105                         reg = <0xfc480000 0x4000>;
 1106                         compatible = "qcom,msm8974-cnoc";
 1107                         #interconnect-cells = <1>;
 1108                         clock-names = "bus", "bus_a";
 1109                         clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
 1110                                  <&rpmcc RPM_SMD_CNOC_A_CLK>;
 1111                 };
 1112 
 1113                 tsens: thermal-sensor@fc4a9000 {
 1114                         compatible = "qcom,msm8974-tsens";
 1115                         reg = <0xfc4a9000 0x1000>, /* TM */
 1116                               <0xfc4a8000 0x1000>; /* SROT */
 1117                         nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 1118                         nvmem-cell-names = "calib", "calib_backup";
 1119                         #qcom,sensors = <11>;
 1120                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 1121                         interrupt-names = "uplow";
 1122                         #thermal-sensor-cells = <1>;
 1123                 };
 1124 
 1125                 restart@fc4ab000 {
 1126                         compatible = "qcom,pshold";
 1127                         reg = <0xfc4ab000 0x4>;
 1128                 };
 1129 
 1130                 qfprom: qfprom@fc4bc000 {
 1131                         compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
 1132                         reg = <0xfc4bc000 0x1000>;
 1133                         #address-cells = <1>;
 1134                         #size-cells = <1>;
 1135                         tsens_calib: calib@d0 {
 1136                                 reg = <0xd0 0x18>;
 1137                         };
 1138                         tsens_backup: backup@440 {
 1139                                 reg = <0x440 0x10>;
 1140                         };
 1141                 };
 1142 
 1143                 spmi_bus: spmi@fc4cf000 {
 1144                         compatible = "qcom,spmi-pmic-arb";
 1145                         reg-names = "core", "intr", "cnfg";
 1146                         reg = <0xfc4cf000 0x1000>,
 1147                               <0xfc4cb000 0x1000>,
 1148                               <0xfc4ca000 0x1000>;
 1149                         interrupt-names = "periph_irq";
 1150                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 1151                         qcom,ee = <0>;
 1152                         qcom,channel = <0>;
 1153                         #address-cells = <2>;
 1154                         #size-cells = <0>;
 1155                         interrupt-controller;
 1156                         #interrupt-cells = <4>;
 1157                 };
 1158 
 1159                 bam_dmux_dma: dma-controller@fc834000 {
 1160                         compatible = "qcom,bam-v1.4.0";
 1161                         reg = <0xfc834000 0x7000>;
 1162                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 1163                         #dma-cells = <1>;
 1164                         qcom,ee = <0>;
 1165 
 1166                         num-channels = <6>;
 1167                         qcom,num-ees = <1>;
 1168                         qcom,powered-remotely;
 1169                 };
 1170 
 1171                 remoteproc_mss: remoteproc@fc880000 {
 1172                         compatible = "qcom,msm8974-mss-pil";
 1173                         reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
 1174                         reg-names = "qdsp6", "rmb";
 1175 
 1176                         interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
 1177                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 1178                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 1179                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 1180                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 1181                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 1182 
 1183                         clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
 1184                                  <&gcc GCC_MSS_CFG_AHB_CLK>,
 1185                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
 1186                                  <&xo_board>;
 1187                         clock-names = "iface", "bus", "mem", "xo";
 1188 
 1189                         resets = <&gcc GCC_MSS_RESTART>;
 1190                         reset-names = "mss_restart";
 1191 
 1192                         qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
 1193 
 1194                         qcom,smem-states = <&modem_smp2p_out 0>;
 1195                         qcom,smem-state-names = "stop";
 1196 
 1197                         status = "disabled";
 1198 
 1199                         mba {
 1200                                 memory-region = <&mba_region>;
 1201                         };
 1202 
 1203                         mpss {
 1204                                 memory-region = <&mpss_region>;
 1205                         };
 1206 
 1207                         bam_dmux: bam-dmux {
 1208                                 compatible = "qcom,bam-dmux";
 1209 
 1210                                 interrupt-parent = <&modem_smsm>;
 1211                                 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
 1212                                 interrupt-names = "pc", "pc-ack";
 1213 
 1214                                 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
 1215                                 qcom,smem-state-names = "pc", "pc-ack";
 1216 
 1217                                 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
 1218                                 dma-names = "tx", "rx";
 1219                         };
 1220 
 1221                         smd-edge {
 1222                                 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
 1223 
 1224                                 qcom,ipc = <&apcs 8 12>;
 1225                                 qcom,smd-edge = <0>;
 1226 
 1227                                 label = "modem";
 1228                         };
 1229                 };
 1230 
 1231                 tcsr_mutex_block: syscon@fd484000 {
 1232                         compatible = "syscon";
 1233                         reg = <0xfd484000 0x2000>;
 1234                 };
 1235 
 1236                 tcsr: syscon@fd4a0000 {
 1237                         compatible = "syscon";
 1238                         reg = <0xfd4a0000 0x10000>;
 1239                 };
 1240 
 1241                 tlmm: pinctrl@fd510000 {
 1242                         compatible = "qcom,msm8974-pinctrl";
 1243                         reg = <0xfd510000 0x4000>;
 1244                         gpio-controller;
 1245                         gpio-ranges = <&tlmm 0 0 146>;
 1246                         #gpio-cells = <2>;
 1247                         interrupt-controller;
 1248                         #interrupt-cells = <2>;
 1249                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 1250 
 1251                         sdc1_off: sdc1-off {
 1252                                 clk {
 1253                                         pins = "sdc1_clk";
 1254                                         bias-disable;
 1255                                         drive-strength = <2>;
 1256                                 };
 1257 
 1258                                 cmd {
 1259                                         pins = "sdc1_cmd";
 1260                                         bias-pull-up;
 1261                                         drive-strength = <2>;
 1262                                 };
 1263 
 1264                                 data {
 1265                                         pins = "sdc1_data";
 1266                                         bias-pull-up;
 1267                                         drive-strength = <2>;
 1268                                 };
 1269                         };
 1270 
 1271                         sdc2_off: sdc2-off {
 1272                                 clk {
 1273                                         pins = "sdc2_clk";
 1274                                         bias-disable;
 1275                                         drive-strength = <2>;
 1276                                 };
 1277 
 1278                                 cmd {
 1279                                         pins = "sdc2_cmd";
 1280                                         bias-pull-up;
 1281                                         drive-strength = <2>;
 1282                                 };
 1283 
 1284                                 data {
 1285                                         pins = "sdc2_data";
 1286                                         bias-pull-up;
 1287                                         drive-strength = <2>;
 1288                                 };
 1289 
 1290                                 cd {
 1291                                         pins = "gpio54";
 1292                                         bias-disable;
 1293                                         drive-strength = <2>;
 1294                                 };
 1295                         };
 1296 
 1297                         blsp1_uart2_default: blsp1-uart2-default {
 1298                                 rx {
 1299                                         pins = "gpio5";
 1300                                         function = "blsp_uart2";
 1301                                         drive-strength = <2>;
 1302                                         bias-pull-up;
 1303                                 };
 1304 
 1305                                 tx {
 1306                                         pins = "gpio4";
 1307                                         function = "blsp_uart2";
 1308                                         drive-strength = <4>;
 1309                                         bias-disable;
 1310                                 };
 1311                         };
 1312 
 1313                         blsp2_uart1_default: blsp2-uart1-default {
 1314                                 tx-rts {
 1315                                         pins = "gpio41", "gpio44";
 1316                                         function = "blsp_uart7";
 1317                                         drive-strength = <2>;
 1318                                         bias-disable;
 1319                                 };
 1320 
 1321                                 rx-cts {
 1322                                         pins = "gpio42", "gpio43";
 1323                                         function = "blsp_uart7";
 1324                                         drive-strength = <2>;
 1325                                         bias-pull-up;
 1326                                 };
 1327                         };
 1328 
 1329                         blsp2_uart1_sleep: blsp2-uart1-sleep {
 1330                                 pins = "gpio41", "gpio42", "gpio43", "gpio44";
 1331                                 function = "gpio";
 1332                                 drive-strength = <2>;
 1333                                 bias-pull-down;
 1334                         };
 1335 
 1336                         blsp2_uart4_default: blsp2-uart4-default {
 1337                                 tx-rts {
 1338                                         pins = "gpio53", "gpio56";
 1339                                         function = "blsp_uart10";
 1340                                         drive-strength = <2>;
 1341                                         bias-disable;
 1342                                 };
 1343 
 1344                                 rx-cts {
 1345                                         pins = "gpio54", "gpio55";
 1346                                         function = "blsp_uart10";
 1347                                         drive-strength = <2>;
 1348                                         bias-pull-up;
 1349                                 };
 1350                         };
 1351 
 1352                         blsp1_i2c1_default: blsp1-i2c1-default {
 1353                                 pins = "gpio2", "gpio3";
 1354                                 function = "blsp_i2c1";
 1355                                 drive-strength = <2>;
 1356                                 bias-disable;
 1357                         };
 1358 
 1359                         blsp1_i2c1_sleep: blsp1-i2c1-sleep {
 1360                                 pins = "gpio2", "gpio3";
 1361                                 function = "blsp_i2c1";
 1362                                 drive-strength = <2>;
 1363                                 bias-pull-up;
 1364                         };
 1365 
 1366                         blsp1_i2c2_default: blsp1-i2c2-default {
 1367                                 pins = "gpio6", "gpio7";
 1368                                 function = "blsp_i2c2";
 1369                                 drive-strength = <2>;
 1370                                 bias-disable;
 1371                         };
 1372 
 1373                         blsp1_i2c2_sleep: blsp1-i2c2-sleep {
 1374                                 pins = "gpio6", "gpio7";
 1375                                 function = "blsp_i2c2";
 1376                                 drive-strength = <2>;
 1377                                 bias-pull-up;
 1378                         };
 1379 
 1380                         blsp1_i2c3_default: blsp1-i2c3-default {
 1381                                 pins = "gpio10", "gpio11";
 1382                                 function = "blsp_i2c3";
 1383                                 drive-strength = <2>;
 1384                                 bias-disable;
 1385                         };
 1386 
 1387                         blsp1_i2c3_sleep: blsp1-i2c3-sleep {
 1388                                 pins = "gpio10", "gpio11";
 1389                                 function = "blsp_i2c3";
 1390                                 drive-strength = <2>;
 1391                                 bias-pull-up;
 1392                         };
 1393 
 1394                         /* BLSP1_I2C4 info is missing */
 1395 
 1396                         /* BLSP1_I2C5 info is missing */
 1397 
 1398                         blsp1_i2c6_default: blsp1-i2c6-default {
 1399                                 pins = "gpio29", "gpio30";
 1400                                 function = "blsp_i2c6";
 1401                                 drive-strength = <2>;
 1402                                 bias-disable;
 1403                         };
 1404 
 1405                         blsp1_i2c6_sleep: blsp1-i2c6-sleep {
 1406                                 pins = "gpio29", "gpio30";
 1407                                 function = "blsp_i2c6";
 1408                                 drive-strength = <2>;
 1409                                 bias-pull-up;
 1410                         };
 1411                         /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
 1412 
 1413                         /* BLSP2_I2C1 info is missing */
 1414 
 1415                         blsp2_i2c2_default: blsp2-i2c2-default {
 1416                                 pins = "gpio47", "gpio48";
 1417                                 function = "blsp_i2c8";
 1418                                 drive-strength = <2>;
 1419                                 bias-disable;
 1420                         };
 1421 
 1422                         blsp2_i2c2_sleep: blsp2-i2c2-sleep {
 1423                                 pins = "gpio47", "gpio48";
 1424                                 function = "blsp_i2c8";
 1425                                 drive-strength = <2>;
 1426                                 bias-pull-up;
 1427                         };
 1428 
 1429                         /* BLSP2_I2C3 info is missing */
 1430 
 1431                         /* BLSP2_I2C4 info is missing */
 1432 
 1433                         blsp2_i2c5_default: blsp2-i2c5-default {
 1434                                 pins = "gpio83", "gpio84";
 1435                                 function = "blsp_i2c11";
 1436                                 drive-strength = <2>;
 1437                                 bias-disable;
 1438                         };
 1439 
 1440                         blsp2_i2c5_sleep: blsp2-i2c5-sleep {
 1441                                 pins = "gpio83", "gpio84";
 1442                                 function = "blsp_i2c11";
 1443                                 drive-strength = <2>;
 1444                                 bias-pull-up;
 1445                         };
 1446 
 1447                         blsp2_i2c6_default: blsp2-i2c6-default {
 1448                                 pins = "gpio87", "gpio88";
 1449                                 function = "blsp_i2c12";
 1450                                 drive-strength = <2>;
 1451                                 bias-disable;
 1452                         };
 1453 
 1454                         blsp2_i2c6_sleep: blsp2-i2c6-sleep {
 1455                                 pins = "gpio87", "gpio88";
 1456                                 function = "blsp_i2c12";
 1457                                 drive-strength = <2>;
 1458                                 bias-pull-up;
 1459                         };
 1460 
 1461                         spi8_default: spi8_default {
 1462                                 mosi {
 1463                                         pins = "gpio45";
 1464                                         function = "blsp_spi8";
 1465                                 };
 1466                                 miso {
 1467                                         pins = "gpio46";
 1468                                         function = "blsp_spi8";
 1469                                 };
 1470                                 cs {
 1471                                         pins = "gpio47";
 1472                                         function = "blsp_spi8";
 1473                                 };
 1474                                 clk {
 1475                                         pins = "gpio48";
 1476                                         function = "blsp_spi8";
 1477                                 };
 1478                         };
 1479                 };
 1480 
 1481                 mmcc: clock-controller@fd8c0000 {
 1482                         compatible = "qcom,mmcc-msm8974";
 1483                         #clock-cells = <1>;
 1484                         #reset-cells = <1>;
 1485                         #power-domain-cells = <1>;
 1486                         reg = <0xfd8c0000 0x6000>;
 1487                 };
 1488 
 1489                 mdss: mdss@fd900000 {
 1490                         compatible = "qcom,mdss";
 1491                         reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
 1492                         reg-names = "mdss_phys", "vbif_phys";
 1493 
 1494                         power-domains = <&mmcc MDSS_GDSC>;
 1495 
 1496                         clocks = <&mmcc MDSS_AHB_CLK>,
 1497                                  <&mmcc MDSS_AXI_CLK>,
 1498                                  <&mmcc MDSS_VSYNC_CLK>;
 1499                         clock-names = "iface", "bus", "vsync";
 1500 
 1501                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 1502 
 1503                         interrupt-controller;
 1504                         #interrupt-cells = <1>;
 1505 
 1506                         status = "disabled";
 1507 
 1508                         #address-cells = <1>;
 1509                         #size-cells = <1>;
 1510                         ranges;
 1511 
 1512                         mdp: mdp@fd900000 {
 1513                                 compatible = "qcom,mdp5";
 1514                                 reg = <0xfd900100 0x22000>;
 1515                                 reg-names = "mdp_phys";
 1516 
 1517                                 interrupt-parent = <&mdss>;
 1518                                 interrupts = <0>;
 1519 
 1520                                 clocks = <&mmcc MDSS_AHB_CLK>,
 1521                                          <&mmcc MDSS_AXI_CLK>,
 1522                                          <&mmcc MDSS_MDP_CLK>,
 1523                                          <&mmcc MDSS_VSYNC_CLK>;
 1524                                 clock-names = "iface", "bus", "core", "vsync";
 1525 
 1526                                 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
 1527                                 interconnect-names = "mdp0-mem";
 1528 
 1529                                 ports {
 1530                                         #address-cells = <1>;
 1531                                         #size-cells = <0>;
 1532 
 1533                                         port@0 {
 1534                                                 reg = <0>;
 1535                                                 mdp5_intf1_out: endpoint {
 1536                                                         remote-endpoint = <&dsi0_in>;
 1537                                                 };
 1538                                         };
 1539                                 };
 1540                         };
 1541 
 1542                         dsi0: dsi@fd922800 {
 1543                                 compatible = "qcom,mdss-dsi-ctrl";
 1544                                 reg = <0xfd922800 0x1f8>;
 1545                                 reg-names = "dsi_ctrl";
 1546 
 1547                                 interrupt-parent = <&mdss>;
 1548                                 interrupts = <4>;
 1549 
 1550                                 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
 1551                                 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
 1552 
 1553                                 clocks = <&mmcc MDSS_MDP_CLK>,
 1554                                          <&mmcc MDSS_AHB_CLK>,
 1555                                          <&mmcc MDSS_AXI_CLK>,
 1556                                          <&mmcc MDSS_BYTE0_CLK>,
 1557                                          <&mmcc MDSS_PCLK0_CLK>,
 1558                                          <&mmcc MDSS_ESC0_CLK>,
 1559                                          <&mmcc MMSS_MISC_AHB_CLK>;
 1560                                 clock-names = "mdp_core",
 1561                                               "iface",
 1562                                               "bus",
 1563                                               "byte",
 1564                                               "pixel",
 1565                                               "core",
 1566                                               "core_mmss";
 1567 
 1568                                 phys = <&dsi0_phy>;
 1569                                 phy-names = "dsi-phy";
 1570 
 1571                                 status = "disabled";
 1572 
 1573                                 #address-cells = <1>;
 1574                                 #size-cells = <0>;
 1575 
 1576                                 ports {
 1577                                         #address-cells = <1>;
 1578                                         #size-cells = <0>;
 1579 
 1580                                         port@0 {
 1581                                                 reg = <0>;
 1582                                                 dsi0_in: endpoint {
 1583                                                         remote-endpoint = <&mdp5_intf1_out>;
 1584                                                 };
 1585                                         };
 1586 
 1587                                         port@1 {
 1588                                                 reg = <1>;
 1589                                                 dsi0_out: endpoint {
 1590                                                 };
 1591                                         };
 1592                                 };
 1593                         };
 1594 
 1595                         dsi0_phy: dsi-phy@fd922a00 {
 1596                                 compatible = "qcom,dsi-phy-28nm-hpm";
 1597                                 reg = <0xfd922a00 0xd4>,
 1598                                       <0xfd922b00 0x280>,
 1599                                       <0xfd922d80 0x30>;
 1600                                 reg-names = "dsi_pll",
 1601                                             "dsi_phy",
 1602                                             "dsi_phy_regulator";
 1603 
 1604                                 #clock-cells = <1>;
 1605                                 #phy-cells = <0>;
 1606 
 1607                                 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
 1608                                 clock-names = "iface", "ref";
 1609 
 1610                                 status = "disabled";
 1611                         };
 1612                 };
 1613 
 1614                 gpu: adreno@fdb00000 {
 1615                         compatible = "qcom,adreno-330.1", "qcom,adreno";
 1616                         reg = <0xfdb00000 0x10000>;
 1617                         reg-names = "kgsl_3d0_reg_memory";
 1618 
 1619                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 1620                         interrupt-names = "kgsl_3d0_irq";
 1621 
 1622                         clocks = <&mmcc OXILI_GFX3D_CLK>,
 1623                                  <&mmcc OXILICX_AHB_CLK>,
 1624                                  <&mmcc OXILICX_AXI_CLK>;
 1625                         clock-names = "core", "iface", "mem_iface";
 1626 
 1627                         sram = <&gmu_sram>;
 1628                         power-domains = <&mmcc OXILICX_GDSC>;
 1629                         operating-points-v2 = <&gpu_opp_table>;
 1630 
 1631                         interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
 1632                                         <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
 1633                         interconnect-names = "gfx-mem", "ocmem";
 1634 
 1635                         // iommus = <&gpu_iommu 0>;
 1636 
 1637                         status = "disabled";
 1638 
 1639                         gpu_opp_table: opp-table {
 1640                                 compatible = "operating-points-v2";
 1641 
 1642                                 opp-320000000 {
 1643                                         opp-hz = /bits/ 64 <320000000>;
 1644                                 };
 1645 
 1646                                 opp-200000000 {
 1647                                         opp-hz = /bits/ 64 <200000000>;
 1648                                 };
 1649 
 1650                                 opp-27000000 {
 1651                                         opp-hz = /bits/ 64 <27000000>;
 1652                                 };
 1653                         };
 1654                 };
 1655 
 1656                 sram@fdd00000 {
 1657                         compatible = "qcom,msm8974-ocmem";
 1658                         reg = <0xfdd00000 0x2000>,
 1659                               <0xfec00000 0x180000>;
 1660                         reg-names = "ctrl", "mem";
 1661                         ranges = <0 0xfec00000 0x180000>;
 1662                         clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
 1663                                  <&mmcc OCMEMCX_OCMEMNOC_CLK>;
 1664                         clock-names = "core", "iface";
 1665 
 1666                         #address-cells = <1>;
 1667                         #size-cells = <1>;
 1668 
 1669                         gmu_sram: gmu-sram@0 {
 1670                                 reg = <0x0 0x100000>;
 1671                         };
 1672                 };
 1673 
 1674                 remoteproc_adsp: remoteproc@fe200000 {
 1675                         compatible = "qcom,msm8974-adsp-pil";
 1676                         reg = <0xfe200000 0x100>;
 1677 
 1678                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 1679                                                <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 1680                                                <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 1681                                                <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 1682                                                <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 1683                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 1684 
 1685                         clocks = <&xo_board>;
 1686                         clock-names = "xo";
 1687 
 1688                         memory-region = <&adsp_region>;
 1689 
 1690                         qcom,smem-states = <&adsp_smp2p_out 0>;
 1691                         qcom,smem-state-names = "stop";
 1692 
 1693                         status = "disabled";
 1694 
 1695                         smd-edge {
 1696                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 1697 
 1698                                 qcom,ipc = <&apcs 8 8>;
 1699                                 qcom,smd-edge = <1>;
 1700                                 label = "lpass";
 1701                                 #address-cells = <1>;
 1702                                 #size-cells = <0>;
 1703                         };
 1704                 };
 1705 
 1706                 imem: sram@fe805000 {
 1707                         compatible = "qcom,msm8974-imem", "syscon", "simple-mfd";
 1708                         reg = <0xfe805000 0x1000>;
 1709 
 1710                         reboot-mode {
 1711                                 compatible = "syscon-reboot-mode";
 1712                                 offset = <0x65c>;
 1713                         };
 1714                 };
 1715         };
 1716 
 1717         tcsr_mutex: tcsr-mutex {
 1718                 compatible = "qcom,tcsr-mutex";
 1719                 syscon = <&tcsr_mutex_block 0 0x80>;
 1720 
 1721                 #hwlock-cells = <1>;
 1722         };
 1723 
 1724         thermal-zones {
 1725                 cpu0-thermal {
 1726                         polling-delay-passive = <250>;
 1727                         polling-delay = <1000>;
 1728 
 1729                         thermal-sensors = <&tsens 5>;
 1730 
 1731                         trips {
 1732                                 cpu_alert0: trip0 {
 1733                                         temperature = <75000>;
 1734                                         hysteresis = <2000>;
 1735                                         type = "passive";
 1736                                 };
 1737                                 cpu_crit0: trip1 {
 1738                                         temperature = <110000>;
 1739                                         hysteresis = <2000>;
 1740                                         type = "critical";
 1741                                 };
 1742                         };
 1743                 };
 1744 
 1745                 cpu1-thermal {
 1746                         polling-delay-passive = <250>;
 1747                         polling-delay = <1000>;
 1748 
 1749                         thermal-sensors = <&tsens 6>;
 1750 
 1751                         trips {
 1752                                 cpu_alert1: trip0 {
 1753                                         temperature = <75000>;
 1754                                         hysteresis = <2000>;
 1755                                         type = "passive";
 1756                                 };
 1757                                 cpu_crit1: trip1 {
 1758                                         temperature = <110000>;
 1759                                         hysteresis = <2000>;
 1760                                         type = "critical";
 1761                                 };
 1762                         };
 1763                 };
 1764 
 1765                 cpu2-thermal {
 1766                         polling-delay-passive = <250>;
 1767                         polling-delay = <1000>;
 1768 
 1769                         thermal-sensors = <&tsens 7>;
 1770 
 1771                         trips {
 1772                                 cpu_alert2: trip0 {
 1773                                         temperature = <75000>;
 1774                                         hysteresis = <2000>;
 1775                                         type = "passive";
 1776                                 };
 1777                                 cpu_crit2: trip1 {
 1778                                         temperature = <110000>;
 1779                                         hysteresis = <2000>;
 1780                                         type = "critical";
 1781                                 };
 1782                         };
 1783                 };
 1784 
 1785                 cpu3-thermal {
 1786                         polling-delay-passive = <250>;
 1787                         polling-delay = <1000>;
 1788 
 1789                         thermal-sensors = <&tsens 8>;
 1790 
 1791                         trips {
 1792                                 cpu_alert3: trip0 {
 1793                                         temperature = <75000>;
 1794                                         hysteresis = <2000>;
 1795                                         type = "passive";
 1796                                 };
 1797                                 cpu_crit3: trip1 {
 1798                                         temperature = <110000>;
 1799                                         hysteresis = <2000>;
 1800                                         type = "critical";
 1801                                 };
 1802                         };
 1803                 };
 1804 
 1805                 q6-dsp-thermal {
 1806                         polling-delay-passive = <250>;
 1807                         polling-delay = <1000>;
 1808 
 1809                         thermal-sensors = <&tsens 1>;
 1810 
 1811                         trips {
 1812                                 q6_dsp_alert0: trip-point0 {
 1813                                         temperature = <90000>;
 1814                                         hysteresis = <2000>;
 1815                                         type = "hot";
 1816                                 };
 1817                         };
 1818                 };
 1819 
 1820                 modemtx-thermal {
 1821                         polling-delay-passive = <250>;
 1822                         polling-delay = <1000>;
 1823 
 1824                         thermal-sensors = <&tsens 2>;
 1825 
 1826                         trips {
 1827                                 modemtx_alert0: trip-point0 {
 1828                                         temperature = <90000>;
 1829                                         hysteresis = <2000>;
 1830                                         type = "hot";
 1831                                 };
 1832                         };
 1833                 };
 1834 
 1835                 video-thermal {
 1836                         polling-delay-passive = <250>;
 1837                         polling-delay = <1000>;
 1838 
 1839                         thermal-sensors = <&tsens 3>;
 1840 
 1841                         trips {
 1842                                 video_alert0: trip-point0 {
 1843                                         temperature = <95000>;
 1844                                         hysteresis = <2000>;
 1845                                         type = "hot";
 1846                                 };
 1847                         };
 1848                 };
 1849 
 1850                 wlan-thermal {
 1851                         polling-delay-passive = <250>;
 1852                         polling-delay = <1000>;
 1853 
 1854                         thermal-sensors = <&tsens 4>;
 1855 
 1856                         trips {
 1857                                 wlan_alert0: trip-point0 {
 1858                                         temperature = <105000>;
 1859                                         hysteresis = <2000>;
 1860                                         type = "hot";
 1861                                 };
 1862                         };
 1863                 };
 1864 
 1865                 gpu-top-thermal {
 1866                         polling-delay-passive = <250>;
 1867                         polling-delay = <1000>;
 1868 
 1869                         thermal-sensors = <&tsens 9>;
 1870 
 1871                         trips {
 1872                                 gpu1_alert0: trip-point0 {
 1873                                         temperature = <90000>;
 1874                                         hysteresis = <2000>;
 1875                                         type = "hot";
 1876                                 };
 1877                         };
 1878                 };
 1879 
 1880                 gpu-bottom-thermal {
 1881                         polling-delay-passive = <250>;
 1882                         polling-delay = <1000>;
 1883 
 1884                         thermal-sensors = <&tsens 10>;
 1885 
 1886                         trips {
 1887                                 gpu2_alert0: trip-point0 {
 1888                                         temperature = <90000>;
 1889                                         hysteresis = <2000>;
 1890                                         type = "hot";
 1891                                 };
 1892                         };
 1893                 };
 1894         };
 1895 
 1896         timer {
 1897                 compatible = "arm,armv7-timer";
 1898                 interrupts = <GIC_PPI 2 0xf08>,
 1899                              <GIC_PPI 3 0xf08>,
 1900                              <GIC_PPI 4 0xf08>,
 1901                              <GIC_PPI 1 0xf08>;
 1902                 clock-frequency = <19200000>;
 1903         };
 1904 
 1905         vreg_boost: vreg-boost {
 1906                 compatible = "regulator-fixed";
 1907 
 1908                 regulator-name = "vreg-boost";
 1909                 regulator-min-microvolt = <3150000>;
 1910                 regulator-max-microvolt = <3150000>;
 1911 
 1912                 regulator-always-on;
 1913                 regulator-boot-on;
 1914 
 1915                 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
 1916                 enable-active-high;
 1917 
 1918                 pinctrl-names = "default";
 1919                 pinctrl-0 = <&boost_bypass_n_pin>;
 1920         };
 1921 
 1922         vreg_vph_pwr: vreg-vph-pwr {
 1923                 compatible = "regulator-fixed";
 1924                 regulator-name = "vph-pwr";
 1925 
 1926                 regulator-min-microvolt = <3600000>;
 1927                 regulator-max-microvolt = <3600000>;
 1928 
 1929                 regulator-always-on;
 1930         };
 1931 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/qcom-msm8974.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/qcom-msm8974.dtsi
