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sys/contrib/device-tree/src/arm/qcom-sdx65.dtsi
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1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * SDX65 SoC device tree source 4 * 5 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 6 * 7 */ 8 9 #include <dt-bindings/clock/qcom,gcc-sdx65.h> 10 #include <dt-bindings/clock/qcom,rpmh.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/power/qcom-rpmpd.h> 13 #include <dt-bindings/soc/qcom,rpmh-rsc.h> 14 15 / { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>; 19 interrupt-parent = <&intc>; 20 21 memory { 22 device_type = "memory"; 23 reg = <0 0>; 24 }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 clock-frequency = <76800000>; 30 clock-output-names = "xo_board"; 31 #clock-cells = <0>; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 clock-frequency = <32764>; 37 clock-output-names = "sleep_clk"; 38 #clock-cells = <0>; 39 }; 40 41 nand_clk_dummy: nand-clk-dummy { 42 compatible = "fixed-clock"; 43 clock-frequency = <32764>; 44 #clock-cells = <0>; 45 }; 46 }; 47 48 cpus { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a7"; 55 reg = <0x0>; 56 enable-method = "psci"; 57 clocks = <&apcs>; 58 power-domains = <&rpmhpd SDX65_CX_AO>; 59 power-domain-names = "rpmhpd"; 60 operating-points-v2 = <&cpu_opp_table>; 61 }; 62 }; 63 64 cpu_opp_table: cpu-opp-table { 65 compatible = "operating-points-v2"; 66 opp-shared; 67 68 opp-345600000 { 69 opp-hz = /bits/ 64 <345600000>; 70 required-opps = <&rpmhpd_opp_low_svs>; 71 }; 72 73 opp-576000000 { 74 opp-hz = /bits/ 64 <576000000>; 75 required-opps = <&rpmhpd_opp_svs>; 76 }; 77 78 opp-1094400000 { 79 opp-hz = /bits/ 64 <1094400000>; 80 required-opps = <&rpmhpd_opp_nom>; 81 }; 82 83 opp-1497600000 { 84 opp-hz = /bits/ 64 <1497600000>; 85 required-opps = <&rpmhpd_opp_turbo>; 86 }; 87 }; 88 89 firmware { 90 scm { 91 compatible = "qcom,scm-sdx65", "qcom,scm"; 92 }; 93 }; 94 95 mc_virt: interconnect-mc-virt { 96 compatible = "qcom,sdx65-mc-virt"; 97 #interconnect-cells = <1>; 98 qcom,bcm-voters = <&apps_bcm_voter>; 99 }; 100 101 psci { 102 compatible = "arm,psci-1.0"; 103 method = "smc"; 104 }; 105 106 reserved_memory: reserved-memory { 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges; 110 111 tz_heap_mem: memory@8fcad000 { 112 no-map; 113 reg = <0x8fcad000 0x40000>; 114 }; 115 116 secdata_mem: memory@8fcfd000 { 117 no-map; 118 reg = <0x8fcfd000 0x1000>; 119 }; 120 121 hyp_mem: memory@8fd00000 { 122 no-map; 123 reg = <0x8fd00000 0x80000>; 124 }; 125 126 access_control_mem: memory@8fd80000 { 127 no-map; 128 reg = <0x8fd80000 0x80000>; 129 }; 130 131 aop_mem: memory@8fe00000 { 132 no-map; 133 reg = <0x8fe00000 0x20000>; 134 }; 135 136 smem_mem: memory@8fe20000 { 137 compatible = "qcom,smem"; 138 reg = <0x8fe20000 0xc0000>; 139 hwlocks = <&tcsr_mutex 3>; 140 no-map; 141 }; 142 143 cmd_db: reserved-memory@8fee0000 { 144 compatible = "qcom,cmd-db"; 145 reg = <0x8fee0000 0x20000>; 146 no-map; 147 }; 148 149 tz_mem: memory@8ff00000 { 150 no-map; 151 reg = <0x8ff00000 0x100000>; 152 }; 153 154 tz_apps_mem: memory@90000000 { 155 no-map; 156 reg = <0x90000000 0x500000>; 157 }; 158 159 llcc_tcm_mem: memory@15800000 { 160 no-map; 161 reg = <0x15800000 0x800000>; 162 }; 163 }; 164 165 smp2p-mpss { 166 compatible = "qcom,smp2p"; 167 qcom,smem = <435>, <428>; 168 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 169 mboxes = <&apcs 14>; 170 qcom,local-pid = <0>; 171 qcom,remote-pid = <1>; 172 173 modem_smp2p_out: master-kernel { 174 qcom,entry-name = "master-kernel"; 175 #qcom,smem-state-cells = <1>; 176 }; 177 178 modem_smp2p_in: slave-kernel { 179 qcom,entry-name = "slave-kernel"; 180 interrupt-controller; 181 #interrupt-cells = <2>; 182 }; 183 184 ipa_smp2p_out: ipa-ap-to-modem { 185 qcom,entry-name = "ipa"; 186 #qcom,smem-state-cells = <1>; 187 }; 188 189 ipa_smp2p_in: ipa-modem-to-ap { 190 qcom,entry-name = "ipa"; 191 interrupt-controller; 192 #interrupt-cells = <2>; 193 }; 194 }; 195 196 soc: soc { 197 #address-cells = <1>; 198 #size-cells = <1>; 199 ranges; 200 compatible = "simple-bus"; 201 202 gcc: clock-controller@100000 { 203 compatible = "qcom,gcc-sdx65"; 204 reg = <0x00100000 0x001f7400>; 205 clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; 206 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 207 #power-domain-cells = <1>; 208 #clock-cells = <1>; 209 #reset-cells = <1>; 210 }; 211 212 blsp1_uart3: serial@831000 { 213 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 214 reg = <0x00831000 0x200>; 215 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 217 clock-names = "core", "iface"; 218 status = "disabled"; 219 }; 220 221 usb_hsphy: phy@ff4000 { 222 compatible = "qcom,usb-snps-hs-7nm-phy"; 223 reg = <0xff4000 0x120>; 224 #phy-cells = <0>; 225 status = "disabled"; 226 clocks = <&rpmhcc RPMH_CXO_CLK>; 227 clock-names = "ref"; 228 resets = <&gcc GCC_QUSB2PHY_BCR>; 229 }; 230 231 usb_qmpphy: phy@ff6000 { 232 compatible = "qcom,sdx65-qmp-usb3-uni-phy"; 233 reg = <0x00ff6000 0x1c8>; 234 status = "disabled"; 235 #address-cells = <1>; 236 #size-cells = <1>; 237 ranges; 238 239 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 240 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 241 <&gcc GCC_USB3_PRIM_CLKREF_EN>; 242 clock-names = "aux", "cfg_ahb", "ref"; 243 244 resets = <&gcc GCC_USB3PHY_PHY_BCR>, 245 <&gcc GCC_USB3_PHY_BCR>; 246 reset-names = "phy", "common"; 247 248 usb_ssphy: phy@ff6200 { 249 reg = <0x00ff6e00 0x160>, 250 <0x00ff7000 0x1ec>, 251 <0x00ff6200 0x1e00>; 252 #phy-cells = <0>; 253 #clock-cells = <0>; 254 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 255 clock-names = "pipe0"; 256 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 257 }; 258 }; 259 260 system_noc: interconnect@1620000 { 261 compatible = "qcom,sdx65-system-noc"; 262 reg = <0x01620000 0x31200>; 263 #interconnect-cells = <1>; 264 qcom,bcm-voters = <&apps_bcm_voter>; 265 }; 266 267 qpic_bam: dma-controller@1b04000 { 268 compatible = "qcom,bam-v1.7.0"; 269 reg = <0x01b04000 0x1c000>; 270 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&rpmhcc RPMH_QPIC_CLK>; 272 clock-names = "bam_clk"; 273 #dma-cells = <1>; 274 qcom,ee = <0>; 275 qcom,controlled-remotely; 276 status = "disabled"; 277 }; 278 279 qpic_nand: nand-controller@1b30000 { 280 compatible = "qcom,sdx55-nand"; 281 reg = <0x01b30000 0x10000>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 clocks = <&rpmhcc RPMH_QPIC_CLK>, 285 <&nand_clk_dummy>; 286 clock-names = "core", "aon"; 287 288 dmas = <&qpic_bam 0>, 289 <&qpic_bam 1>, 290 <&qpic_bam 2>; 291 dma-names = "tx", "rx", "cmd"; 292 status = "disabled"; 293 }; 294 295 tcsr_mutex: hwlock@1f40000 { 296 compatible = "qcom,tcsr-mutex"; 297 reg = <0x01f40000 0x40000>; 298 #hwlock-cells = <1>; 299 }; 300 301 remoteproc_mpss: remoteproc@4080000 { 302 compatible = "qcom,sdx55-mpss-pas"; 303 reg = <0x04080000 0x4040>; 304 305 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 306 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 307 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 308 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 309 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 310 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 311 interrupt-names = "wdog", "fatal", "ready", "handover", 312 "stop-ack", "shutdown-ack"; 313 314 clocks = <&rpmhcc RPMH_CXO_CLK>; 315 clock-names = "xo"; 316 317 power-domains = <&rpmhpd SDX65_CX>, 318 <&rpmhpd SDX65_MSS>; 319 power-domain-names = "cx", "mss"; 320 321 qcom,smem-states = <&modem_smp2p_out 0>; 322 qcom,smem-state-names = "stop"; 323 324 status = "disabled"; 325 326 glink-edge { 327 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; 328 label = "mpss"; 329 qcom,remote-pid = <1>; 330 mboxes = <&apcs 15>; 331 }; 332 }; 333 334 sdhc_1: mmc@8804000 { 335 compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; 336 reg = <0x08804000 0x1000>; 337 reg-names = "hc_mem"; 338 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-names = "hc_irq", "pwr_irq"; 341 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 342 <&gcc GCC_SDCC1_AHB_CLK>; 343 clock-names = "core", "iface"; 344 status = "disabled"; 345 }; 346 347 mem_noc: interconnect@9680000 { 348 compatible = "qcom,sdx65-mem-noc"; 349 reg = <0x09680000 0x27200>; 350 #interconnect-cells = <1>; 351 qcom,bcm-voters = <&apps_bcm_voter>; 352 }; 353 354 usb: usb@a6f8800 { 355 compatible = "qcom,sdx65-dwc3", "qcom,dwc3"; 356 reg = <0x0a6f8800 0x400>; 357 status = "disabled"; 358 #address-cells = <1>; 359 #size-cells = <1>; 360 ranges; 361 362 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, 363 <&gcc GCC_USB30_MASTER_CLK>, 364 <&gcc GCC_USB30_MSTR_AXI_CLK>, 365 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 366 <&gcc GCC_USB30_SLEEP_CLK>; 367 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 368 "sleep"; 369 370 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 371 <&gcc GCC_USB30_MASTER_CLK>; 372 assigned-clock-rates = <19200000>, <200000000>; 373 374 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 375 <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, 376 <&pdc 18 IRQ_TYPE_EDGE_BOTH>, 377 <&pdc 19 IRQ_TYPE_EDGE_BOTH>; 378 interrupt-names = "hs_phy_irq", 379 "ss_phy_irq", 380 "dm_hs_phy_irq", 381 "dp_hs_phy_irq"; 382 383 power-domains = <&gcc USB30_GDSC>; 384 385 resets = <&gcc GCC_USB30_BCR>; 386 387 usb_dwc3: usb@a600000 { 388 compatible = "snps,dwc3"; 389 reg = <0x0a600000 0xcd00>; 390 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 391 iommus = <&apps_smmu 0x1a0 0x0>; 392 snps,dis_u2_susphy_quirk; 393 snps,dis_enblslpm_quirk; 394 phys = <&usb_hsphy>, <&usb_ssphy>; 395 phy-names = "usb2-phy", "usb3-phy"; 396 }; 397 }; 398 399 restart@c264000 { 400 compatible = "qcom,pshold"; 401 reg = <0x0c264000 0x1000>; 402 }; 403 404 spmi_bus: qcom,spmi@c440000 { 405 compatible = "qcom,spmi-pmic-arb"; 406 reg = <0xc440000 0xd00>, 407 <0xc600000 0x2000000>, 408 <0xe600000 0x100000>, 409 <0xe700000 0xa0000>, 410 <0xc40a000 0x26000>; 411 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 412 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 413 interrupt-names = "periph_irq"; 414 interrupt-controller; 415 #interrupt-cells = <4>; 416 #address-cells = <2>; 417 #size-cells = <0>; 418 cell-index = <0>; 419 qcom,channel = <0>; 420 qcom,ee = <0>; 421 }; 422 423 tlmm: pinctrl@f100000 { 424 compatible = "qcom,sdx65-tlmm"; 425 reg = <0xf100000 0x300000>; 426 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 427 gpio-controller; 428 #gpio-cells = <2>; 429 gpio-ranges = <&tlmm 0 0 109>; 430 interrupt-controller; 431 interrupt-parent = <&intc>; 432 #interrupt-cells = <2>; 433 }; 434 435 pdc: interrupt-controller@b210000 { 436 compatible = "qcom,sdx65-pdc", "qcom,pdc"; 437 reg = <0xb210000 0x10000>; 438 qcom,pdc-ranges = <0 147 52>, <52 266 32>; 439 #interrupt-cells = <2>; 440 interrupt-parent = <&intc>; 441 interrupt-controller; 442 }; 443 444 imem@1468f000 { 445 compatible = "simple-mfd"; 446 reg = <0x1468f000 0x1000>; 447 ranges = <0x0 0x1468f000 0x1000>; 448 #address-cells = <1>; 449 #size-cells = <1>; 450 451 pil-reloc@94c { 452 compatible = "qcom,pil-reloc-info"; 453 reg = <0x94c 0xc8>; 454 }; 455 }; 456 457 apps_smmu: iommu@15000000 { 458 compatible = "qcom,sdx65-smmu-500", "arm,mmu-500"; 459 reg = <0x15000000 0x40000>; 460 #iommu-cells = <2>; 461 #global-interrupts = <1>; 462 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 495 }; 496 497 intc: interrupt-controller@17800000 { 498 compatible = "qcom,msm-qgic2"; 499 interrupt-controller; 500 interrupt-parent = <&intc>; 501 #interrupt-cells = <3>; 502 reg = <0x17800000 0x1000>, 503 <0x17802000 0x1000>; 504 }; 505 506 a7pll: clock@17808000 { 507 compatible = "qcom,sdx55-a7pll"; 508 reg = <0x17808000 0x1000>; 509 clocks = <&rpmhcc RPMH_CXO_CLK>; 510 clock-names = "bi_tcxo"; 511 #clock-cells = <0>; 512 }; 513 514 apcs: mailbox@17810000 { 515 compatible = "qcom,sdx55-apcs-gcc", "syscon"; 516 reg = <0x17810000 0x2000>; 517 #mbox-cells = <1>; 518 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; 519 clock-names = "ref", "pll", "aux"; 520 #clock-cells = <0>; 521 }; 522 523 watchdog@17817000 { 524 compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt"; 525 reg = <0x17817000 0x1000>; 526 clocks = <&sleep_clk>; 527 }; 528 529 timer@17820000 { 530 #address-cells = <1>; 531 #size-cells = <1>; 532 ranges; 533 compatible = "arm,armv7-timer-mem"; 534 reg = <0x17820000 0x1000>; 535 clock-frequency = <19200000>; 536 537 frame@17821000 { 538 frame-number = <0>; 539 interrupts = <GIC_SPI 7 0x4>, 540 <GIC_SPI 6 0x4>; 541 reg = <0x17821000 0x1000>, 542 <0x17822000 0x1000>; 543 }; 544 545 frame@17823000 { 546 frame-number = <1>; 547 interrupts = <GIC_SPI 8 0x4>; 548 reg = <0x17823000 0x1000>; 549 status = "disabled"; 550 }; 551 552 frame@17824000 { 553 frame-number = <2>; 554 interrupts = <GIC_SPI 9 0x4>; 555 reg = <0x17824000 0x1000>; 556 status = "disabled"; 557 }; 558 559 frame@17825000 { 560 frame-number = <3>; 561 interrupts = <GIC_SPI 10 0x4>; 562 reg = <0x17825000 0x1000>; 563 status = "disabled"; 564 }; 565 566 frame@17826000 { 567 frame-number = <4>; 568 interrupts = <GIC_SPI 11 0x4>; 569 reg = <0x17826000 0x1000>; 570 status = "disabled"; 571 }; 572 573 frame@17827000 { 574 frame-number = <5>; 575 interrupts = <GIC_SPI 12 0x4>; 576 reg = <0x17827000 0x1000>; 577 status = "disabled"; 578 }; 579 580 frame@17828000 { 581 frame-number = <6>; 582 interrupts = <GIC_SPI 13 0x4>; 583 reg = <0x17828000 0x1000>; 584 status = "disabled"; 585 }; 586 587 frame@17829000 { 588 frame-number = <7>; 589 interrupts = <GIC_SPI 14 0x4>; 590 reg = <0x17829000 0x1000>; 591 status = "disabled"; 592 }; 593 }; 594 595 apps_rsc: rsc@17830000 { 596 label = "apps_rsc"; 597 compatible = "qcom,rpmh-rsc"; 598 reg = <0x17830000 0x10000>, 599 <0x17840000 0x10000>; 600 reg-names = "drv-0", "drv-1"; 601 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 603 qcom,tcs-offset = <0xd00>; 604 qcom,drv-id = <1>; 605 qcom,tcs-config = <ACTIVE_TCS 2>, 606 <SLEEP_TCS 2>, 607 <WAKE_TCS 2>, 608 <CONTROL_TCS 1>; 609 610 rpmhcc: clock-controller { 611 compatible = "qcom,sdx65-rpmh-clk"; 612 #clock-cells = <1>; 613 clock-names = "xo"; 614 clocks = <&xo_board>; 615 }; 616 617 rpmhpd: power-controller { 618 compatible = "qcom,sdx65-rpmhpd"; 619 #power-domain-cells = <1>; 620 operating-points-v2 = <&rpmhpd_opp_table>; 621 622 rpmhpd_opp_table: opp-table { 623 compatible = "operating-points-v2"; 624 625 rpmhpd_opp_ret: opp1 { 626 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 627 }; 628 629 rpmhpd_opp_min_svs: opp2 { 630 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 631 }; 632 633 rpmhpd_opp_low_svs: opp3 { 634 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 635 }; 636 637 rpmhpd_opp_svs: opp4 { 638 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 639 }; 640 641 rpmhpd_opp_svs_l1: opp5 { 642 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 643 }; 644 645 rpmhpd_opp_nom: opp6 { 646 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 647 }; 648 649 rpmhpd_opp_nom_l1: opp7 { 650 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 651 }; 652 653 rpmhpd_opp_nom_l2: opp8 { 654 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 655 }; 656 657 rpmhpd_opp_turbo: opp9 { 658 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 659 }; 660 661 rpmhpd_opp_turbo_l1: opp10 { 662 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 663 }; 664 }; 665 }; 666 667 apps_bcm_voter: bcm-voter { 668 compatible = "qcom,bcm-voter"; 669 }; 670 671 }; 672 }; 673 674 timer { 675 compatible = "arm,armv7-timer"; 676 interrupts = <1 13 0xf08>, 677 <1 12 0xf08>, 678 <1 10 0xf08>, 679 <1 11 0xf08>; 680 clock-frequency = <19200000>; 681 }; 682 };
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