Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/rk3288-veyron-jerry.dts
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Google Veyron Jerry Rev 3+ board device tree source 4 * 5 * Copyright 2015 Google, Inc 6 */ 7 8 /dts-v1/; 9 #include "rk3288-veyron-chromebook.dtsi" 10 #include "cros-ec-sbs.dtsi" 11 12 / { 13 model = "Google Jerry"; 14 compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14", 15 "google,veyron-jerry-rev13", "google,veyron-jerry-rev12", 16 "google,veyron-jerry-rev11", "google,veyron-jerry-rev10", 17 "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", 18 "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", 19 "google,veyron-jerry-rev3", "google,veyron-jerry", 20 "google,veyron", "rockchip,rk3288"; 21 }; 22 23 &rk808 { 24 pinctrl-names = "default"; 25 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; 26 dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, 27 <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; 28 29 regulators { 30 mic_vcc: LDO_REG2 { 31 regulator-name = "mic_vcc"; 32 regulator-always-on; 33 regulator-boot-on; 34 regulator-min-microvolt = <1800000>; 35 regulator-max-microvolt = <1800000>; 36 regulator-state-mem { 37 regulator-off-in-suspend; 38 }; 39 }; 40 }; 41 }; 42 43 &sdio0 { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 47 mwifiex: wifi@1 { 48 compatible = "marvell,sd8897"; 49 reg = <1>; 50 51 marvell,caldata-txpwrlimit-2g = /bits/ 8 < 52 0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01 53 0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 54 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 55 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f 56 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 57 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 58 0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 59 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 60 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x04 0x00 0x0f 61 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 62 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 63 0x24 0x00 0x67 0x09 0x14 0x05 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 64 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 65 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x06 0x00 0x0f 66 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 67 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 68 0x24 0x00 0x67 0x09 0x14 0x07 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 69 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 70 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x08 0x00 0x0f 71 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 72 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 73 0x24 0x00 0x67 0x09 0x14 0x09 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 74 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 75 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0a 0x00 0x0f 76 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 77 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 78 0x24 0x00 0x67 0x09 0x14 0x0b 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 79 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 80 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0c 0x00 0x0f 81 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 82 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 83 0x24 0x00 0x67 0x09 0x14 0x0d 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 84 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 85 0x0d 0x09 0x0e 0x09 0x0f 0x09>; 86 87 marvell,caldata-txpwrlimit-5g-sub0 = /bits/ 8 < 88 0x01 0x00 0x06 0x00 0xf0 0x01 0x89 0x01 89 0x3a 0x00 0x88 0x13 0x14 0x24 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 90 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 91 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 92 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 93 0x88 0x13 0x14 0x28 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 94 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 95 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 96 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 97 0x14 0x2c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 98 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 99 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 100 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x30 101 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 102 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 103 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 104 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x34 0x01 0x0c 105 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 106 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 107 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 108 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x38 0x01 0x0c 0x02 0x0c 109 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 110 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 111 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 112 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x3c 0x01 0x0c 0x02 0x0c 0x03 0x0c 113 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 114 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 115 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 116 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x40 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 117 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 118 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 119 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>; 120 121 marvell,caldata-txpwrlimit-5g-sub1 = /bits/ 8 < 122 0x01 0x00 0x06 0x00 0xaa 0x02 0x89 0x01 123 0x3a 0x00 0x88 0x13 0x14 0x64 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 124 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 125 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 126 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 127 0x88 0x13 0x14 0x68 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 128 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 129 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 130 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 131 0x14 0x6c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 132 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 133 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 134 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x70 135 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 136 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 137 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 138 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x74 0x01 0x0c 139 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 140 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 141 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 142 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x78 0x01 0x0c 0x02 0x0c 143 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 144 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 145 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 146 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x7c 0x01 0x0c 0x02 0x0c 0x03 0x0c 147 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 148 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 149 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 150 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x80 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 151 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 152 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 153 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 154 0x3a 0x00 0x88 0x13 0x14 0x84 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 155 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 156 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 157 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 158 0x88 0x13 0x14 0x88 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 159 0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 160 0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 161 0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 162 0x14 0x8c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 163 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 164 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 165 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>; 166 167 marvell,caldata-txpwrlimit-5g-sub2 = /bits/ 8 < 168 0x01 0x00 0x06 0x00 0x36 0x01 0x89 0x01 169 0x3a 0x00 0x88 0x13 0x14 0x95 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 170 0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 171 0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 172 0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 173 0x88 0x13 0x14 0x99 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 174 0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 175 0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 176 0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 177 0x14 0x9d 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 178 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 179 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 180 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa1 181 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 182 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 183 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 184 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa5 0x01 0x0b 185 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 186 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 187 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 188 0x1a 0x05 0x1b 0x05>; 189 }; 190 }; 191 192 &sdmmc { 193 disable-wp; 194 pinctrl-names = "default"; 195 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin 196 &sdmmc_bus4>; 197 }; 198 199 &vcc_5v { 200 enable-active-high; 201 gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&drv_5v>; 204 }; 205 206 &vcc50_hdmi { 207 enable-active-high; 208 gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&vcc50_hdmi_en>; 211 }; 212 213 &gpio0 { 214 gpio-line-names = "PMIC_SLEEP_AP", 215 "DDRIO_PWROFF", 216 "DDRIO_RETEN", 217 "TS3A227E_INT_L", 218 "PMIC_INT_L", 219 "PWR_KEY_L", 220 "AP_LID_INT_L", 221 "EC_IN_RW", 222 223 "AC_PRESENT_AP", 224 /* 225 * RECOVERY_SW_L is Chrome OS ABI. Schematics call 226 * it REC_MODE_L. 227 */ 228 "RECOVERY_SW_L", 229 "OTP_OUT", 230 "HOST1_PWR_EN", 231 "USBOTG_PWREN_H", 232 "AP_WARM_RESET_H", 233 "nFAULT2", 234 "I2C0_SDA_PMIC", 235 236 "I2C0_SCL_PMIC", 237 "SUSPEND_L", 238 "USB_INT"; 239 }; 240 241 &gpio2 { 242 gpio-line-names = "CONFIG0", 243 "CONFIG1", 244 "CONFIG2", 245 "", 246 "", 247 "", 248 "", 249 "CONFIG3", 250 251 "", 252 "EMMC_RST_L", 253 "", 254 "", 255 "BL_PWR_EN", 256 "AVDD_1V8_DISP_EN"; 257 }; 258 259 &gpio3 { 260 gpio-line-names = "FLASH0_D0", 261 "FLASH0_D1", 262 "FLASH0_D2", 263 "FLASH0_D3", 264 "FLASH0_D4", 265 "FLASH0_D5", 266 "FLASH0_D6", 267 "FLASH0_D7", 268 269 "", 270 "", 271 "", 272 "", 273 "", 274 "", 275 "", 276 "", 277 278 "FLASH0_CS2/EMMC_CMD", 279 "", 280 "FLASH0_DQS/EMMC_CLKO"; 281 }; 282 283 &gpio4 { 284 gpio-line-names = "", 285 "", 286 "", 287 "", 288 "", 289 "", 290 "", 291 "", 292 293 "", 294 "", 295 "", 296 "", 297 "", 298 "", 299 "", 300 "", 301 302 "UART0_RXD", 303 "UART0_TXD", 304 "UART0_CTS", 305 "UART0_RTS", 306 "SDIO0_D0", 307 "SDIO0_D1", 308 "SDIO0_D2", 309 "SDIO0_D3", 310 311 "SDIO0_CMD", 312 "SDIO0_CLK", 313 "BT_DEV_WAKE", 314 "", 315 "WIFI_ENABLE_H", 316 "BT_ENABLE_L", 317 "WIFI_HOST_WAKE", 318 "BT_HOST_WAKE"; 319 }; 320 321 &gpio5 { 322 gpio-line-names = "", 323 "", 324 "", 325 "", 326 "", 327 "", 328 "", 329 "", 330 331 "", 332 "", 333 "", 334 "", 335 "SPI0_CLK", 336 "SPI0_CS0", 337 "SPI0_TXD", 338 "SPI0_RXD", 339 340 "", 341 "", 342 "", 343 "VCC50_HDMI_EN"; 344 }; 345 346 &gpio6 { 347 gpio-line-names = "I2S0_SCLK", 348 "I2S0_LRCK_RX", 349 "I2S0_LRCK_TX", 350 "I2S0_SDI", 351 "I2S0_SDO0", 352 "HP_DET_H", 353 "", 354 "INT_CODEC", 355 356 "I2S0_CLK", 357 "I2C2_SDA", 358 "I2C2_SCL", 359 "MICDET", 360 "", 361 "", 362 "", 363 "", 364 365 "SDMMC_D0", 366 "SDMMC_D1", 367 "SDMMC_D2", 368 "SDMMC_D3", 369 "SDMMC_CLK", 370 "SDMMC_CMD"; 371 }; 372 373 &gpio7 { 374 gpio-line-names = "LCDC_BL", 375 "PWM_LOG", 376 "BL_EN", 377 "TRACKPAD_INT", 378 "TPM_INT_H", 379 "SDMMC_DET_L", 380 /* 381 * AP_FLASH_WP_L is Chrome OS ABI. Schematics call 382 * it FW_WP_AP. 383 */ 384 "AP_FLASH_WP_L", 385 "EC_INT", 386 387 "CPU_NMI", 388 "DVSOK", 389 "", 390 "EDP_HPD", 391 "DVS1", 392 "nFAULT1", 393 "LCD_EN", 394 "DVS2", 395 396 "VCC5V_GOOD_H", 397 "I2C4_SDA_TP", 398 "I2C4_SCL_TP", 399 "I2C5_SDA_HDMI", 400 "I2C5_SCL_HDMI", 401 "5V_DRV", 402 "UART2_RXD", 403 "UART2_TXD"; 404 }; 405 406 &gpio8 { 407 gpio-line-names = "RAM_ID0", 408 "RAM_ID1", 409 "RAM_ID2", 410 "RAM_ID3", 411 "I2C1_SDA_TPM", 412 "I2C1_SCL_TPM", 413 "SPI2_CLK", 414 "SPI2_CS0", 415 416 "SPI2_RXD", 417 "SPI2_TXD"; 418 }; 419 420 &pinctrl { 421 pinctrl-names = "default", "sleep"; 422 pinctrl-0 = < 423 /* Common for sleep and wake, but no owners */ 424 &ddr0_retention 425 &ddrio_pwroff 426 &global_pwroff 427 428 /* Wake only */ 429 &suspend_l_wake 430 &bt_dev_wake_awake 431 >; 432 pinctrl-1 = < 433 /* Common for sleep and wake, but no owners */ 434 &ddr0_retention 435 &ddrio_pwroff 436 &global_pwroff 437 438 /* Sleep only */ 439 &suspend_l_sleep 440 &bt_dev_wake_sleep 441 >; 442 443 buck-5v { 444 drv_5v: drv-5v { 445 rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 446 }; 447 }; 448 449 hdmi { 450 vcc50_hdmi_en: vcc50-hdmi-en { 451 rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 452 }; 453 }; 454 455 pmic { 456 dvs_1: dvs-1 { 457 rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; 458 }; 459 460 dvs_2: dvs-2 { 461 rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; 462 }; 463 }; 464 }; 465 466 &i2c4 { 467 status = "okay"; 468 469 /* 470 * Trackpad pin control is shared between Elan and Synaptics devices 471 * so we have to pull it up to the bus level. 472 */ 473 pinctrl-names = "default"; 474 pinctrl-0 = <&i2c4_xfer &trackpad_int>; 475 476 trackpad@15 { 477 /* 478 * Remove the inherited pinctrl settings to avoid clashing 479 * with bus-wide ones. 480 */ 481 /delete-property/pinctrl-names; 482 /delete-property/pinctrl-0; 483 }; 484 485 trackpad@2c { 486 compatible = "hid-over-i2c"; 487 interrupt-parent = <&gpio7>; 488 interrupts = <RK_PA3 IRQ_TYPE_EDGE_FALLING>; 489 reg = <0x2c>; 490 hid-descr-addr = <0x0020>; 491 vcc-supply = <&vcc33_io>; 492 wakeup-source; 493 }; 494 };
Cache object: 0ed5be36c8b09490a9ad417b8c622b44
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