Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/rk3xxx.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7 #include <dt-bindings/interrupt-controller/irq.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/soc/rockchip,boot-mode.h> 10 11 / { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 interrupt-parent = <&gic>; 16 17 aliases { 18 ethernet0 = &emac; 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 serial0 = &uart0; 25 serial1 = &uart1; 26 serial2 = &uart2; 27 serial3 = &uart3; 28 spi0 = &spi0; 29 spi1 = &spi1; 30 }; 31 32 xin24m: oscillator { 33 compatible = "fixed-clock"; 34 clock-frequency = <24000000>; 35 #clock-cells = <0>; 36 clock-output-names = "xin24m"; 37 }; 38 39 gpu: gpu@10090000 { 40 compatible = "arm,mali-400"; 41 reg = <0x10090000 0x10000>; 42 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 43 clock-names = "bus", "core"; 44 assigned-clocks = <&cru ACLK_GPU>; 45 assigned-clock-rates = <100000000>; 46 resets = <&cru SRST_GPU>; 47 status = "disabled"; 48 }; 49 50 vpu: video-codec@10104000 { 51 compatible = "rockchip,rk3066-vpu"; 52 reg = <0x10104000 0x800>; 53 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 55 interrupt-names = "vepu", "vdpu"; 56 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, 57 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; 58 clock-names = "aclk_vdpu", "hclk_vdpu", 59 "aclk_vepu", "hclk_vepu"; 60 }; 61 62 L2: cache-controller@10138000 { 63 compatible = "arm,pl310-cache"; 64 reg = <0x10138000 0x1000>; 65 cache-unified; 66 cache-level = <2>; 67 }; 68 69 scu@1013c000 { 70 compatible = "arm,cortex-a9-scu"; 71 reg = <0x1013c000 0x100>; 72 }; 73 74 global_timer: global-timer@1013c200 { 75 compatible = "arm,cortex-a9-global-timer"; 76 reg = <0x1013c200 0x20>; 77 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 78 clocks = <&cru CORE_PERI>; 79 }; 80 81 local_timer: local-timer@1013c600 { 82 compatible = "arm,cortex-a9-twd-timer"; 83 reg = <0x1013c600 0x20>; 84 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 85 clocks = <&cru CORE_PERI>; 86 }; 87 88 gic: interrupt-controller@1013d000 { 89 compatible = "arm,cortex-a9-gic"; 90 interrupt-controller; 91 #interrupt-cells = <3>; 92 reg = <0x1013d000 0x1000>, 93 <0x1013c100 0x0100>; 94 }; 95 96 uart0: serial@10124000 { 97 compatible = "snps,dw-apb-uart"; 98 reg = <0x10124000 0x400>; 99 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 100 reg-shift = <2>; 101 reg-io-width = <1>; 102 clock-names = "baudclk", "apb_pclk"; 103 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 104 status = "disabled"; 105 }; 106 107 uart1: serial@10126000 { 108 compatible = "snps,dw-apb-uart"; 109 reg = <0x10126000 0x400>; 110 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 111 reg-shift = <2>; 112 reg-io-width = <1>; 113 clock-names = "baudclk", "apb_pclk"; 114 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 115 status = "disabled"; 116 }; 117 118 qos_gpu: qos@1012d000 { 119 compatible = "rockchip,rk3066-qos", "syscon"; 120 reg = <0x1012d000 0x20>; 121 }; 122 123 qos_vpu: qos@1012e000 { 124 compatible = "rockchip,rk3066-qos", "syscon"; 125 reg = <0x1012e000 0x20>; 126 }; 127 128 qos_lcdc0: qos@1012f000 { 129 compatible = "rockchip,rk3066-qos", "syscon"; 130 reg = <0x1012f000 0x20>; 131 }; 132 133 qos_cif0: qos@1012f080 { 134 compatible = "rockchip,rk3066-qos", "syscon"; 135 reg = <0x1012f080 0x20>; 136 }; 137 138 qos_ipp: qos@1012f100 { 139 compatible = "rockchip,rk3066-qos", "syscon"; 140 reg = <0x1012f100 0x20>; 141 }; 142 143 qos_lcdc1: qos@1012f180 { 144 compatible = "rockchip,rk3066-qos", "syscon"; 145 reg = <0x1012f180 0x20>; 146 }; 147 148 qos_cif1: qos@1012f200 { 149 compatible = "rockchip,rk3066-qos", "syscon"; 150 reg = <0x1012f200 0x20>; 151 }; 152 153 qos_rga: qos@1012f280 { 154 compatible = "rockchip,rk3066-qos", "syscon"; 155 reg = <0x1012f280 0x20>; 156 }; 157 158 usb_otg: usb@10180000 { 159 compatible = "rockchip,rk3066-usb", "snps,dwc2"; 160 reg = <0x10180000 0x40000>; 161 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&cru HCLK_OTG0>; 163 clock-names = "otg"; 164 dr_mode = "otg"; 165 g-np-tx-fifo-size = <16>; 166 g-rx-fifo-size = <275>; 167 g-tx-fifo-size = <256 128 128 64 64 32>; 168 phys = <&usbphy0>; 169 phy-names = "usb2-phy"; 170 status = "disabled"; 171 }; 172 173 usb_host: usb@101c0000 { 174 compatible = "snps,dwc2"; 175 reg = <0x101c0000 0x40000>; 176 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&cru HCLK_OTG1>; 178 clock-names = "otg"; 179 dr_mode = "host"; 180 phys = <&usbphy1>; 181 phy-names = "usb2-phy"; 182 status = "disabled"; 183 }; 184 185 emac: ethernet@10204000 { 186 compatible = "snps,arc-emac"; 187 reg = <0x10204000 0x3c>; 188 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 192 rockchip,grf = <&grf>; 193 194 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; 195 clock-names = "hclk", "macref"; 196 max-speed = <100>; 197 phy-mode = "rmii"; 198 199 status = "disabled"; 200 }; 201 202 mmc0: mmc@10214000 { 203 compatible = "rockchip,rk2928-dw-mshc"; 204 reg = <0x10214000 0x1000>; 205 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 207 clock-names = "biu", "ciu"; 208 dmas = <&dmac2 1>; 209 dma-names = "rx-tx"; 210 fifo-depth = <256>; 211 resets = <&cru SRST_SDMMC>; 212 reset-names = "reset"; 213 status = "disabled"; 214 }; 215 216 mmc1: mmc@10218000 { 217 compatible = "rockchip,rk2928-dw-mshc"; 218 reg = <0x10218000 0x1000>; 219 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; 221 clock-names = "biu", "ciu"; 222 dmas = <&dmac2 3>; 223 dma-names = "rx-tx"; 224 fifo-depth = <256>; 225 resets = <&cru SRST_SDIO>; 226 reset-names = "reset"; 227 status = "disabled"; 228 }; 229 230 emmc: mmc@1021c000 { 231 compatible = "rockchip,rk2928-dw-mshc"; 232 reg = <0x1021c000 0x1000>; 233 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 235 clock-names = "biu", "ciu"; 236 dmas = <&dmac2 4>; 237 dma-names = "rx-tx"; 238 fifo-depth = <256>; 239 resets = <&cru SRST_EMMC>; 240 reset-names = "reset"; 241 status = "disabled"; 242 }; 243 244 nfc: nand-controller@10500000 { 245 compatible = "rockchip,rk2928-nfc"; 246 reg = <0x10500000 0x4000>; 247 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&cru HCLK_NANDC0>; 249 clock-names = "ahb"; 250 status = "disabled"; 251 }; 252 253 pmu: pmu@20004000 { 254 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; 255 reg = <0x20004000 0x100>; 256 257 reboot-mode { 258 compatible = "syscon-reboot-mode"; 259 offset = <0x40>; 260 mode-normal = <BOOT_NORMAL>; 261 mode-recovery = <BOOT_RECOVERY>; 262 mode-bootloader = <BOOT_FASTBOOT>; 263 mode-loader = <BOOT_BL_DOWNLOAD>; 264 }; 265 }; 266 267 grf: grf@20008000 { 268 compatible = "syscon", "simple-mfd"; 269 reg = <0x20008000 0x200>; 270 }; 271 272 dmac1_s: dma-controller@20018000 { 273 compatible = "arm,pl330", "arm,primecell"; 274 reg = <0x20018000 0x4000>; 275 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 277 #dma-cells = <1>; 278 arm,pl330-broken-no-flushp; 279 arm,pl330-periph-burst; 280 clocks = <&cru ACLK_DMA1>; 281 clock-names = "apb_pclk"; 282 }; 283 284 dmac1_ns: dma-controller@2001c000 { 285 compatible = "arm,pl330", "arm,primecell"; 286 reg = <0x2001c000 0x4000>; 287 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 289 #dma-cells = <1>; 290 arm,pl330-broken-no-flushp; 291 arm,pl330-periph-burst; 292 clocks = <&cru ACLK_DMA1>; 293 clock-names = "apb_pclk"; 294 status = "disabled"; 295 }; 296 297 i2c0: i2c@2002d000 { 298 compatible = "rockchip,rk3066-i2c"; 299 reg = <0x2002d000 0x1000>; 300 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 304 rockchip,grf = <&grf>; 305 306 clock-names = "i2c"; 307 clocks = <&cru PCLK_I2C0>; 308 309 status = "disabled"; 310 }; 311 312 i2c1: i2c@2002f000 { 313 compatible = "rockchip,rk3066-i2c"; 314 reg = <0x2002f000 0x1000>; 315 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 319 rockchip,grf = <&grf>; 320 321 clocks = <&cru PCLK_I2C1>; 322 clock-names = "i2c"; 323 324 status = "disabled"; 325 }; 326 327 pwm0: pwm@20030000 { 328 compatible = "rockchip,rk2928-pwm"; 329 reg = <0x20030000 0x10>; 330 #pwm-cells = <2>; 331 clocks = <&cru PCLK_PWM01>; 332 status = "disabled"; 333 }; 334 335 pwm1: pwm@20030010 { 336 compatible = "rockchip,rk2928-pwm"; 337 reg = <0x20030010 0x10>; 338 #pwm-cells = <2>; 339 clocks = <&cru PCLK_PWM01>; 340 status = "disabled"; 341 }; 342 343 wdt: watchdog@2004c000 { 344 compatible = "snps,dw-wdt"; 345 reg = <0x2004c000 0x100>; 346 clocks = <&cru PCLK_WDT>; 347 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 348 status = "disabled"; 349 }; 350 351 pwm2: pwm@20050020 { 352 compatible = "rockchip,rk2928-pwm"; 353 reg = <0x20050020 0x10>; 354 #pwm-cells = <2>; 355 clocks = <&cru PCLK_PWM23>; 356 status = "disabled"; 357 }; 358 359 pwm3: pwm@20050030 { 360 compatible = "rockchip,rk2928-pwm"; 361 reg = <0x20050030 0x10>; 362 #pwm-cells = <2>; 363 clocks = <&cru PCLK_PWM23>; 364 status = "disabled"; 365 }; 366 367 i2c2: i2c@20056000 { 368 compatible = "rockchip,rk3066-i2c"; 369 reg = <0x20056000 0x1000>; 370 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 374 rockchip,grf = <&grf>; 375 376 clocks = <&cru PCLK_I2C2>; 377 clock-names = "i2c"; 378 379 status = "disabled"; 380 }; 381 382 i2c3: i2c@2005a000 { 383 compatible = "rockchip,rk3066-i2c"; 384 reg = <0x2005a000 0x1000>; 385 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 389 rockchip,grf = <&grf>; 390 391 clocks = <&cru PCLK_I2C3>; 392 clock-names = "i2c"; 393 394 status = "disabled"; 395 }; 396 397 i2c4: i2c@2005e000 { 398 compatible = "rockchip,rk3066-i2c"; 399 reg = <0x2005e000 0x1000>; 400 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 404 rockchip,grf = <&grf>; 405 406 clocks = <&cru PCLK_I2C4>; 407 clock-names = "i2c"; 408 409 status = "disabled"; 410 }; 411 412 uart2: serial@20064000 { 413 compatible = "snps,dw-apb-uart"; 414 reg = <0x20064000 0x400>; 415 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 416 reg-shift = <2>; 417 reg-io-width = <1>; 418 clock-names = "baudclk", "apb_pclk"; 419 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 420 status = "disabled"; 421 }; 422 423 uart3: serial@20068000 { 424 compatible = "snps,dw-apb-uart"; 425 reg = <0x20068000 0x400>; 426 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 427 reg-shift = <2>; 428 reg-io-width = <1>; 429 clock-names = "baudclk", "apb_pclk"; 430 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 431 status = "disabled"; 432 }; 433 434 saradc: saradc@2006c000 { 435 compatible = "rockchip,saradc"; 436 reg = <0x2006c000 0x100>; 437 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 438 #io-channel-cells = <1>; 439 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 440 clock-names = "saradc", "apb_pclk"; 441 resets = <&cru SRST_SARADC>; 442 reset-names = "saradc-apb"; 443 status = "disabled"; 444 }; 445 446 spi0: spi@20070000 { 447 compatible = "rockchip,rk3066-spi"; 448 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 449 clock-names = "spiclk", "apb_pclk"; 450 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 451 reg = <0x20070000 0x1000>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 dmas = <&dmac2 10>, <&dmac2 11>; 455 dma-names = "tx", "rx"; 456 status = "disabled"; 457 }; 458 459 spi1: spi@20074000 { 460 compatible = "rockchip,rk3066-spi"; 461 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 462 clock-names = "spiclk", "apb_pclk"; 463 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 464 reg = <0x20074000 0x1000>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 dmas = <&dmac2 12>, <&dmac2 13>; 468 dma-names = "tx", "rx"; 469 status = "disabled"; 470 }; 471 472 dmac2: dma-controller@20078000 { 473 compatible = "arm,pl330", "arm,primecell"; 474 reg = <0x20078000 0x4000>; 475 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 477 #dma-cells = <1>; 478 arm,pl330-broken-no-flushp; 479 arm,pl330-periph-burst; 480 clocks = <&cru ACLK_DMA2>; 481 clock-names = "apb_pclk"; 482 }; 483 };
Cache object: 63eac10963e8d48825b76be6d86df9b4
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