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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9 #include <dt-bindings/dma/at91.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 11 #include <dt-bindings/clock/at91.h> 12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 13 14 / { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Atmel SAMA5D2 family SoC"; 18 compatible = "atmel,sama5d2"; 19 interrupt-parent = <&aic>; 20 21 aliases { 22 serial0 = &uart1; 23 serial1 = &uart3; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a5"; 33 reg = <0>; 34 next-level-cache = <&L2>; 35 }; 36 }; 37 38 pmu { 39 compatible = "arm,cortex-a5-pmu"; 40 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; 41 }; 42 43 etb@740000 { 44 compatible = "arm,coresight-etb10", "arm,primecell"; 45 reg = <0x740000 0x1000>; 46 47 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 48 clock-names = "apb_pclk"; 49 50 in-ports { 51 port { 52 etb_in: endpoint { 53 remote-endpoint = <&etm_out>; 54 }; 55 }; 56 }; 57 }; 58 59 etm@73c000 { 60 compatible = "arm,coresight-etm3x", "arm,primecell"; 61 reg = <0x73c000 0x1000>; 62 63 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 64 clock-names = "apb_pclk"; 65 66 out-ports { 67 port { 68 etm_out: endpoint { 69 remote-endpoint = <&etb_in>; 70 }; 71 }; 72 }; 73 }; 74 75 memory@20000000 { 76 device_type = "memory"; 77 reg = <0x20000000 0x20000000>; 78 }; 79 80 clocks { 81 slow_xtal: slow_xtal { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <0>; 85 }; 86 87 main_xtal: main_xtal { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <0>; 91 }; 92 }; 93 94 ns_sram: sram@200000 { 95 compatible = "mmio-sram"; 96 reg = <0x00200000 0x20000>; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 ranges = <0 0x00200000 0x20000>; 100 }; 101 102 resistive_touch: resistive-touch { 103 compatible = "resistive-adc-touch"; 104 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, 105 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, 106 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; 107 io-channel-names = "x", "y", "pressure"; 108 touchscreen-min-pressure = <50000>; 109 status = "disabled"; 110 }; 111 112 ahb { 113 compatible = "simple-bus"; 114 #address-cells = <1>; 115 #size-cells = <1>; 116 ranges; 117 118 nfc_sram: sram@100000 { 119 compatible = "mmio-sram"; 120 no-memory-wc; 121 reg = <0x00100000 0x2400>; 122 #address-cells = <1>; 123 #size-cells = <1>; 124 ranges = <0 0x00100000 0x2400>; 125 126 }; 127 128 usb0: gadget@300000 { 129 compatible = "atmel,sama5d3-udc"; 130 reg = <0x00300000 0x100000 131 0xfc02c000 0x400>; 132 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; 133 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 134 clock-names = "pclk", "hclk"; 135 status = "disabled"; 136 }; 137 138 usb1: ohci@400000 { 139 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 140 reg = <0x00400000 0x100000>; 141 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 142 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; 143 clock-names = "ohci_clk", "hclk", "uhpck"; 144 status = "disabled"; 145 }; 146 147 usb2: ehci@500000 { 148 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 149 reg = <0x00500000 0x100000>; 150 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 151 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; 152 clock-names = "usb_clk", "ehci_clk"; 153 status = "disabled"; 154 }; 155 156 L2: cache-controller@a00000 { 157 compatible = "arm,pl310-cache"; 158 reg = <0x00a00000 0x1000>; 159 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; 160 cache-unified; 161 cache-level = <2>; 162 }; 163 164 ebi: ebi@10000000 { 165 compatible = "atmel,sama5d3-ebi"; 166 #address-cells = <2>; 167 #size-cells = <1>; 168 atmel,smc = <&hsmc>; 169 reg = <0x10000000 0x10000000 170 0x60000000 0x30000000>; 171 ranges = <0x0 0x0 0x10000000 0x10000000 172 0x1 0x0 0x60000000 0x10000000 173 0x2 0x0 0x70000000 0x10000000 174 0x3 0x0 0x80000000 0x10000000>; 175 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 176 status = "disabled"; 177 178 nand_controller: nand-controller { 179 compatible = "atmel,sama5d3-nand-controller"; 180 atmel,nfc-sram = <&nfc_sram>; 181 atmel,nfc-io = <&nfc_io>; 182 ecc-engine = <&pmecc>; 183 #address-cells = <2>; 184 #size-cells = <1>; 185 ranges; 186 status = "disabled"; 187 }; 188 }; 189 190 sdmmc0: sdio-host@a0000000 { 191 compatible = "atmel,sama5d2-sdhci"; 192 reg = <0xa0000000 0x300>; 193 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 194 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 195 clock-names = "hclock", "multclk", "baseclk"; 196 assigned-clocks = <&pmc PMC_TYPE_GCK 31>; 197 assigned-clock-rates = <480000000>; 198 status = "disabled"; 199 }; 200 201 sdmmc1: sdio-host@b0000000 { 202 compatible = "atmel,sama5d2-sdhci"; 203 reg = <0xb0000000 0x300>; 204 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; 205 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 206 clock-names = "hclock", "multclk", "baseclk"; 207 assigned-clocks = <&pmc PMC_TYPE_GCK 32>; 208 assigned-clock-rates = <480000000>; 209 status = "disabled"; 210 }; 211 212 nfc_io: nfc-io@c0000000 { 213 compatible = "atmel,sama5d3-nfc-io", "syscon"; 214 reg = <0xc0000000 0x8000000>; 215 }; 216 217 apb { 218 compatible = "simple-bus"; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 ranges; 222 223 hlcdc: hlcdc@f0000000 { 224 compatible = "atmel,sama5d2-hlcdc"; 225 reg = <0xf0000000 0x2000>; 226 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 227 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 228 clock-names = "periph_clk","sys_clk", "slow_clk"; 229 status = "disabled"; 230 231 hlcdc-display-controller { 232 compatible = "atmel,hlcdc-display-controller"; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 236 port@0 { 237 #address-cells = <1>; 238 #size-cells = <0>; 239 reg = <0>; 240 }; 241 }; 242 243 hlcdc_pwm: hlcdc-pwm { 244 compatible = "atmel,hlcdc-pwm"; 245 #pwm-cells = <3>; 246 }; 247 }; 248 249 isc: isc@f0008000 { 250 compatible = "atmel,sama5d2-isc"; 251 reg = <0xf0008000 0x4000>; 252 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; 253 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; 254 clock-names = "hclock", "iscck", "gck"; 255 #clock-cells = <0>; 256 clock-output-names = "isc-mck"; 257 status = "disabled"; 258 }; 259 260 ramc0: ramc@f000c000 { 261 compatible = "atmel,sama5d3-ddramc"; 262 reg = <0xf000c000 0x200>; 263 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; 264 clock-names = "ddrck", "mpddr"; 265 }; 266 267 dma0: dma-controller@f0010000 { 268 compatible = "atmel,sama5d4-dma"; 269 reg = <0xf0010000 0x1000>; 270 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 271 #dma-cells = <1>; 272 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 273 clock-names = "dma_clk"; 274 }; 275 276 /* Place dma1 here despite its address */ 277 dma1: dma-controller@f0004000 { 278 compatible = "atmel,sama5d4-dma"; 279 reg = <0xf0004000 0x1000>; 280 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; 281 #dma-cells = <1>; 282 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 283 clock-names = "dma_clk"; 284 }; 285 286 pmc: pmc@f0014000 { 287 compatible = "atmel,sama5d2-pmc", "syscon"; 288 reg = <0xf0014000 0x160>; 289 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 290 #clock-cells = <2>; 291 clocks = <&clk32k>, <&main_xtal>; 292 clock-names = "slow_clk", "main_xtal"; 293 }; 294 295 qspi0: spi@f0020000 { 296 compatible = "atmel,sama5d2-qspi"; 297 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; 298 reg-names = "qspi_base", "qspi_mmap"; 299 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; 300 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 301 clock-names = "pclk"; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 status = "disabled"; 305 }; 306 307 qspi1: spi@f0024000 { 308 compatible = "atmel,sama5d2-qspi"; 309 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; 310 reg-names = "qspi_base", "qspi_mmap"; 311 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; 312 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; 313 clock-names = "pclk"; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 status = "disabled"; 317 }; 318 319 sha: crypto@f0028000 { 320 compatible = "atmel,at91sam9g46-sha"; 321 reg = <0xf0028000 0x100>; 322 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 323 dmas = <&dma0 324 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 325 AT91_XDMAC_DT_PERID(30))>; 326 dma-names = "tx"; 327 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 328 clock-names = "sha_clk"; 329 }; 330 331 aes: crypto@f002c000 { 332 compatible = "atmel,at91sam9g46-aes"; 333 reg = <0xf002c000 0x100>; 334 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 335 dmas = <&dma0 336 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 337 AT91_XDMAC_DT_PERID(26))>, 338 <&dma0 339 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 340 AT91_XDMAC_DT_PERID(27))>; 341 dma-names = "tx", "rx"; 342 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 343 clock-names = "aes_clk"; 344 }; 345 346 spi0: spi@f8000000 { 347 compatible = "atmel,at91rm9200-spi"; 348 reg = <0xf8000000 0x100>; 349 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 350 dmas = <&dma0 351 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 352 AT91_XDMAC_DT_PERID(6))>, 353 <&dma0 354 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 355 AT91_XDMAC_DT_PERID(7))>; 356 dma-names = "tx", "rx"; 357 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 358 clock-names = "spi_clk"; 359 atmel,fifo-size = <16>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 status = "disabled"; 363 }; 364 365 ssc0: ssc@f8004000 { 366 compatible = "atmel,at91sam9g45-ssc"; 367 reg = <0xf8004000 0x4000>; 368 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 369 dmas = <&dma0 370 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 371 AT91_XDMAC_DT_PERID(21))>, 372 <&dma0 373 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 374 AT91_XDMAC_DT_PERID(22))>; 375 dma-names = "tx", "rx"; 376 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 377 clock-names = "pclk"; 378 status = "disabled"; 379 }; 380 381 macb0: ethernet@f8008000 { 382 compatible = "atmel,sama5d2-gem"; 383 reg = <0xf8008000 0x1000>; 384 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ 385 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ 386 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ 387 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; 388 clock-names = "hclk", "pclk"; 389 status = "disabled"; 390 }; 391 392 tcb0: timer@f800c000 { 393 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 reg = <0xf800c000 0x100>; 397 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 398 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; 399 clock-names = "t0_clk", "gclk", "slow_clk"; 400 }; 401 402 tcb1: timer@f8010000 { 403 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 reg = <0xf8010000 0x100>; 407 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 408 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; 409 clock-names = "t0_clk", "gclk", "slow_clk"; 410 }; 411 412 hsmc: hsmc@f8014000 { 413 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 414 reg = <0xf8014000 0x1000>; 415 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; 416 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 417 #address-cells = <1>; 418 #size-cells = <1>; 419 ranges; 420 421 pmecc: ecc-engine@f8014070 { 422 compatible = "atmel,sama5d2-pmecc"; 423 reg = <0xf8014070 0x490>, 424 <0xf8014500 0x200>; 425 }; 426 }; 427 428 pdmic: pdmic@f8018000 { 429 compatible = "atmel,sama5d2-pdmic"; 430 reg = <0xf8018000 0x124>; 431 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; 432 dmas = <&dma0 433 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 434 | AT91_XDMAC_DT_PERID(50))>; 435 dma-names = "rx"; 436 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; 437 clock-names = "pclk", "gclk"; 438 status = "disabled"; 439 }; 440 441 uart0: serial@f801c000 { 442 compatible = "atmel,at91sam9260-usart"; 443 reg = <0xf801c000 0x100>; 444 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; 445 dmas = <&dma0 446 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 447 AT91_XDMAC_DT_PERID(35))>, 448 <&dma0 449 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 450 AT91_XDMAC_DT_PERID(36))>; 451 dma-names = "tx", "rx"; 452 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 453 clock-names = "usart"; 454 status = "disabled"; 455 }; 456 457 uart1: serial@f8020000 { 458 compatible = "atmel,at91sam9260-usart"; 459 reg = <0xf8020000 0x100>; 460 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; 461 dmas = <&dma0 462 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 463 AT91_XDMAC_DT_PERID(37))>, 464 <&dma0 465 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 466 AT91_XDMAC_DT_PERID(38))>; 467 dma-names = "tx", "rx"; 468 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 469 clock-names = "usart"; 470 status = "disabled"; 471 }; 472 473 uart2: serial@f8024000 { 474 compatible = "atmel,at91sam9260-usart"; 475 reg = <0xf8024000 0x100>; 476 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; 477 dmas = <&dma0 478 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 479 AT91_XDMAC_DT_PERID(39))>, 480 <&dma0 481 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 482 AT91_XDMAC_DT_PERID(40))>; 483 dma-names = "tx", "rx"; 484 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 485 clock-names = "usart"; 486 status = "disabled"; 487 }; 488 489 i2c0: i2c@f8028000 { 490 compatible = "atmel,sama5d2-i2c"; 491 reg = <0xf8028000 0x100>; 492 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; 493 dmas = <&dma0 494 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 495 AT91_XDMAC_DT_PERID(0))>, 496 <&dma0 497 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 498 AT91_XDMAC_DT_PERID(1))>; 499 dma-names = "tx", "rx"; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 503 atmel,fifo-size = <16>; 504 status = "disabled"; 505 }; 506 507 pwm0: pwm@f802c000 { 508 compatible = "atmel,sama5d2-pwm"; 509 reg = <0xf802c000 0x4000>; 510 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; 511 #pwm-cells = <3>; 512 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 513 status = "disabled"; 514 }; 515 516 sfr: sfr@f8030000 { 517 compatible = "atmel,sama5d2-sfr", "syscon"; 518 reg = <0xf8030000 0x98>; 519 }; 520 521 flx0: flexcom@f8034000 { 522 compatible = "atmel,sama5d2-flexcom"; 523 reg = <0xf8034000 0x200>; 524 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 525 #address-cells = <1>; 526 #size-cells = <1>; 527 ranges = <0x0 0xf8034000 0x800>; 528 status = "disabled"; 529 530 uart5: serial@200 { 531 compatible = "atmel,at91sam9260-usart"; 532 reg = <0x200 0x200>; 533 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 534 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 535 clock-names = "usart"; 536 dmas = <&dma0 537 (AT91_XDMAC_DT_MEM_IF(0) | 538 AT91_XDMAC_DT_PER_IF(1) | 539 AT91_XDMAC_DT_PERID(11))>, 540 <&dma0 541 (AT91_XDMAC_DT_MEM_IF(0) | 542 AT91_XDMAC_DT_PER_IF(1) | 543 AT91_XDMAC_DT_PERID(12))>; 544 dma-names = "tx", "rx"; 545 atmel,fifo-size = <32>; 546 status = "disabled"; 547 }; 548 549 spi2: spi@400 { 550 compatible = "atmel,at91rm9200-spi"; 551 reg = <0x400 0x200>; 552 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 556 clock-names = "spi_clk"; 557 dmas = <&dma0 558 (AT91_XDMAC_DT_MEM_IF(0) | 559 AT91_XDMAC_DT_PER_IF(1) | 560 AT91_XDMAC_DT_PERID(11))>, 561 <&dma0 562 (AT91_XDMAC_DT_MEM_IF(0) | 563 AT91_XDMAC_DT_PER_IF(1) | 564 AT91_XDMAC_DT_PERID(12))>; 565 dma-names = "tx", "rx"; 566 atmel,fifo-size = <16>; 567 status = "disabled"; 568 }; 569 570 i2c2: i2c@600 { 571 compatible = "atmel,sama5d2-i2c"; 572 reg = <0x600 0x200>; 573 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 577 dmas = <&dma0 578 (AT91_XDMAC_DT_MEM_IF(0) | 579 AT91_XDMAC_DT_PER_IF(1) | 580 AT91_XDMAC_DT_PERID(11))>, 581 <&dma0 582 (AT91_XDMAC_DT_MEM_IF(0) | 583 AT91_XDMAC_DT_PER_IF(1) | 584 AT91_XDMAC_DT_PERID(12))>; 585 dma-names = "tx", "rx"; 586 atmel,fifo-size = <16>; 587 status = "disabled"; 588 }; 589 }; 590 591 flx1: flexcom@f8038000 { 592 compatible = "atmel,sama5d2-flexcom"; 593 reg = <0xf8038000 0x200>; 594 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 595 #address-cells = <1>; 596 #size-cells = <1>; 597 ranges = <0x0 0xf8038000 0x800>; 598 status = "disabled"; 599 600 uart6: serial@200 { 601 compatible = "atmel,at91sam9260-usart"; 602 reg = <0x200 0x200>; 603 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 604 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 605 clock-names = "usart"; 606 dmas = <&dma0 607 (AT91_XDMAC_DT_MEM_IF(0) | 608 AT91_XDMAC_DT_PER_IF(1) | 609 AT91_XDMAC_DT_PERID(13))>, 610 <&dma0 611 (AT91_XDMAC_DT_MEM_IF(0) | 612 AT91_XDMAC_DT_PER_IF(1) | 613 AT91_XDMAC_DT_PERID(14))>; 614 dma-names = "tx", "rx"; 615 atmel,fifo-size = <32>; 616 status = "disabled"; 617 }; 618 619 spi3: spi@400 { 620 compatible = "atmel,at91rm9200-spi"; 621 reg = <0x400 0x200>; 622 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 626 clock-names = "spi_clk"; 627 dmas = <&dma0 628 (AT91_XDMAC_DT_MEM_IF(0) | 629 AT91_XDMAC_DT_PER_IF(1) | 630 AT91_XDMAC_DT_PERID(13))>, 631 <&dma0 632 (AT91_XDMAC_DT_MEM_IF(0) | 633 AT91_XDMAC_DT_PER_IF(1) | 634 AT91_XDMAC_DT_PERID(14))>; 635 dma-names = "tx", "rx"; 636 atmel,fifo-size = <16>; 637 status = "disabled"; 638 }; 639 640 i2c3: i2c@600 { 641 compatible = "atmel,sama5d2-i2c"; 642 reg = <0x600 0x200>; 643 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 644 #address-cells = <1>; 645 #size-cells = <0>; 646 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 647 dmas = <&dma0 648 (AT91_XDMAC_DT_MEM_IF(0) | 649 AT91_XDMAC_DT_PER_IF(1) | 650 AT91_XDMAC_DT_PERID(13))>, 651 <&dma0 652 (AT91_XDMAC_DT_MEM_IF(0) | 653 AT91_XDMAC_DT_PER_IF(1) | 654 AT91_XDMAC_DT_PERID(14))>; 655 dma-names = "tx", "rx"; 656 atmel,fifo-size = <16>; 657 status = "disabled"; 658 }; 659 }; 660 661 securam: sram@f8044000 { 662 compatible = "atmel,sama5d2-securam", "mmio-sram"; 663 reg = <0xf8044000 0x1420>; 664 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; 665 #address-cells = <1>; 666 #size-cells = <1>; 667 no-memory-wc; 668 ranges = <0 0xf8044000 0x1420>; 669 }; 670 671 reset_controller: reset-controller@f8048000 { 672 compatible = "atmel,sama5d3-rstc"; 673 reg = <0xf8048000 0x10>; 674 clocks = <&clk32k>; 675 }; 676 677 shutdown_controller: shdwc@f8048010 { 678 compatible = "atmel,sama5d2-shdwc"; 679 reg = <0xf8048010 0x10>; 680 clocks = <&clk32k>; 681 #address-cells = <1>; 682 #size-cells = <0>; 683 atmel,wakeup-rtc-timer; 684 }; 685 686 pit: timer@f8048030 { 687 compatible = "atmel,at91sam9260-pit"; 688 reg = <0xf8048030 0x10>; 689 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 690 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 691 }; 692 693 watchdog: watchdog@f8048040 { 694 compatible = "atmel,sama5d4-wdt"; 695 reg = <0xf8048040 0x10>; 696 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 697 clocks = <&clk32k>; 698 status = "disabled"; 699 }; 700 701 clk32k: sckc@f8048050 { 702 compatible = "atmel,sama5d4-sckc"; 703 reg = <0xf8048050 0x4>; 704 705 clocks = <&slow_xtal>; 706 #clock-cells = <0>; 707 }; 708 709 rtc: rtc@f80480b0 { 710 compatible = "atmel,sama5d2-rtc"; 711 reg = <0xf80480b0 0x30>; 712 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 713 clocks = <&clk32k>; 714 }; 715 716 i2s0: i2s@f8050000 { 717 compatible = "atmel,sama5d2-i2s"; 718 reg = <0xf8050000 0x100>; 719 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; 720 dmas = <&dma0 721 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 722 AT91_XDMAC_DT_PERID(31))>, 723 <&dma0 724 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 725 AT91_XDMAC_DT_PERID(32))>; 726 dma-names = "tx", "rx"; 727 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; 728 clock-names = "pclk", "gclk"; 729 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; 730 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; 731 status = "disabled"; 732 }; 733 734 can0: can@f8054000 { 735 compatible = "bosch,m_can"; 736 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; 737 reg-names = "m_can", "message_ram"; 738 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, 739 <64 IRQ_TYPE_LEVEL_HIGH 7>; 740 interrupt-names = "int0", "int1"; 741 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; 742 clock-names = "hclk", "cclk"; 743 assigned-clocks = <&pmc PMC_TYPE_GCK 56>; 744 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 745 assigned-clock-rates = <40000000>; 746 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 747 status = "disabled"; 748 }; 749 750 spi1: spi@fc000000 { 751 compatible = "atmel,at91rm9200-spi"; 752 reg = <0xfc000000 0x100>; 753 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 754 dmas = <&dma0 755 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 756 AT91_XDMAC_DT_PERID(8))>, 757 <&dma0 758 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 759 AT91_XDMAC_DT_PERID(9))>; 760 dma-names = "tx", "rx"; 761 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 762 clock-names = "spi_clk"; 763 atmel,fifo-size = <16>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 status = "disabled"; 767 }; 768 769 uart3: serial@fc008000 { 770 compatible = "atmel,at91sam9260-usart"; 771 reg = <0xfc008000 0x100>; 772 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; 773 dmas = <&dma1 774 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 775 AT91_XDMAC_DT_PERID(41))>, 776 <&dma1 777 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 778 AT91_XDMAC_DT_PERID(42))>; 779 dma-names = "tx", "rx"; 780 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 781 clock-names = "usart"; 782 status = "disabled"; 783 }; 784 785 uart4: serial@fc00c000 { 786 compatible = "atmel,at91sam9260-usart"; 787 reg = <0xfc00c000 0x100>; 788 dmas = <&dma0 789 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 790 AT91_XDMAC_DT_PERID(43))>, 791 <&dma0 792 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 793 AT91_XDMAC_DT_PERID(44))>; 794 dma-names = "tx", "rx"; 795 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; 796 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 797 clock-names = "usart"; 798 status = "disabled"; 799 }; 800 801 flx2: flexcom@fc010000 { 802 compatible = "atmel,sama5d2-flexcom"; 803 reg = <0xfc010000 0x200>; 804 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 805 #address-cells = <1>; 806 #size-cells = <1>; 807 ranges = <0x0 0xfc010000 0x800>; 808 status = "disabled"; 809 810 uart7: serial@200 { 811 compatible = "atmel,at91sam9260-usart"; 812 reg = <0x200 0x200>; 813 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 814 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 815 clock-names = "usart"; 816 dmas = <&dma0 817 (AT91_XDMAC_DT_MEM_IF(0) | 818 AT91_XDMAC_DT_PER_IF(1) | 819 AT91_XDMAC_DT_PERID(15))>, 820 <&dma0 821 (AT91_XDMAC_DT_MEM_IF(0) | 822 AT91_XDMAC_DT_PER_IF(1) | 823 AT91_XDMAC_DT_PERID(16))>; 824 dma-names = "tx", "rx"; 825 atmel,fifo-size = <32>; 826 status = "disabled"; 827 }; 828 829 spi4: spi@400 { 830 compatible = "atmel,at91rm9200-spi"; 831 reg = <0x400 0x200>; 832 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 836 clock-names = "spi_clk"; 837 dmas = <&dma0 838 (AT91_XDMAC_DT_MEM_IF(0) | 839 AT91_XDMAC_DT_PER_IF(1) | 840 AT91_XDMAC_DT_PERID(15))>, 841 <&dma0 842 (AT91_XDMAC_DT_MEM_IF(0) | 843 AT91_XDMAC_DT_PER_IF(1) | 844 AT91_XDMAC_DT_PERID(16))>; 845 dma-names = "tx", "rx"; 846 atmel,fifo-size = <16>; 847 status = "disabled"; 848 }; 849 850 i2c4: i2c@600 { 851 compatible = "atmel,sama5d2-i2c"; 852 reg = <0x600 0x200>; 853 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 857 dmas = <&dma0 858 (AT91_XDMAC_DT_MEM_IF(0) | 859 AT91_XDMAC_DT_PER_IF(1) | 860 AT91_XDMAC_DT_PERID(15))>, 861 <&dma0 862 (AT91_XDMAC_DT_MEM_IF(0) | 863 AT91_XDMAC_DT_PER_IF(1) | 864 AT91_XDMAC_DT_PERID(16))>; 865 dma-names = "tx", "rx"; 866 atmel,fifo-size = <16>; 867 status = "disabled"; 868 }; 869 }; 870 871 flx3: flexcom@fc014000 { 872 compatible = "atmel,sama5d2-flexcom"; 873 reg = <0xfc014000 0x200>; 874 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 875 #address-cells = <1>; 876 #size-cells = <1>; 877 ranges = <0x0 0xfc014000 0x800>; 878 status = "disabled"; 879 880 uart8: serial@200 { 881 compatible = "atmel,at91sam9260-usart"; 882 reg = <0x200 0x200>; 883 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 884 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 885 clock-names = "usart"; 886 dmas = <&dma0 887 (AT91_XDMAC_DT_MEM_IF(0) | 888 AT91_XDMAC_DT_PER_IF(1) | 889 AT91_XDMAC_DT_PERID(17))>, 890 <&dma0 891 (AT91_XDMAC_DT_MEM_IF(0) | 892 AT91_XDMAC_DT_PER_IF(1) | 893 AT91_XDMAC_DT_PERID(18))>; 894 dma-names = "tx", "rx"; 895 atmel,fifo-size = <32>; 896 status = "disabled"; 897 }; 898 899 spi5: spi@400 { 900 compatible = "atmel,at91rm9200-spi"; 901 reg = <0x400 0x200>; 902 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 903 #address-cells = <1>; 904 #size-cells = <0>; 905 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 906 clock-names = "spi_clk"; 907 dmas = <&dma0 908 (AT91_XDMAC_DT_MEM_IF(0) | 909 AT91_XDMAC_DT_PER_IF(1) | 910 AT91_XDMAC_DT_PERID(17))>, 911 <&dma0 912 (AT91_XDMAC_DT_MEM_IF(0) | 913 AT91_XDMAC_DT_PER_IF(1) | 914 AT91_XDMAC_DT_PERID(18))>; 915 dma-names = "tx", "rx"; 916 atmel,fifo-size = <16>; 917 status = "disabled"; 918 }; 919 920 i2c5: i2c@600 { 921 compatible = "atmel,sama5d2-i2c"; 922 reg = <0x600 0x200>; 923 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 927 dmas = <&dma0 928 (AT91_XDMAC_DT_MEM_IF(0) | 929 AT91_XDMAC_DT_PER_IF(1) | 930 AT91_XDMAC_DT_PERID(17))>, 931 <&dma0 932 (AT91_XDMAC_DT_MEM_IF(0) | 933 AT91_XDMAC_DT_PER_IF(1) | 934 AT91_XDMAC_DT_PERID(18))>; 935 dma-names = "tx", "rx"; 936 atmel,fifo-size = <16>; 937 status = "disabled"; 938 }; 939 940 }; 941 942 flx4: flexcom@fc018000 { 943 compatible = "atmel,sama5d2-flexcom"; 944 reg = <0xfc018000 0x200>; 945 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 946 #address-cells = <1>; 947 #size-cells = <1>; 948 ranges = <0x0 0xfc018000 0x800>; 949 status = "disabled"; 950 951 uart9: serial@200 { 952 compatible = "atmel,at91sam9260-usart"; 953 reg = <0x200 0x200>; 954 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 955 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 956 clock-names = "usart"; 957 dmas = <&dma0 958 (AT91_XDMAC_DT_MEM_IF(0) | 959 AT91_XDMAC_DT_PER_IF(1) | 960 AT91_XDMAC_DT_PERID(19))>, 961 <&dma0 962 (AT91_XDMAC_DT_MEM_IF(0) | 963 AT91_XDMAC_DT_PER_IF(1) | 964 AT91_XDMAC_DT_PERID(20))>; 965 dma-names = "tx", "rx"; 966 atmel,fifo-size = <32>; 967 status = "disabled"; 968 }; 969 970 spi6: spi@400 { 971 compatible = "atmel,at91rm9200-spi"; 972 reg = <0x400 0x200>; 973 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 977 clock-names = "spi_clk"; 978 dmas = <&dma0 979 (AT91_XDMAC_DT_MEM_IF(0) | 980 AT91_XDMAC_DT_PER_IF(1) | 981 AT91_XDMAC_DT_PERID(19))>, 982 <&dma0 983 (AT91_XDMAC_DT_MEM_IF(0) | 984 AT91_XDMAC_DT_PER_IF(1) | 985 AT91_XDMAC_DT_PERID(20))>; 986 dma-names = "tx", "rx"; 987 atmel,fifo-size = <16>; 988 status = "disabled"; 989 }; 990 991 i2c6: i2c@600 { 992 compatible = "atmel,sama5d2-i2c"; 993 reg = <0x600 0x200>; 994 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 998 dmas = <&dma0 999 (AT91_XDMAC_DT_MEM_IF(0) | 1000 AT91_XDMAC_DT_PER_IF(1) | 1001 AT91_XDMAC_DT_PERID(19))>, 1002 <&dma0 1003 (AT91_XDMAC_DT_MEM_IF(0) | 1004 AT91_XDMAC_DT_PER_IF(1) | 1005 AT91_XDMAC_DT_PERID(20))>; 1006 dma-names = "tx", "rx"; 1007 atmel,fifo-size = <16>; 1008 status = "disabled"; 1009 }; 1010 }; 1011 1012 trng@fc01c000 { 1013 compatible = "atmel,at91sam9g45-trng"; 1014 reg = <0xfc01c000 0x100>; 1015 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; 1016 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1017 }; 1018 1019 aic: interrupt-controller@fc020000 { 1020 #interrupt-cells = <3>; 1021 compatible = "atmel,sama5d2-aic"; 1022 interrupt-controller; 1023 reg = <0xfc020000 0x200>; 1024 atmel,external-irqs = <49>; 1025 }; 1026 1027 i2c1: i2c@fc028000 { 1028 compatible = "atmel,sama5d2-i2c"; 1029 reg = <0xfc028000 0x100>; 1030 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; 1031 dmas = <&dma0 1032 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1033 AT91_XDMAC_DT_PERID(2))>, 1034 <&dma0 1035 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1036 AT91_XDMAC_DT_PERID(3))>; 1037 dma-names = "tx", "rx"; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 1041 atmel,fifo-size = <16>; 1042 status = "disabled"; 1043 }; 1044 1045 adc: adc@fc030000 { 1046 compatible = "atmel,sama5d2-adc"; 1047 reg = <0xfc030000 0x100>; 1048 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; 1049 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 1050 clock-names = "adc_clk"; 1051 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; 1052 dma-names = "rx"; 1053 atmel,min-sample-rate-hz = <200000>; 1054 atmel,max-sample-rate-hz = <20000000>; 1055 atmel,startup-time-ms = <4>; 1056 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 1057 #io-channel-cells = <1>; 1058 status = "disabled"; 1059 }; 1060 1061 pioA: pinctrl@fc038000 { 1062 compatible = "atmel,sama5d2-pinctrl"; 1063 reg = <0xfc038000 0x600>; 1064 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, 1065 <68 IRQ_TYPE_LEVEL_HIGH 7>, 1066 <69 IRQ_TYPE_LEVEL_HIGH 7>, 1067 <70 IRQ_TYPE_LEVEL_HIGH 7>; 1068 interrupt-controller; 1069 #interrupt-cells = <2>; 1070 gpio-controller; 1071 #gpio-cells = <2>; 1072 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1073 }; 1074 1075 pioBU: secumod@fc040000 { 1076 compatible = "atmel,sama5d2-secumod", "syscon"; 1077 reg = <0xfc040000 0x100>; 1078 1079 gpio-controller; 1080 #gpio-cells = <2>; 1081 }; 1082 1083 tdes: crypto@fc044000 { 1084 compatible = "atmel,at91sam9g46-tdes"; 1085 reg = <0xfc044000 0x100>; 1086 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 1087 dmas = <&dma0 1088 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1089 AT91_XDMAC_DT_PERID(28))>, 1090 <&dma0 1091 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1092 AT91_XDMAC_DT_PERID(29))>; 1093 dma-names = "tx", "rx"; 1094 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 1095 clock-names = "tdes_clk"; 1096 }; 1097 1098 classd: classd@fc048000 { 1099 compatible = "atmel,sama5d2-classd"; 1100 reg = <0xfc048000 0x100>; 1101 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; 1102 dmas = <&dma0 1103 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1104 AT91_XDMAC_DT_PERID(47))>; 1105 dma-names = "tx"; 1106 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; 1107 clock-names = "pclk", "gclk"; 1108 status = "disabled"; 1109 }; 1110 1111 i2s1: i2s@fc04c000 { 1112 compatible = "atmel,sama5d2-i2s"; 1113 reg = <0xfc04c000 0x100>; 1114 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; 1115 dmas = <&dma0 1116 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1117 AT91_XDMAC_DT_PERID(33))>, 1118 <&dma0 1119 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1120 AT91_XDMAC_DT_PERID(34))>; 1121 dma-names = "tx", "rx"; 1122 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; 1123 clock-names = "pclk", "gclk"; 1124 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; 1125 assigned-clock-parents = <&pmc PMC_TYPE_GCK 55>; 1126 status = "disabled"; 1127 }; 1128 1129 can1: can@fc050000 { 1130 compatible = "bosch,m_can"; 1131 reg = <0xfc050000 0x4000>, <0x210000 0x3800>; 1132 reg-names = "m_can", "message_ram"; 1133 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, 1134 <65 IRQ_TYPE_LEVEL_HIGH 7>; 1135 interrupt-names = "int0", "int1"; 1136 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 1137 clock-names = "hclk", "cclk"; 1138 assigned-clocks = <&pmc PMC_TYPE_GCK 57>; 1139 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 1140 assigned-clock-rates = <40000000>; 1141 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; 1142 status = "disabled"; 1143 }; 1144 1145 sfrbu: sfr@fc05c000 { 1146 compatible = "atmel,sama5d2-sfrbu", "syscon"; 1147 reg = <0xfc05c000 0x20>; 1148 }; 1149 1150 chipid@fc069000 { 1151 compatible = "atmel,sama5d2-chipid"; 1152 reg = <0xfc069000 0x8>; 1153 }; 1154 }; 1155 }; 1156 };
Cache object: e6c7a753c384f4ed13b95b2fcd0e94a6
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