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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC 4 * 5 * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries 6 * 7 * Author: Eugen Hristev <eugen.hristev@microchip.com> 8 * Author: Claudiu Beznea <claudiu.beznea@microchip.com> 9 * 10 */ 11 12 #include <dt-bindings/interrupt-controller/irq.h> 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 #include <dt-bindings/clock/at91.h> 15 #include <dt-bindings/dma/at91.h> 16 #include <dt-bindings/gpio/gpio.h> 17 18 / { 19 model = "Microchip SAMA7G5 family SoC"; 20 compatible = "microchip,sama7g5"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 interrupt-parent = <&gic>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a7"; 32 reg = <0x0>; 33 clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; 34 clock-names = "cpu"; 35 operating-points-v2 = <&cpu_opp_table>; 36 }; 37 }; 38 39 cpu_opp_table: opp-table { 40 compatible = "operating-points-v2"; 41 42 opp-90000000 { 43 opp-hz = /bits/ 64 <90000000>; 44 opp-microvolt = <1050000 1050000 1225000>; 45 clock-latency-ns = <320000>; 46 }; 47 48 opp-250000000 { 49 opp-hz = /bits/ 64 <250000000>; 50 opp-microvolt = <1050000 1050000 1225000>; 51 clock-latency-ns = <320000>; 52 }; 53 54 opp-600000000 { 55 opp-hz = /bits/ 64 <600000000>; 56 opp-microvolt = <1050000 1050000 1225000>; 57 clock-latency-ns = <320000>; 58 opp-suspend; 59 }; 60 61 opp-800000000 { 62 opp-hz = /bits/ 64 <800000000>; 63 opp-microvolt = <1150000 1125000 1225000>; 64 clock-latency-ns = <320000>; 65 }; 66 67 opp-1000000002 { 68 opp-hz = /bits/ 64 <1000000002>; 69 opp-microvolt = <1250000 1225000 1300000>; 70 clock-latency-ns = <320000>; 71 }; 72 }; 73 74 clocks { 75 slow_xtal: slow_xtal { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 }; 79 80 main_xtal: main_xtal { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 }; 84 85 usb_clk: usb_clk { 86 compatible = "fixed-clock"; 87 #clock-cells = <0>; 88 clock-frequency = <48000000>; 89 }; 90 }; 91 92 vddout25: fixed-regulator-vddout25 { 93 compatible = "regulator-fixed"; 94 95 regulator-name = "VDDOUT25"; 96 regulator-min-microvolt = <2500000>; 97 regulator-max-microvolt = <2500000>; 98 regulator-boot-on; 99 status = "disabled"; 100 }; 101 102 ns_sram: sram@100000 { 103 compatible = "mmio-sram"; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 reg = <0x100000 0x20000>; 107 ranges; 108 }; 109 110 soc { 111 compatible = "simple-bus"; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 ranges; 115 116 nfc_sram: sram@600000 { 117 compatible = "mmio-sram"; 118 no-memory-wc; 119 reg = <0x00600000 0x2400>; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges = <0 0x00600000 0x2400>; 123 }; 124 125 nfc_io: nfc-io@10000000 { 126 compatible = "atmel,sama5d3-nfc-io", "syscon"; 127 reg = <0x10000000 0x8000000>; 128 }; 129 130 ebi: ebi@40000000 { 131 compatible = "atmel,sama5d3-ebi"; 132 #address-cells = <2>; 133 #size-cells = <1>; 134 atmel,smc = <&hsmc>; 135 reg = <0x40000000 0x20000000>; 136 ranges = <0x0 0x0 0x40000000 0x8000000 137 0x1 0x0 0x48000000 0x8000000 138 0x2 0x0 0x50000000 0x8000000 139 0x3 0x0 0x58000000 0x8000000>; 140 clocks = <&pmc PMC_TYPE_CORE PMC_MCK1>; 141 status = "disabled"; 142 143 nand_controller: nand-controller { 144 compatible = "atmel,sama5d3-nand-controller"; 145 atmel,nfc-sram = <&nfc_sram>; 146 atmel,nfc-io = <&nfc_io>; 147 ecc-engine = <&pmecc>; 148 #address-cells = <2>; 149 #size-cells = <1>; 150 ranges; 151 status = "disabled"; 152 }; 153 }; 154 155 securam: securam@e0000000 { 156 compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; 157 reg = <0xe0000000 0x4000>; 158 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 159 #address-cells = <1>; 160 #size-cells = <1>; 161 ranges = <0 0xe0000000 0x4000>; 162 no-memory-wc; 163 }; 164 165 secumod: secumod@e0004000 { 166 compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon"; 167 reg = <0xe0004000 0x4000>; 168 gpio-controller; 169 #gpio-cells = <2>; 170 }; 171 172 sfrbu: sfr@e0008000 { 173 compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; 174 reg = <0xe0008000 0x20>; 175 }; 176 177 pioA: pinctrl@e0014000 { 178 compatible = "microchip,sama7g5-pinctrl"; 179 reg = <0xe0014000 0x800>; 180 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-controller; 186 #interrupt-cells = <2>; 187 gpio-controller; 188 #gpio-cells = <2>; 189 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 190 }; 191 192 pmc: pmc@e0018000 { 193 compatible = "microchip,sama7g5-pmc", "syscon"; 194 reg = <0xe0018000 0x200>; 195 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 196 #clock-cells = <2>; 197 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 198 clock-names = "td_slck", "md_slck", "main_xtal"; 199 }; 200 201 reset_controller: reset-controller@e001d000 { 202 compatible = "microchip,sama7g5-rstc"; 203 reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>; 204 #reset-cells = <1>; 205 clocks = <&clk32k 0>; 206 }; 207 208 shdwc: shdwc@e001d010 { 209 compatible = "microchip,sama7g5-shdwc", "syscon"; 210 reg = <0xe001d010 0x10>; 211 clocks = <&clk32k 0>; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 atmel,wakeup-rtc-timer; 215 atmel,wakeup-rtt-timer; 216 status = "disabled"; 217 }; 218 219 rtt: rtc@e001d020 { 220 compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; 221 reg = <0xe001d020 0x30>; 222 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&clk32k 0>; 224 }; 225 226 clk32k: clock-controller@e001d050 { 227 compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; 228 reg = <0xe001d050 0x4>; 229 clocks = <&slow_xtal>; 230 #clock-cells = <1>; 231 }; 232 233 gpbr: gpbr@e001d060 { 234 compatible = "microchip,sama7g5-gpbr", "syscon"; 235 reg = <0xe001d060 0x48>; 236 }; 237 238 rtc: rtc@e001d0a8 { 239 compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc"; 240 reg = <0xe001d0a8 0x30>; 241 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&clk32k 1>; 243 }; 244 245 ps_wdt: watchdog@e001d180 { 246 compatible = "microchip,sama7g5-wdt"; 247 reg = <0xe001d180 0x24>; 248 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&clk32k 0>; 250 }; 251 252 chipid@e0020000 { 253 compatible = "microchip,sama7g5-chipid"; 254 reg = <0xe0020000 0x8>; 255 }; 256 257 tcb1: timer@e0800000 { 258 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 reg = <0xe0800000 0x100>; 262 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>; 264 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 265 }; 266 267 hsmc: hsmc@e0808000 { 268 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 269 reg = <0xe0808000 0x1000>; 270 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 ranges; 275 276 pmecc: ecc-engine@e0808070 { 277 compatible = "atmel,sama5d2-pmecc"; 278 reg = <0xe0808070 0x490>, 279 <0xe0808500 0x200>; 280 }; 281 }; 282 283 qspi0: spi@e080c000 { 284 compatible = "microchip,sama7g5-ospi"; 285 reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; 286 reg-names = "qspi_base", "qspi_mmap"; 287 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 288 dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>, 289 <&dma0 AT91_XDMAC_DT_PERID(40)>; 290 dma-names = "tx", "rx"; 291 clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>; 292 clock-names = "pclk", "gclk"; 293 #address-cells = <1>; 294 #size-cells = <0>; 295 status = "disabled"; 296 }; 297 298 qspi1: spi@e0810000 { 299 compatible = "microchip,sama7g5-qspi"; 300 reg = <0xe0810000 0x400>, <0x30000000 0x10000000>; 301 reg-names = "qspi_base", "qspi_mmap"; 302 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 303 dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>, 304 <&dma0 AT91_XDMAC_DT_PERID(42)>; 305 dma-names = "tx", "rx"; 306 clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>; 307 clock-names = "pclk", "gclk"; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 status = "disabled"; 311 }; 312 313 can0: can@e0828000 { 314 compatible = "bosch,m_can"; 315 reg = <0xe0828000 0x100>, <0x100000 0x7800>; 316 reg-names = "m_can", "message_ram"; 317 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH 318 GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 319 interrupt-names = "int0", "int1"; 320 clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; 321 clock-names = "hclk", "cclk"; 322 assigned-clocks = <&pmc PMC_TYPE_GCK 61>; 323 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 324 assigned-clock-rates = <40000000>; 325 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; 326 status = "disabled"; 327 }; 328 329 can1: can@e082c000 { 330 compatible = "bosch,m_can"; 331 reg = <0xe082c000 0x100>, <0x100000 0xbc00>; 332 reg-names = "m_can", "message_ram"; 333 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 334 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 335 interrupt-names = "int0", "int1"; 336 clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; 337 clock-names = "hclk", "cclk"; 338 assigned-clocks = <&pmc PMC_TYPE_GCK 62>; 339 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 340 assigned-clock-rates = <40000000>; 341 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; 342 status = "disabled"; 343 }; 344 345 can2: can@e0830000 { 346 compatible = "bosch,m_can"; 347 reg = <0xe0830000 0x100>, <0x100000 0x10000>; 348 reg-names = "m_can", "message_ram"; 349 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH 350 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 351 interrupt-names = "int0", "int1"; 352 clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>; 353 clock-names = "hclk", "cclk"; 354 assigned-clocks = <&pmc PMC_TYPE_GCK 63>; 355 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 356 assigned-clock-rates = <40000000>; 357 bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; 358 status = "disabled"; 359 }; 360 361 can3: can@e0834000 { 362 compatible = "bosch,m_can"; 363 reg = <0xe0834000 0x100>, <0x110000 0x4400>; 364 reg-names = "m_can", "message_ram"; 365 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 366 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 367 interrupt-names = "int0", "int1"; 368 clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>; 369 clock-names = "hclk", "cclk"; 370 assigned-clocks = <&pmc PMC_TYPE_GCK 64>; 371 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 372 assigned-clock-rates = <40000000>; 373 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 374 status = "disabled"; 375 }; 376 377 can4: can@e0838000 { 378 compatible = "bosch,m_can"; 379 reg = <0xe0838000 0x100>, <0x110000 0x8800>; 380 reg-names = "m_can", "message_ram"; 381 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 382 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 383 interrupt-names = "int0", "int1"; 384 clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>; 385 clock-names = "hclk", "cclk"; 386 assigned-clocks = <&pmc PMC_TYPE_GCK 65>; 387 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 388 assigned-clock-rates = <40000000>; 389 bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; 390 status = "disabled"; 391 }; 392 393 can5: can@e083c000 { 394 compatible = "bosch,m_can"; 395 reg = <0xe083c000 0x100>, <0x110000 0xcc00>; 396 reg-names = "m_can", "message_ram"; 397 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 398 GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 399 interrupt-names = "int0", "int1"; 400 clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; 401 clock-names = "hclk", "cclk"; 402 assigned-clocks = <&pmc PMC_TYPE_GCK 66>; 403 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 404 assigned-clock-rates = <40000000>; 405 bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>; 406 status = "disabled"; 407 }; 408 409 adc: adc@e1000000 { 410 compatible = "microchip,sama7g5-adc"; 411 reg = <0xe1000000 0x200>; 412 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&pmc PMC_TYPE_GCK 26>; 414 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 415 assigned-clock-rates = <100000000>; 416 clock-names = "adc_clk"; 417 dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>; 418 dma-names = "rx"; 419 atmel,min-sample-rate-hz = <200000>; 420 atmel,max-sample-rate-hz = <20000000>; 421 atmel,startup-time-ms = <4>; 422 status = "disabled"; 423 }; 424 425 sdmmc0: mmc@e1204000 { 426 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 427 reg = <0xe1204000 0x4000>; 428 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; 430 clock-names = "hclock", "multclk"; 431 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 432 assigned-clocks = <&pmc PMC_TYPE_GCK 80>; 433 assigned-clock-rates = <200000000>; 434 microchip,sdcal-inverted; 435 status = "disabled"; 436 }; 437 438 sdmmc1: mmc@e1208000 { 439 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 440 reg = <0xe1208000 0x4000>; 441 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; 443 clock-names = "hclock", "multclk"; 444 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 445 assigned-clocks = <&pmc PMC_TYPE_GCK 81>; 446 assigned-clock-rates = <200000000>; 447 microchip,sdcal-inverted; 448 status = "disabled"; 449 }; 450 451 sdmmc2: mmc@e120c000 { 452 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; 453 reg = <0xe120c000 0x4000>; 454 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>; 456 clock-names = "hclock", "multclk"; 457 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; 458 assigned-clocks = <&pmc PMC_TYPE_GCK 82>; 459 assigned-clock-rates = <200000000>; 460 microchip,sdcal-inverted; 461 status = "disabled"; 462 }; 463 464 pwm: pwm@e1604000 { 465 compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; 466 reg = <0xe1604000 0x4000>; 467 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 468 #pwm-cells = <3>; 469 clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; 470 status = "disabled"; 471 }; 472 473 pdmc0: sound@e1608000 { 474 compatible = "microchip,sama7g5-pdmc"; 475 reg = <0xe1608000 0x1000>; 476 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 477 #sound-dai-cells = <0>; 478 dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>; 479 dma-names = "rx"; 480 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>; 481 clock-names = "pclk", "gclk"; 482 status = "disabled"; 483 }; 484 485 pdmc1: sound@e160c000 { 486 compatible = "microchip,sama7g5-pdmc"; 487 reg = <0xe160c000 0x1000>; 488 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 489 #sound-dai-cells = <0>; 490 dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>; 491 dma-names = "rx"; 492 clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>; 493 clock-names = "pclk", "gclk"; 494 status = "disabled"; 495 }; 496 497 spdifrx: spdifrx@e1614000 { 498 #sound-dai-cells = <0>; 499 compatible = "microchip,sama7g5-spdifrx"; 500 reg = <0xe1614000 0x4000>; 501 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 502 dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>; 503 dma-names = "rx"; 504 clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>; 505 clock-names = "pclk", "gclk"; 506 status = "disabled"; 507 }; 508 509 spdiftx: spdiftx@e1618000 { 510 #sound-dai-cells = <0>; 511 compatible = "microchip,sama7g5-spdiftx"; 512 reg = <0xe1618000 0x4000>; 513 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 514 dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>; 515 dma-names = "tx"; 516 clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>; 517 clock-names = "pclk", "gclk"; 518 }; 519 520 i2s0: i2s@e161c000 { 521 compatible = "microchip,sama7g5-i2smcc"; 522 #sound-dai-cells = <0>; 523 reg = <0xe161c000 0x4000>; 524 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 525 dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>; 526 dma-names = "tx", "rx"; 527 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 528 clock-names = "pclk", "gclk"; 529 status = "disabled"; 530 }; 531 532 i2s1: i2s@e1620000 { 533 compatible = "microchip,sama7g5-i2smcc"; 534 #sound-dai-cells = <0>; 535 reg = <0xe1620000 0x4000>; 536 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 537 dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>; 538 dma-names = "tx", "rx"; 539 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; 540 clock-names = "pclk", "gclk"; 541 status = "disabled"; 542 }; 543 544 eic: interrupt-controller@e1628000 { 545 compatible = "microchip,sama7g5-eic"; 546 reg = <0xe1628000 0xec>; 547 interrupt-parent = <&gic>; 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 553 clock-names = "pclk"; 554 status = "disabled"; 555 }; 556 557 pit64b0: timer@e1800000 { 558 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 559 reg = <0xe1800000 0x4000>; 560 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; 562 clock-names = "pclk", "gclk"; 563 }; 564 565 pit64b1: timer@e1804000 { 566 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; 567 reg = <0xe1804000 0x4000>; 568 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>; 570 clock-names = "pclk", "gclk"; 571 }; 572 573 aes: crypto@e1810000 { 574 compatible = "atmel,at91sam9g46-aes"; 575 reg = <0xe1810000 0x100>; 576 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 578 clock-names = "aes_clk"; 579 dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, 580 <&dma0 AT91_XDMAC_DT_PERID(2)>; 581 dma-names = "tx", "rx"; 582 }; 583 584 sha: crypto@e1814000 { 585 compatible = "atmel,at91sam9g46-sha"; 586 reg = <0xe1814000 0x100>; 587 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; 589 clock-names = "sha_clk"; 590 dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; 591 dma-names = "tx"; 592 }; 593 594 flx0: flexcom@e1818000 { 595 compatible = "atmel,sama5d2-flexcom"; 596 reg = <0xe1818000 0x200>; 597 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 598 #address-cells = <1>; 599 #size-cells = <1>; 600 ranges = <0x0 0xe1818000 0x800>; 601 status = "disabled"; 602 603 uart0: serial@200 { 604 compatible = "atmel,at91sam9260-usart"; 605 reg = <0x200 0x200>; 606 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 608 clock-names = "usart"; 609 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, 610 <&dma1 AT91_XDMAC_DT_PERID(5)>; 611 dma-names = "tx", "rx"; 612 atmel,use-dma-rx; 613 atmel,use-dma-tx; 614 status = "disabled"; 615 }; 616 }; 617 618 flx1: flexcom@e181c000 { 619 compatible = "atmel,sama5d2-flexcom"; 620 reg = <0xe181c000 0x200>; 621 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 622 #address-cells = <1>; 623 #size-cells = <1>; 624 ranges = <0x0 0xe181c000 0x800>; 625 status = "disabled"; 626 627 i2c1: i2c@600 { 628 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 629 reg = <0x600 0x200>; 630 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 634 atmel,fifo-size = <32>; 635 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 636 <&dma0 AT91_XDMAC_DT_PERID(7)>; 637 dma-names = "tx", "rx"; 638 status = "disabled"; 639 }; 640 }; 641 642 flx3: flexcom@e1824000 { 643 compatible = "atmel,sama5d2-flexcom"; 644 reg = <0xe1824000 0x200>; 645 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 646 #address-cells = <1>; 647 #size-cells = <1>; 648 ranges = <0x0 0xe1824000 0x800>; 649 status = "disabled"; 650 651 uart3: serial@200 { 652 compatible = "atmel,at91sam9260-usart"; 653 reg = <0x200 0x200>; 654 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 656 clock-names = "usart"; 657 dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>, 658 <&dma1 AT91_XDMAC_DT_PERID(11)>; 659 dma-names = "tx", "rx"; 660 atmel,use-dma-rx; 661 atmel,use-dma-tx; 662 status = "disabled"; 663 }; 664 }; 665 666 trng: rng@e2010000 { 667 compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng"; 668 reg = <0xe2010000 0x100>; 669 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; 671 status = "disabled"; 672 }; 673 674 tdes: crypto@e2014000 { 675 compatible = "atmel,at91sam9g46-tdes"; 676 reg = <0xe2014000 0x100>; 677 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; 679 clock-names = "tdes_clk"; 680 dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, 681 <&dma0 AT91_XDMAC_DT_PERID(53)>; 682 dma-names = "tx", "rx"; 683 }; 684 685 flx4: flexcom@e2018000 { 686 compatible = "atmel,sama5d2-flexcom"; 687 reg = <0xe2018000 0x200>; 688 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 689 #address-cells = <1>; 690 #size-cells = <1>; 691 ranges = <0x0 0xe2018000 0x800>; 692 status = "disabled"; 693 694 uart4: serial@200 { 695 compatible = "atmel,at91sam9260-usart"; 696 reg = <0x200 0x200>; 697 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 699 clock-names = "usart"; 700 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, 701 <&dma1 AT91_XDMAC_DT_PERID(13)>; 702 dma-names = "tx", "rx"; 703 atmel,use-dma-rx; 704 atmel,use-dma-tx; 705 atmel,fifo-size = <16>; 706 status = "disabled"; 707 }; 708 }; 709 710 flx7: flexcom@e2024000 { 711 compatible = "atmel,sama5d2-flexcom"; 712 reg = <0xe2024000 0x200>; 713 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 714 #address-cells = <1>; 715 #size-cells = <1>; 716 ranges = <0x0 0xe2024000 0x800>; 717 status = "disabled"; 718 719 uart7: serial@200 { 720 compatible = "atmel,at91sam9260-usart"; 721 reg = <0x200 0x200>; 722 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 723 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 724 clock-names = "usart"; 725 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 726 <&dma1 AT91_XDMAC_DT_PERID(19)>; 727 dma-names = "tx", "rx"; 728 atmel,use-dma-rx; 729 atmel,use-dma-tx; 730 atmel,fifo-size = <16>; 731 status = "disabled"; 732 }; 733 }; 734 735 gmac0: ethernet@e2800000 { 736 compatible = "microchip,sama7g5-gem"; 737 reg = <0xe2800000 0x1000>; 738 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 739 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 740 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 741 GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 742 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 743 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; 745 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 746 assigned-clocks = <&pmc PMC_TYPE_GCK 51>; 747 assigned-clock-rates = <125000000>; 748 status = "disabled"; 749 }; 750 751 gmac1: ethernet@e2804000 { 752 compatible = "microchip,sama7g5-emac"; 753 reg = <0xe2804000 0x1000>; 754 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 755 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; 757 clock-names = "pclk", "hclk"; 758 status = "disabled"; 759 }; 760 761 dma0: dma-controller@e2808000 { 762 compatible = "microchip,sama7g5-dma"; 763 reg = <0xe2808000 0x1000>; 764 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 765 #dma-cells = <1>; 766 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 767 clock-names = "dma_clk"; 768 status = "disabled"; 769 }; 770 771 dma1: dma-controller@e280c000 { 772 compatible = "microchip,sama7g5-dma"; 773 reg = <0xe280c000 0x1000>; 774 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 775 #dma-cells = <1>; 776 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 777 clock-names = "dma_clk"; 778 status = "disabled"; 779 }; 780 781 /* Place dma2 here despite it's address */ 782 dma2: dma-controller@e1200000 { 783 compatible = "microchip,sama7g5-dma"; 784 reg = <0xe1200000 0x1000>; 785 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 786 #dma-cells = <1>; 787 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 788 clock-names = "dma_clk"; 789 dma-requests = <0>; 790 status = "disabled"; 791 }; 792 793 tcb0: timer@e2814000 { 794 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 reg = <0xe2814000 0x100>; 798 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 799 clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>; 800 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 801 }; 802 803 flx8: flexcom@e2818000 { 804 compatible = "atmel,sama5d2-flexcom"; 805 reg = <0xe2818000 0x200>; 806 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 807 #address-cells = <1>; 808 #size-cells = <1>; 809 ranges = <0x0 0xe2818000 0x800>; 810 status = "disabled"; 811 812 i2c8: i2c@600 { 813 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 814 reg = <0x600 0x200>; 815 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; 819 atmel,fifo-size = <32>; 820 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, 821 <&dma0 AT91_XDMAC_DT_PERID(21)>; 822 dma-names = "tx", "rx"; 823 status = "disabled"; 824 }; 825 }; 826 827 flx9: flexcom@e281c000 { 828 compatible = "atmel,sama5d2-flexcom"; 829 reg = <0xe281c000 0x200>; 830 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 831 #address-cells = <1>; 832 #size-cells = <1>; 833 ranges = <0x0 0xe281c000 0x800>; 834 status = "disabled"; 835 836 i2c9: i2c@600 { 837 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c"; 838 reg = <0x600 0x200>; 839 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 843 atmel,fifo-size = <32>; 844 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, 845 <&dma0 AT91_XDMAC_DT_PERID(23)>; 846 dma-names = "tx", "rx"; 847 status = "disabled"; 848 }; 849 }; 850 851 flx11: flexcom@e2824000 { 852 compatible = "atmel,sama5d2-flexcom"; 853 reg = <0xe2824000 0x200>; 854 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 855 #address-cells = <1>; 856 #size-cells = <1>; 857 ranges = <0x0 0xe2824000 0x800>; 858 status = "disabled"; 859 860 spi11: spi@400 { 861 compatible = "atmel,at91rm9200-spi"; 862 reg = <0x400 0x200>; 863 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 865 clock-names = "spi_clk"; 866 #address-cells = <1>; 867 #size-cells = <0>; 868 atmel,fifo-size = <32>; 869 dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>, 870 <&dma0 AT91_XDMAC_DT_PERID(28)>; 871 dma-names = "rx", "tx"; 872 status = "disabled"; 873 }; 874 }; 875 876 uddrc: uddrc@e3800000 { 877 compatible = "microchip,sama7g5-uddrc"; 878 reg = <0xe3800000 0x4000>; 879 }; 880 881 ddr3phy: ddr3phy@e3804000 { 882 compatible = "microchip,sama7g5-ddr3phy"; 883 reg = <0xe3804000 0x1000>; 884 }; 885 886 gic: interrupt-controller@e8c11000 { 887 compatible = "arm,cortex-a7-gic"; 888 #interrupt-cells = <3>; 889 #address-cells = <0>; 890 interrupt-controller; 891 reg = <0xe8c11000 0x1000>, 892 <0xe8c12000 0x2000>; 893 }; 894 }; 895 };
Cache object: 6dd9ef153cc603495befca87227b31c3
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