socfpga_arria10_socdk.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0+
    2 /*
    3  * Copyright (C) 2015 Altera Corporation <www.altera.com>
    4  */
    5 #include "socfpga_arria10.dtsi"
    6 
    7 / {
    8         model = "Altera SOCFPGA Arria 10";
    9         compatible = "altr,socfpga-arria10-socdk", "altr,socfpga-arria10", "altr,socfpga";
   10 
   11         aliases {
   12                 ethernet0 = &gmac0;
   13                 serial0 = &uart1;
   14         };
   15 
   16         chosen {
   17                 bootargs = "earlyprintk";
   18                 stdout-path = "serial0:115200n8";
   19         };
   20 
   21         memory@0 {
   22                 name = "memory";
   23                 device_type = "memory";
   24                 reg = <0x0 0x40000000>; /* 1GB */
   25         };
   26 
   27         a10leds {
   28                 compatible = "gpio-leds";
   29 
   30                 a10sr_led0 {
   31                         label = "a10sr-led0";
   32                         gpios = <&a10sr_gpio 0 1>;
   33                 };
   34 
   35                 a10sr_led1 {
   36                         label = "a10sr-led1";
   37                         gpios = <&a10sr_gpio 1 1>;
   38                 };
   39 
   40                 a10sr_led2 {
   41                         label = "a10sr-led2";
   42                         gpios = <&a10sr_gpio 2 1>;
   43                 };
   44 
   45                 a10sr_led3 {
   46                         label = "a10sr-led3";
   47                         gpios = <&a10sr_gpio 3 1>;
   48                 };
   49         };
   50 
   51         ref_033v: 033-v-ref {
   52                 compatible = "regulator-fixed";
   53                 regulator-name = "0.33V";
   54                 regulator-min-microvolt = <330000>;
   55                 regulator-max-microvolt = <330000>;
   56         };
   57 
   58         soc {
   59                 clkmgr@ffd04000 {
   60                         clocks {
   61                                 osc1 {
   62                                         clock-frequency = <25000000>;
   63                                 };
   64                         };
   65                 };
   66         };
   67 };
   68 
   69 &gmac0 {
   70         phy-mode = "rgmii";
   71         phy-addr = <0xffffffff>; /* probe for phy addr */
   72 
   73         /*
   74          * These skews assume the user's FPGA design is adding 600ps of delay
   75          * for TX_CLK on Arria 10.
   76          *
   77          * All skews are offset since hardware skew values for the ksz9031
   78          * range from a negative skew to a positive skew.
   79          * See the micrel-ksz90x1.txt Documentation file for details.
   80          */
   81         txd0-skew-ps = <0>; /* -420ps */
   82         txd1-skew-ps = <0>; /* -420ps */
   83         txd2-skew-ps = <0>; /* -420ps */
   84         txd3-skew-ps = <0>; /* -420ps */
   85         rxd0-skew-ps = <420>; /* 0ps */
   86         rxd1-skew-ps = <420>; /* 0ps */
   87         rxd2-skew-ps = <420>; /* 0ps */
   88         rxd3-skew-ps = <420>; /* 0ps */
   89         txen-skew-ps = <0>; /* -420ps */
   90         txc-skew-ps = <1860>; /* 960ps */
   91         rxdv-skew-ps = <420>; /* 0ps */
   92         rxc-skew-ps = <1680>; /* 780ps */
   93         max-frame-size = <3800>;
   94         status = "okay";
   95 };
   96 
   97 &gpio1 {
   98         status = "okay";
   99 };
  100 
  101 &spi1 {
  102         status = "okay";
  103 
  104         resource-manager@0 {
  105                 compatible = "altr,a10sr";
  106                 reg = <0>;
  107                 spi-max-frequency = <100000>;
  108                 /* low-level active IRQ at GPIO1_5 */
  109                 interrupt-parent = <&portb>;
  110                 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
  111                 interrupt-controller;
  112                 #interrupt-cells = <2>;
  113 
  114                 a10sr_gpio: gpio-controller {
  115                         compatible = "altr,a10sr-gpio";
  116                         gpio-controller;
  117                         #gpio-cells = <2>;
  118                 };
  119 
  120                 a10sr_rst: reset-controller {
  121                         compatible = "altr,a10sr-reset";
  122                         #reset-cells = <1>;
  123                 };
  124         };
  125 };
  126 
  127 &i2c1 {
  128         status = "okay";
  129 
  130         /*
  131          * adjust the falling times to decrease the i2c frequency to 50Khz
  132          * because the LCD module does not work at the standard 100Khz
  133          */
  134         clock-frequency = <100000>;
  135         i2c-sda-falling-time-ns = <6000>;
  136         i2c-scl-falling-time-ns = <6000>;
  137 
  138         adc@14 {
  139                 compatible = "lltc,ltc2497";
  140                 reg = <0x14>;
  141                 vref-supply = <&ref_033v>;
  142         };
  143 
  144         adc@16 {
  145                 compatible = "lltc,ltc2497";
  146                 reg = <0x16>;
  147                 vref-supply = <&ref_033v>;
  148         };
  149 
  150         eeprom@51 {
  151                 compatible = "atmel,24c32";
  152                 reg = <0x51>;
  153                 pagesize = <32>;
  154         };
  155 
  156         rtc@68 {
  157                 compatible = "dallas,ds1339";
  158                 reg = <0x68>;
  159         };
  160 
  161         ltc@5c {
  162                 compatible = "ltc2977";
  163                 reg = <0x5c>;
  164         };
  165 
  166         temp@4c {
  167                 compatible = "maxim,max1619";
  168                 reg = <0x4c>;
  169         };
  170 };
  171 
  172 &uart1 {
  173         status = "okay";
  174 };
  175 
  176 &usb0 {
  177         status = "okay";
  178         disable-over-current;
  179 };
  180 
  181 &watchdog1 {
  182         status = "okay";
  183 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/socfpga_arria10_socdk.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/socfpga_arria10_socdk.dtsi