socfpga_cyclone5_vining_fpga.dts

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    1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
    2 /*
    3  * Copyright (C) 2015 Marek Vasut <marex@denx.de>
    4  */
    5 
    6 #include "socfpga_cyclone5.dtsi"
    7 #include <dt-bindings/gpio/gpio.h>
    8 #include <dt-bindings/input/input.h>
    9 
   10 / {
   11         model = "samtec VIN|ING FPGA";
   12         compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
   13 
   14         chosen {
   15                 bootargs = "earlyprintk";
   16                 stdout-path = "serial0:115200n8";
   17         };
   18 
   19         memory@0 {
   20                 name = "memory";
   21                 device_type = "memory";
   22                 reg = <0x0 0x40000000>; /* 1GB */
   23         };
   24 
   25         aliases {
   26                 /*
   27                  * This allow the ethaddr uboot environment variable contents
   28                  * to be added to the gmac1 device tree blob.
   29                  */
   30                 ethernet0 = &gmac1;
   31                 ethernet1 = &gmac0;
   32         };
   33 
   34         gpio-keys {
   35                 compatible = "gpio-keys";
   36 
   37                 hps_temp0 {
   38                         label = "BTN_0";                        /* TEMP_OS */
   39                         gpios = <&portc 18 GPIO_ACTIVE_LOW>;    /* HPS_GPI5 */
   40                         linux,code = <BTN_0>;
   41                 };
   42 
   43                 hps_hkey0 {
   44                         label = "GP_SWITCH";                    /* GP_SWITCH */
   45                         gpios = <&portc 19 GPIO_ACTIVE_LOW>;    /* HPS_GPI6 */
   46                         linux,code = <BTN_1>;
   47                 };
   48 
   49                 hps_hkey1 {
   50                         label = "RESET_SWITCH";                 /* RESET_SWITCH */
   51                         gpios = <&portc 20 GPIO_ACTIVE_LOW>;    /* HPS_GPI7 */
   52                         linux,code = <BTN_2>;
   53                 };
   54 
   55                 hps_hkey2 {
   56                         label = "POWER_DOWN";                   /* POWER_DOWN */
   57                         gpios = <&portc 4 GPIO_ACTIVE_LOW>;     /* HPS_GPIO62 */
   58                         linux,code = <KEY_POWER>;
   59                 };
   60 
   61                 hps_hkey3 {
   62                         label = "SENSE";                        /* SENSE */
   63                         gpios = <&porta 9 GPIO_ACTIVE_LOW>;     /* HPS_GPIO9 */
   64                         linux,code = <BTN_3>;
   65                 };
   66         };
   67 
   68         regulator-usb-nrst {
   69                 compatible = "regulator-fixed";
   70                 regulator-name = "usb_nrst";
   71                 regulator-min-microvolt = <5000000>;
   72                 regulator-max-microvolt = <5000000>;
   73                 gpio = <&portb 5 GPIO_ACTIVE_HIGH>;
   74                 startup-delay-us = <70000>;
   75                 enable-active-high;
   76                 regulator-always-on;
   77         };
   78 };
   79 
   80 &gmac1 {
   81         status = "okay";
   82         phy-mode = "rgmii";
   83         phy-handle = <&phy1>;
   84 
   85         snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>;
   86         snps,reset-active-low;
   87         snps,reset-delays-us = <10000 10000 10000>;
   88 
   89         mdio0 {
   90                 #address-cells = <1>;
   91                 #size-cells = <0>;
   92                 compatible = "snps,dwmac-mdio";
   93                 phy1: ethernet-phy@1 {
   94                         reg = <1>;
   95                         rxd0-skew-ps = <0>;
   96                         rxd1-skew-ps = <0>;
   97                         rxd2-skew-ps = <0>;
   98                         rxd3-skew-ps = <0>;
   99                         txd0-skew-ps = <0>;
  100                         txd1-skew-ps = <0>;
  101                         txd2-skew-ps = <0>;
  102                         txd3-skew-ps = <0>;
  103                         txen-skew-ps = <0>;
  104                         txc-skew-ps = <1860>;
  105                         rxdv-skew-ps = <0>;
  106                         rxc-skew-ps = <1860>;
  107                 };
  108         };
  109 };
  110 
  111 &gpio0 {        /* GPIO 0..29 */
  112         status = "okay";
  113 };
  114 
  115 &gpio1 {        /* GPIO 30..57 */
  116         status = "okay";
  117 };
  118 
  119 &gpio2 {        /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
  120         status = "okay";
  121 };
  122 
  123 &i2c0 {
  124         status = "okay";
  125 
  126         gpio: pca9557@1f {
  127                 compatible = "nxp,pca9557";
  128                 reg = <0x1f>;
  129                 gpio-controller;
  130                 #gpio-cells = <2>;
  131         };
  132 
  133         temp: lm75@48 {
  134                 compatible = "lm75";
  135                 reg = <0x48>;
  136         };
  137 
  138         at24@50 {
  139                 compatible = "atmel,24c01";
  140                 pagesize = <8>;
  141                 reg = <0x50>;
  142         };
  143 
  144         i2cswitch@70 {
  145                 compatible = "nxp,pca9548";
  146                 #address-cells = <1>;
  147                 #size-cells = <0>;
  148                 reg = <0x70>;
  149 
  150                 i2c@0 {
  151                         #address-cells = <1>;
  152                         #size-cells = <0>;
  153                         reg = <0>;
  154                 };
  155 
  156                 i2c@1 {
  157                         #address-cells = <1>;
  158                         #size-cells = <0>;
  159                         reg = <1>;
  160                 };
  161 
  162                 i2c@2 {
  163                         #address-cells = <1>;
  164                         #size-cells = <0>;
  165                         reg = <2>;
  166                 };
  167 
  168                 i2c@3 {
  169                         #address-cells = <1>;
  170                         #size-cells = <0>;
  171                         reg = <3>;
  172                 };
  173 
  174                 i2c@4 {
  175                         #address-cells = <1>;
  176                         #size-cells = <0>;
  177                         reg = <4>;
  178                 };
  179 
  180                 i2c@5 {
  181                         #address-cells = <1>;
  182                         #size-cells = <0>;
  183                         reg = <5>;
  184                 };
  185 
  186                 i2c@6 { /* Backplane EEPROM */
  187                         #address-cells = <1>;
  188                         #size-cells = <0>;
  189                         reg = <6>;
  190                         eeprom@51 {
  191                                 compatible = "atmel,24c01";
  192                                 pagesize = <8>;
  193                                 reg = <0x51>;
  194                         };
  195                 };
  196 
  197                 i2c@7 { /* Power board EEPROM */
  198                         #address-cells = <1>;
  199                         #size-cells = <0>;
  200                         reg = <7>;
  201                         eeprom@51 {
  202                                 compatible = "atmel,24c01";
  203                                 pagesize = <8>;
  204                                 reg = <0x51>;
  205                         };
  206                 };
  207         };
  208 };
  209 
  210 &i2c1 {
  211         status = "okay";
  212         clock-frequency = <100000>;
  213 
  214         at24@50 {
  215                 compatible = "atmel,24c02";
  216                 pagesize = <8>;
  217                 reg = <0x50>;
  218         };
  219 };
  220 
  221 &qspi {
  222         status = "okay";
  223 
  224         flash@0 {
  225                 #address-cells = <1>;
  226                 #size-cells = <1>;
  227                 compatible = "micron,n25q128", "jedec,spi-nor";
  228                 reg = <0>;              /* chip select */
  229                 spi-max-frequency = <100000000>;
  230                 m25p,fast-read;
  231 
  232                 cdns,page-size = <256>;
  233                 cdns,block-size = <16>;
  234                 cdns,read-delay = <4>;
  235                 cdns,tshsl-ns = <50>;
  236                 cdns,tsd2d-ns = <50>;
  237                 cdns,tchsh-ns = <4>;
  238                 cdns,tslch-ns = <4>;
  239         };
  240 
  241         flash@1 {
  242                 #address-cells = <1>;
  243                 #size-cells = <1>;
  244                 compatible = "micron,mt25qu02g", "jedec,spi-nor";
  245                 reg = <1>;              /* chip select */
  246                 spi-max-frequency = <100000000>;
  247                 m25p,fast-read;
  248 
  249                 cdns,page-size = <256>;
  250                 cdns,block-size = <16>;
  251                 cdns,read-delay = <4>;
  252                 cdns,tshsl-ns = <50>;
  253                 cdns,tsd2d-ns = <50>;
  254                 cdns,tchsh-ns = <4>;
  255                 cdns,tslch-ns = <4>;
  256         };
  257 };
  258 
  259 &usb0 {
  260         dr_mode = "host";
  261         status = "okay";
  262 };
  263 
  264 &usb1 {
  265         dr_mode = "peripheral";
  266         status = "okay";
  267 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/socfpga_cyclone5_vining_fpga.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/socfpga_cyclone5_vining_fpga.dts