The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/st-pincfg.h

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    1 /* SPDX-License-Identifier: GPL-2.0 */
    2 #ifndef _ST_PINCFG_H_
    3 #define _ST_PINCFG_H_
    4 
    5 /* Alternate functions */
    6 #define ALT1    1
    7 #define ALT2    2
    8 #define ALT3    3
    9 #define ALT4    4
   10 #define ALT5    5
   11 #define ALT6    6
   12 #define ALT7    7
   13 
   14 /* Output enable */
   15 #define OE                      (1 << 27)
   16 /* Pull Up */
   17 #define PU                      (1 << 26)
   18 /* Open Drain */
   19 #define OD                      (1 << 25)
   20 #define RT                      (1 << 23)
   21 #define INVERTCLK               (1 << 22)
   22 #define CLKNOTDATA              (1 << 21)
   23 #define DOUBLE_EDGE             (1 << 20)
   24 #define CLK_A                   (0 << 18)
   25 #define CLK_B                   (1 << 18)
   26 #define CLK_C                   (2 << 18)
   27 #define CLK_D                   (3 << 18)
   28 
   29 /* User-frendly defines for Pin Direction */
   30                 /* oe = 0, pu = 0, od = 0 */
   31 #define IN                      (0)
   32                 /* oe = 0, pu = 1, od = 0 */
   33 #define IN_PU                   (PU)
   34                 /* oe = 1, pu = 0, od = 0 */
   35 #define OUT                     (OE)
   36                 /* oe = 1, pu = 0, od = 1 */
   37 #define BIDIR                   (OE | OD)
   38                 /* oe = 1, pu = 1, od = 1 */
   39 #define BIDIR_PU                (OE | PU | OD)
   40 
   41 /* RETIME_TYPE */
   42 /*
   43  * B Mode
   44  * Bypass retime with optional delay parameter
   45  */
   46 #define BYPASS          (0)
   47 /*
   48  * R0, R1, R0D, R1D modes
   49  * single-edge data non inverted clock, retime data with clk
   50  */
   51 #define SE_NICLK_IO     (RT)
   52 /*
   53  * RIV0, RIV1, RIV0D, RIV1D modes
   54  * single-edge data inverted clock, retime data with clk
   55  */
   56 #define SE_ICLK_IO      (RT | INVERTCLK)
   57 /*
   58  * R0E, R1E, R0ED, R1ED modes
   59  * double-edge data, retime data with clk
   60  */
   61 #define DE_IO           (RT | DOUBLE_EDGE)
   62 /*
   63  * CIV0, CIV1 modes with inverted clock
   64  * Retiming the clk pins will park clock & reduce the noise within the core.
   65  */
   66 #define ICLK            (RT | CLKNOTDATA | INVERTCLK)
   67 /*
   68  * CLK0, CLK1 modes with non-inverted clock
   69  * Retiming the clk pins will park clock & reduce the noise within the core.
   70  */
   71 #define NICLK           (RT | CLKNOTDATA)
   72 #endif /* _ST_PINCFG_H_ */

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