Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/stm32h743-pinctrl.dtsi
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1 /* 2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43 #include <dt-bindings/pinctrl/stm32-pinfunc.h> 44 45 / { 46 soc { 47 pin-controller { 48 #address-cells = <1>; 49 #size-cells = <1>; 50 compatible = "st,stm32h743-pinctrl"; 51 ranges = <0 0x58020000 0x3000>; 52 interrupt-parent = <&exti>; 53 st,syscfg = <&syscfg 0x8>; 54 pins-are-numbered; 55 56 gpioa: gpio@58020000 { 57 gpio-controller; 58 #gpio-cells = <2>; 59 reg = <0x0 0x400>; 60 clocks = <&rcc GPIOA_CK>; 61 st,bank-name = "GPIOA"; 62 interrupt-controller; 63 #interrupt-cells = <2>; 64 }; 65 66 gpiob: gpio@58020400 { 67 gpio-controller; 68 #gpio-cells = <2>; 69 reg = <0x400 0x400>; 70 clocks = <&rcc GPIOB_CK>; 71 st,bank-name = "GPIOB"; 72 interrupt-controller; 73 #interrupt-cells = <2>; 74 }; 75 76 gpioc: gpio@58020800 { 77 gpio-controller; 78 #gpio-cells = <2>; 79 reg = <0x800 0x400>; 80 clocks = <&rcc GPIOC_CK>; 81 st,bank-name = "GPIOC"; 82 interrupt-controller; 83 #interrupt-cells = <2>; 84 }; 85 86 gpiod: gpio@58020c00 { 87 gpio-controller; 88 #gpio-cells = <2>; 89 reg = <0xc00 0x400>; 90 clocks = <&rcc GPIOD_CK>; 91 st,bank-name = "GPIOD"; 92 interrupt-controller; 93 #interrupt-cells = <2>; 94 }; 95 96 gpioe: gpio@58021000 { 97 gpio-controller; 98 #gpio-cells = <2>; 99 reg = <0x1000 0x400>; 100 clocks = <&rcc GPIOE_CK>; 101 st,bank-name = "GPIOE"; 102 interrupt-controller; 103 #interrupt-cells = <2>; 104 }; 105 106 gpiof: gpio@58021400 { 107 gpio-controller; 108 #gpio-cells = <2>; 109 reg = <0x1400 0x400>; 110 clocks = <&rcc GPIOF_CK>; 111 st,bank-name = "GPIOF"; 112 interrupt-controller; 113 #interrupt-cells = <2>; 114 }; 115 116 gpiog: gpio@58021800 { 117 gpio-controller; 118 #gpio-cells = <2>; 119 reg = <0x1800 0x400>; 120 clocks = <&rcc GPIOG_CK>; 121 st,bank-name = "GPIOG"; 122 interrupt-controller; 123 #interrupt-cells = <2>; 124 }; 125 126 gpioh: gpio@58021c00 { 127 gpio-controller; 128 #gpio-cells = <2>; 129 reg = <0x1c00 0x400>; 130 clocks = <&rcc GPIOH_CK>; 131 st,bank-name = "GPIOH"; 132 interrupt-controller; 133 #interrupt-cells = <2>; 134 }; 135 136 gpioi: gpio@58022000 { 137 gpio-controller; 138 #gpio-cells = <2>; 139 reg = <0x2000 0x400>; 140 clocks = <&rcc GPIOI_CK>; 141 st,bank-name = "GPIOI"; 142 interrupt-controller; 143 #interrupt-cells = <2>; 144 }; 145 146 gpioj: gpio@58022400 { 147 gpio-controller; 148 #gpio-cells = <2>; 149 reg = <0x2400 0x400>; 150 clocks = <&rcc GPIOJ_CK>; 151 st,bank-name = "GPIOJ"; 152 interrupt-controller; 153 #interrupt-cells = <2>; 154 }; 155 156 gpiok: gpio@58022800 { 157 gpio-controller; 158 #gpio-cells = <2>; 159 reg = <0x2800 0x400>; 160 clocks = <&rcc GPIOK_CK>; 161 st,bank-name = "GPIOK"; 162 interrupt-controller; 163 #interrupt-cells = <2>; 164 }; 165 166 i2c1_pins_a: i2c1-0 { 167 pins { 168 pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */ 169 <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */ 170 bias-disable; 171 drive-open-drain; 172 slew-rate = <0>; 173 }; 174 }; 175 176 ethernet_rmii: rmii-0 { 177 pins { 178 pinmux = <STM32_PINMUX('G', 11, AF11)>, 179 <STM32_PINMUX('G', 13, AF11)>, 180 <STM32_PINMUX('G', 12, AF11)>, 181 <STM32_PINMUX('C', 4, AF11)>, 182 <STM32_PINMUX('C', 5, AF11)>, 183 <STM32_PINMUX('A', 7, AF11)>, 184 <STM32_PINMUX('C', 1, AF11)>, 185 <STM32_PINMUX('A', 2, AF11)>, 186 <STM32_PINMUX('A', 1, AF11)>; 187 slew-rate = <2>; 188 }; 189 }; 190 191 sdmmc1_b4_pins_a: sdmmc1-b4-0 { 192 pins { 193 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 194 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 195 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 196 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ 197 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */ 198 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 199 slew-rate = <3>; 200 drive-push-pull; 201 bias-disable; 202 }; 203 }; 204 205 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { 206 pins1 { 207 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 208 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 209 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 210 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ 211 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 212 slew-rate = <3>; 213 drive-push-pull; 214 bias-disable; 215 }; 216 pins2{ 217 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 218 slew-rate = <3>; 219 drive-open-drain; 220 bias-disable; 221 }; 222 }; 223 224 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { 225 pins { 226 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ 227 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ 228 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ 229 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ 230 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ 231 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ 232 }; 233 }; 234 235 sdmmc1_dir_pins_a: sdmmc1-dir-0 { 236 pins1 { 237 pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */ 238 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ 239 <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */ 240 slew-rate = <3>; 241 drive-push-pull; 242 bias-pull-up; 243 }; 244 pins2{ 245 pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */ 246 bias-pull-up; 247 }; 248 }; 249 250 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { 251 pins { 252 pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */ 253 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ 254 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ 255 <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */ 256 }; 257 }; 258 259 usart1_pins: usart1-0 { 260 pins1 { 261 pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */ 262 bias-disable; 263 drive-push-pull; 264 slew-rate = <0>; 265 }; 266 pins2 { 267 pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */ 268 bias-disable; 269 }; 270 }; 271 272 usart2_pins: usart2-0 { 273 pins1 { 274 pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */ 275 bias-disable; 276 drive-push-pull; 277 slew-rate = <0>; 278 }; 279 pins2 { 280 pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ 281 bias-disable; 282 }; 283 }; 284 285 usbotg_hs_pins_a: usbotg-hs-0 { 286 pins { 287 pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */ 288 <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */ 289 <STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */ 290 <STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */ 291 <STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */ 292 <STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */ 293 <STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */ 294 <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */ 295 <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */ 296 <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */ 297 <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */ 298 <STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */ 299 bias-disable; 300 drive-push-pull; 301 slew-rate = <2>; 302 }; 303 }; 304 }; 305 }; 306 };
Cache object: c8f459bc49f513a498502da5cb97c96c
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