Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/stm32mp131.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/clock/stm32mp13-clks.h> 8 #include <dt-bindings/reset/stm32mp13-resets.h> 9 10 / { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 compatible = "arm,cortex-a7"; 20 device_type = "cpu"; 21 reg = <0>; 22 }; 23 }; 24 25 arm-pmu { 26 compatible = "arm,cortex-a7-pmu"; 27 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 28 interrupt-affinity = <&cpu0>; 29 interrupt-parent = <&intc>; 30 }; 31 32 firmware { 33 optee { 34 method = "smc"; 35 compatible = "linaro,optee-tz"; 36 }; 37 38 scmi: scmi { 39 compatible = "linaro,scmi-optee"; 40 #address-cells = <1>; 41 #size-cells = <0>; 42 linaro,optee-channel-id = <0>; 43 shmem = <&scmi_shm>; 44 45 scmi_clk: protocol@14 { 46 reg = <0x14>; 47 #clock-cells = <1>; 48 }; 49 50 scmi_reset: protocol@16 { 51 reg = <0x16>; 52 #reset-cells = <1>; 53 }; 54 }; 55 }; 56 57 intc: interrupt-controller@a0021000 { 58 compatible = "arm,cortex-a7-gic"; 59 #interrupt-cells = <3>; 60 interrupt-controller; 61 reg = <0xa0021000 0x1000>, 62 <0xa0022000 0x2000>; 63 }; 64 65 psci { 66 compatible = "arm,psci-1.0"; 67 method = "smc"; 68 }; 69 70 timer { 71 compatible = "arm,armv7-timer"; 72 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 73 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 74 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 75 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 76 interrupt-parent = <&intc>; 77 always-on; 78 }; 79 80 soc { 81 compatible = "simple-bus"; 82 #address-cells = <1>; 83 #size-cells = <1>; 84 interrupt-parent = <&intc>; 85 ranges; 86 87 scmi_sram: sram@2ffff000 { 88 compatible = "mmio-sram"; 89 reg = <0x2ffff000 0x1000>; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 ranges = <0 0x2ffff000 0x1000>; 93 94 scmi_shm: scmi-sram@0 { 95 compatible = "arm,scmi-shmem"; 96 reg = <0 0x80>; 97 }; 98 }; 99 100 uart4: serial@40010000 { 101 compatible = "st,stm32h7-uart"; 102 reg = <0x40010000 0x400>; 103 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 104 clocks = <&rcc UART4_K>; 105 resets = <&rcc UART4_R>; 106 status = "disabled"; 107 }; 108 109 dma1: dma-controller@48000000 { 110 compatible = "st,stm32-dma"; 111 reg = <0x48000000 0x400>; 112 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 120 clocks = <&rcc DMA1>; 121 resets = <&rcc DMA1_R>; 122 #dma-cells = <4>; 123 st,mem2mem; 124 dma-requests = <8>; 125 }; 126 127 dma2: dma-controller@48001000 { 128 compatible = "st,stm32-dma"; 129 reg = <0x48001000 0x400>; 130 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&rcc DMA2>; 139 resets = <&rcc DMA2_R>; 140 #dma-cells = <4>; 141 st,mem2mem; 142 dma-requests = <8>; 143 }; 144 145 dmamux1: dma-router@48002000 { 146 compatible = "st,stm32h7-dmamux"; 147 reg = <0x48002000 0x40>; 148 clocks = <&rcc DMAMUX1>; 149 resets = <&rcc DMAMUX1_R>; 150 #dma-cells = <3>; 151 dma-masters = <&dma1 &dma2>; 152 dma-requests = <128>; 153 dma-channels = <16>; 154 }; 155 156 rcc: rcc@50000000 { 157 compatible = "st,stm32mp13-rcc", "syscon"; 158 reg = <0x50000000 0x1000>; 159 #clock-cells = <1>; 160 #reset-cells = <1>; 161 clock-names = "hse", "hsi", "csi", "lse", "lsi"; 162 clocks = <&scmi_clk CK_SCMI_HSE>, 163 <&scmi_clk CK_SCMI_HSI>, 164 <&scmi_clk CK_SCMI_CSI>, 165 <&scmi_clk CK_SCMI_LSE>, 166 <&scmi_clk CK_SCMI_LSI>; 167 }; 168 169 exti: interrupt-controller@5000d000 { 170 compatible = "st,stm32mp13-exti", "syscon"; 171 interrupt-controller; 172 #interrupt-cells = <2>; 173 reg = <0x5000d000 0x400>; 174 }; 175 176 syscfg: syscon@50020000 { 177 compatible = "st,stm32mp157-syscfg", "syscon"; 178 reg = <0x50020000 0x400>; 179 clocks = <&rcc SYSCFG>; 180 }; 181 182 mdma: dma-controller@58000000 { 183 compatible = "st,stm32h7-mdma"; 184 reg = <0x58000000 0x1000>; 185 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&rcc MDMA>; 187 #dma-cells = <5>; 188 dma-channels = <32>; 189 dma-requests = <48>; 190 }; 191 192 sdmmc1: mmc@58005000 { 193 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 194 arm,primecell-periphid = <0x20253180>; 195 reg = <0x58005000 0x1000>, <0x58006000 0x1000>; 196 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 197 interrupt-names = "cmd_irq"; 198 clocks = <&rcc SDMMC1_K>; 199 clock-names = "apb_pclk"; 200 resets = <&rcc SDMMC1_R>; 201 cap-sd-highspeed; 202 cap-mmc-highspeed; 203 max-frequency = <130000000>; 204 status = "disabled"; 205 }; 206 207 sdmmc2: mmc@58007000 { 208 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; 209 arm,primecell-periphid = <0x20253180>; 210 reg = <0x58007000 0x1000>, <0x58008000 0x1000>; 211 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 212 interrupt-names = "cmd_irq"; 213 clocks = <&rcc SDMMC2_K>; 214 clock-names = "apb_pclk"; 215 resets = <&rcc SDMMC2_R>; 216 cap-sd-highspeed; 217 cap-mmc-highspeed; 218 max-frequency = <130000000>; 219 status = "disabled"; 220 }; 221 222 iwdg2: watchdog@5a002000 { 223 compatible = "st,stm32mp1-iwdg"; 224 reg = <0x5a002000 0x400>; 225 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; 226 clock-names = "pclk", "lsi"; 227 status = "disabled"; 228 }; 229 230 rtc: rtc@5c004000 { 231 compatible = "st,stm32mp1-rtc"; 232 reg = <0x5c004000 0x400>; 233 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&scmi_clk CK_SCMI_RTCAPB>, 235 <&scmi_clk CK_SCMI_RTC>; 236 clock-names = "pclk", "rtc_ck"; 237 status = "disabled"; 238 }; 239 240 bsec: efuse@5c005000 { 241 compatible = "st,stm32mp15-bsec"; 242 reg = <0x5c005000 0x400>; 243 #address-cells = <1>; 244 #size-cells = <1>; 245 246 part_number_otp: part_number_otp@4 { 247 reg = <0x4 0x2>; 248 }; 249 ts_cal1: calib@5c { 250 reg = <0x5c 0x2>; 251 }; 252 ts_cal2: calib@5e { 253 reg = <0x5e 0x2>; 254 }; 255 }; 256 257 /* 258 * Break node order to solve dependency probe issue between 259 * pinctrl and exti. 260 */ 261 pinctrl: pinctrl@50002000 { 262 #address-cells = <1>; 263 #size-cells = <1>; 264 compatible = "st,stm32mp135-pinctrl"; 265 ranges = <0 0x50002000 0x8400>; 266 interrupt-parent = <&exti>; 267 st,syscfg = <&exti 0x60 0xff>; 268 pins-are-numbered; 269 270 gpioa: gpio@50002000 { 271 gpio-controller; 272 #gpio-cells = <2>; 273 interrupt-controller; 274 #interrupt-cells = <2>; 275 reg = <0x0 0x400>; 276 clocks = <&rcc GPIOA>; 277 st,bank-name = "GPIOA"; 278 ngpios = <16>; 279 gpio-ranges = <&pinctrl 0 0 16>; 280 }; 281 282 gpiob: gpio@50003000 { 283 gpio-controller; 284 #gpio-cells = <2>; 285 interrupt-controller; 286 #interrupt-cells = <2>; 287 reg = <0x1000 0x400>; 288 clocks = <&rcc GPIOB>; 289 st,bank-name = "GPIOB"; 290 ngpios = <16>; 291 gpio-ranges = <&pinctrl 0 16 16>; 292 }; 293 294 gpioc: gpio@50004000 { 295 gpio-controller; 296 #gpio-cells = <2>; 297 interrupt-controller; 298 #interrupt-cells = <2>; 299 reg = <0x2000 0x400>; 300 clocks = <&rcc GPIOC>; 301 st,bank-name = "GPIOC"; 302 ngpios = <16>; 303 gpio-ranges = <&pinctrl 0 32 16>; 304 }; 305 306 gpiod: gpio@50005000 { 307 gpio-controller; 308 #gpio-cells = <2>; 309 interrupt-controller; 310 #interrupt-cells = <2>; 311 reg = <0x3000 0x400>; 312 clocks = <&rcc GPIOD>; 313 st,bank-name = "GPIOD"; 314 ngpios = <16>; 315 gpio-ranges = <&pinctrl 0 48 16>; 316 }; 317 318 gpioe: gpio@50006000 { 319 gpio-controller; 320 #gpio-cells = <2>; 321 interrupt-controller; 322 #interrupt-cells = <2>; 323 reg = <0x4000 0x400>; 324 clocks = <&rcc GPIOE>; 325 st,bank-name = "GPIOE"; 326 ngpios = <16>; 327 gpio-ranges = <&pinctrl 0 64 16>; 328 }; 329 330 gpiof: gpio@50007000 { 331 gpio-controller; 332 #gpio-cells = <2>; 333 interrupt-controller; 334 #interrupt-cells = <2>; 335 reg = <0x5000 0x400>; 336 clocks = <&rcc GPIOF>; 337 st,bank-name = "GPIOF"; 338 ngpios = <16>; 339 gpio-ranges = <&pinctrl 0 80 16>; 340 }; 341 342 gpiog: gpio@50008000 { 343 gpio-controller; 344 #gpio-cells = <2>; 345 interrupt-controller; 346 #interrupt-cells = <2>; 347 reg = <0x6000 0x400>; 348 clocks = <&rcc GPIOG>; 349 st,bank-name = "GPIOG"; 350 ngpios = <16>; 351 gpio-ranges = <&pinctrl 0 96 16>; 352 }; 353 354 gpioh: gpio@50009000 { 355 gpio-controller; 356 #gpio-cells = <2>; 357 interrupt-controller; 358 #interrupt-cells = <2>; 359 reg = <0x7000 0x400>; 360 clocks = <&rcc GPIOH>; 361 st,bank-name = "GPIOH"; 362 ngpios = <15>; 363 gpio-ranges = <&pinctrl 0 112 15>; 364 }; 365 366 gpioi: gpio@5000a000 { 367 gpio-controller; 368 #gpio-cells = <2>; 369 interrupt-controller; 370 #interrupt-cells = <2>; 371 reg = <0x8000 0x400>; 372 clocks = <&rcc GPIOI>; 373 st,bank-name = "GPIOI"; 374 ngpios = <8>; 375 gpio-ranges = <&pinctrl 0 128 8>; 376 }; 377 }; 378 }; 379 };
Cache object: 818448e339564fc2f718451b2396abc0
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