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sys/contrib/device-tree/src/arm/stm32mp15-pinctrl.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6 #include <dt-bindings/pinctrl/stm32-pinfunc.h> 7 8 &pinctrl { 9 adc1_in6_pins_a: adc1-in6-0 { 10 pins { 11 pinmux = <STM32_PINMUX('F', 12, ANALOG)>; 12 }; 13 }; 14 15 adc12_ain_pins_a: adc12-ain-0 { 16 pins { 17 pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */ 18 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ 19 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */ 20 <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */ 21 }; 22 }; 23 24 adc12_ain_pins_b: adc12-ain-1 { 25 pins { 26 pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ 27 <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */ 28 }; 29 }; 30 31 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { 32 pins { 33 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */ 34 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */ 35 }; 36 }; 37 38 cec_pins_a: cec-0 { 39 pins { 40 pinmux = <STM32_PINMUX('A', 15, AF4)>; 41 bias-disable; 42 drive-open-drain; 43 slew-rate = <0>; 44 }; 45 }; 46 47 cec_sleep_pins_a: cec-sleep-0 { 48 pins { 49 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */ 50 }; 51 }; 52 53 cec_pins_b: cec-1 { 54 pins { 55 pinmux = <STM32_PINMUX('B', 6, AF5)>; 56 bias-disable; 57 drive-open-drain; 58 slew-rate = <0>; 59 }; 60 }; 61 62 cec_sleep_pins_b: cec-sleep-1 { 63 pins { 64 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */ 65 }; 66 }; 67 68 dac_ch1_pins_a: dac-ch1-0 { 69 pins { 70 pinmux = <STM32_PINMUX('A', 4, ANALOG)>; 71 }; 72 }; 73 74 dac_ch2_pins_a: dac-ch2-0 { 75 pins { 76 pinmux = <STM32_PINMUX('A', 5, ANALOG)>; 77 }; 78 }; 79 80 dcmi_pins_a: dcmi-0 { 81 pins { 82 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ 83 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ 84 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ 85 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */ 86 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ 87 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ 88 <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */ 89 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ 90 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ 91 <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ 92 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ 93 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ 94 <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */ 95 <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */ 96 <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */ 97 bias-disable; 98 }; 99 }; 100 101 dcmi_sleep_pins_a: dcmi-sleep-0 { 102 pins { 103 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ 104 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ 105 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ 106 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */ 107 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ 108 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ 109 <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */ 110 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ 111 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ 112 <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ 113 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ 114 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ 115 <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */ 116 <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */ 117 <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */ 118 }; 119 }; 120 121 dcmi_pins_b: dcmi-1 { 122 pins { 123 pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ 124 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ 125 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ 126 <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */ 127 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ 128 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ 129 <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ 130 <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */ 131 <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */ 132 <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */ 133 <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */ 134 bias-disable; 135 }; 136 }; 137 138 dcmi_sleep_pins_b: dcmi-sleep-1 { 139 pins { 140 pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ 141 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ 142 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ 143 <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */ 144 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ 145 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ 146 <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ 147 <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */ 148 <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */ 149 <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */ 150 <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */ 151 }; 152 }; 153 154 dcmi_pins_c: dcmi-2 { 155 pins { 156 pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ 157 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ 158 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ 159 <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */ 160 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ 161 <STM32_PINMUX('E', 0, AF13)>,/* DCMI_D2 */ 162 <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ 163 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ 164 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ 165 <STM32_PINMUX('I', 6, AF13)>,/* DCMI_D6 */ 166 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ 167 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ 168 <STM32_PINMUX('H', 7, AF13)>;/* DCMI_D9 */ 169 bias-pull-up; 170 }; 171 }; 172 173 dcmi_sleep_pins_c: dcmi-sleep-2 { 174 pins { 175 pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ 176 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ 177 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ 178 <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */ 179 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ 180 <STM32_PINMUX('E', 0, ANALOG)>,/* DCMI_D2 */ 181 <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ 182 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ 183 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ 184 <STM32_PINMUX('I', 6, ANALOG)>,/* DCMI_D6 */ 185 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ 186 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ 187 <STM32_PINMUX('H', 7, ANALOG)>;/* DCMI_D9 */ 188 }; 189 }; 190 191 ethernet0_rgmii_pins_a: rgmii-0 { 192 pins1 { 193 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 194 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 195 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ 196 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 197 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 198 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 199 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 200 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 201 bias-disable; 202 drive-push-pull; 203 slew-rate = <2>; 204 }; 205 pins2 { 206 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 207 bias-disable; 208 drive-push-pull; 209 slew-rate = <0>; 210 }; 211 pins3 { 212 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 213 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 214 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ 215 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ 216 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 217 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 218 bias-disable; 219 }; 220 }; 221 222 ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { 223 pins1 { 224 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 225 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 226 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ 227 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 228 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 229 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 230 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 231 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 232 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 233 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 234 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 235 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */ 236 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ 237 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 238 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 239 }; 240 }; 241 242 ethernet0_rgmii_pins_b: rgmii-1 { 243 pins1 { 244 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 245 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 246 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ 247 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 248 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 249 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 250 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 251 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 252 bias-disable; 253 drive-push-pull; 254 slew-rate = <2>; 255 }; 256 pins2 { 257 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 258 bias-disable; 259 drive-push-pull; 260 slew-rate = <0>; 261 }; 262 pins3 { 263 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 264 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 265 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ 266 <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */ 267 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 268 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 269 bias-disable; 270 }; 271 }; 272 273 ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { 274 pins1 { 275 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 276 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 277 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ 278 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 279 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 280 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 281 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 282 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 283 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 284 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 285 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 286 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ 287 <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */ 288 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 289 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 290 }; 291 }; 292 293 ethernet0_rgmii_pins_c: rgmii-2 { 294 pins1 { 295 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ 296 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ 297 <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */ 298 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ 299 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ 300 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ 301 <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */ 302 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ 303 bias-disable; 304 drive-push-pull; 305 slew-rate = <2>; 306 }; 307 pins2 { 308 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ 309 bias-disable; 310 drive-push-pull; 311 slew-rate = <0>; 312 }; 313 pins3 { 314 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ 315 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ 316 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ 317 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ 318 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ 319 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ 320 bias-disable; 321 }; 322 }; 323 324 ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { 325 pins1 { 326 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ 327 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ 328 <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */ 329 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ 330 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ 331 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ 332 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ 333 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ 334 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ 335 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ 336 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ 337 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ 338 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ 339 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ 340 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ 341 }; 342 }; 343 344 ethernet0_rmii_pins_a: rmii-0 { 345 pins1 { 346 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ 347 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ 348 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ 349 <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ 350 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ 351 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ 352 bias-disable; 353 drive-push-pull; 354 slew-rate = <2>; 355 }; 356 pins2 { 357 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ 358 <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ 359 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ 360 bias-disable; 361 }; 362 }; 363 364 ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { 365 pins1 { 366 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ 367 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ 368 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ 369 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ 370 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ 371 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ 372 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ 373 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ 374 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ 375 }; 376 }; 377 378 ethernet0_rmii_pins_b: rmii-1 { 379 pins1 { 380 pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */ 381 <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */ 382 <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */ 383 <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */ 384 bias-disable; 385 drive-push-pull; 386 slew-rate = <1>; 387 }; 388 pins2 { 389 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */ 390 bias-disable; 391 drive-push-pull; 392 slew-rate = <0>; 393 }; 394 pins3 { 395 pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */ 396 <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */ 397 <STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */ 398 bias-disable; 399 }; 400 pins4 { 401 pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */ 402 }; 403 }; 404 405 ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { 406 pins1 { 407 pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ 408 <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */ 409 <STM32_PINMUX('B', 5, ANALOG)>, /* ETH1_CLK */ 410 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */ 411 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ 412 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */ 413 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */ 414 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */ 415 <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */ 416 }; 417 }; 418 419 ethernet0_rmii_pins_c: rmii-2 { 420 pins1 { 421 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ 422 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ 423 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ 424 <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */ 425 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ 426 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ 427 bias-disable; 428 drive-push-pull; 429 slew-rate = <2>; 430 }; 431 pins2 { 432 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ 433 <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ 434 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ 435 bias-disable; 436 }; 437 }; 438 439 ethernet0_rmii_sleep_pins_c: rmii-sleep-2 { 440 pins1 { 441 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ 442 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ 443 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ 444 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ 445 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ 446 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ 447 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ 448 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ 449 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ 450 }; 451 }; 452 453 fmc_pins_a: fmc-0 { 454 pins1 { 455 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ 456 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ 457 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */ 458 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */ 459 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ 460 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ 461 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ 462 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ 463 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ 464 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ 465 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ 466 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ 467 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */ 468 bias-disable; 469 drive-push-pull; 470 slew-rate = <1>; 471 }; 472 pins2 { 473 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */ 474 bias-pull-up; 475 }; 476 }; 477 478 fmc_sleep_pins_a: fmc-sleep-0 { 479 pins { 480 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ 481 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ 482 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */ 483 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */ 484 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ 485 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ 486 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ 487 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ 488 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ 489 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ 490 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ 491 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ 492 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */ 493 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */ 494 }; 495 }; 496 497 fmc_pins_b: fmc-1 { 498 pins { 499 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ 500 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ 501 <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */ 502 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ 503 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ 504 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ 505 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ 506 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ 507 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ 508 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ 509 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ 510 <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */ 511 <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */ 512 <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */ 513 <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */ 514 <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */ 515 <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */ 516 <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */ 517 <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */ 518 <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */ 519 <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */ 520 bias-disable; 521 drive-push-pull; 522 slew-rate = <3>; 523 }; 524 }; 525 526 fmc_sleep_pins_b: fmc-sleep-1 { 527 pins { 528 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ 529 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ 530 <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */ 531 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ 532 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ 533 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ 534 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ 535 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ 536 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ 537 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ 538 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ 539 <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */ 540 <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */ 541 <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */ 542 <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */ 543 <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */ 544 <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */ 545 <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */ 546 <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */ 547 <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */ 548 <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */ 549 }; 550 }; 551 552 i2c1_pins_a: i2c1-0 { 553 pins { 554 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ 555 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ 556 bias-disable; 557 drive-open-drain; 558 slew-rate = <0>; 559 }; 560 }; 561 562 i2c1_sleep_pins_a: i2c1-sleep-0 { 563 pins { 564 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ 565 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ 566 }; 567 }; 568 569 i2c1_pins_b: i2c1-1 { 570 pins { 571 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ 572 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ 573 bias-disable; 574 drive-open-drain; 575 slew-rate = <0>; 576 }; 577 }; 578 579 i2c1_sleep_pins_b: i2c1-sleep-1 { 580 pins { 581 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ 582 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ 583 }; 584 }; 585 586 i2c2_pins_a: i2c2-0 { 587 pins { 588 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ 589 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 590 bias-disable; 591 drive-open-drain; 592 slew-rate = <0>; 593 }; 594 }; 595 596 i2c2_sleep_pins_a: i2c2-sleep-0 { 597 pins { 598 pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */ 599 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 600 }; 601 }; 602 603 i2c2_pins_b1: i2c2-1 { 604 pins { 605 pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 606 bias-disable; 607 drive-open-drain; 608 slew-rate = <0>; 609 }; 610 }; 611 612 i2c2_sleep_pins_b1: i2c2-sleep-1 { 613 pins { 614 pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 615 }; 616 }; 617 618 i2c2_pins_c: i2c2-2 { 619 pins { 620 pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */ 621 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ 622 bias-disable; 623 drive-open-drain; 624 slew-rate = <0>; 625 }; 626 }; 627 628 i2c2_pins_sleep_c: i2c2-sleep-2 { 629 pins { 630 pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */ 631 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ 632 }; 633 }; 634 635 i2c5_pins_a: i2c5-0 { 636 pins { 637 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */ 638 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */ 639 bias-disable; 640 drive-open-drain; 641 slew-rate = <0>; 642 }; 643 }; 644 645 i2c5_sleep_pins_a: i2c5-sleep-0 { 646 pins { 647 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */ 648 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */ 649 650 }; 651 }; 652 653 i2c5_pins_b: i2c5-1 { 654 pins { 655 pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */ 656 <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */ 657 bias-disable; 658 drive-open-drain; 659 slew-rate = <0>; 660 }; 661 }; 662 663 i2c5_sleep_pins_b: i2c5-sleep-1 { 664 pins { 665 pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */ 666 <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */ 667 }; 668 }; 669 670 i2s2_pins_a: i2s2-0 { 671 pins { 672 pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ 673 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */ 674 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */ 675 slew-rate = <1>; 676 drive-push-pull; 677 bias-disable; 678 }; 679 }; 680 681 i2s2_sleep_pins_a: i2s2-sleep-0 { 682 pins { 683 pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */ 684 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */ 685 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */ 686 }; 687 }; 688 689 ltdc_pins_a: ltdc-0 { 690 pins { 691 pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ 692 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ 693 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ 694 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */ 695 <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */ 696 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ 697 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ 698 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ 699 <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */ 700 <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */ 701 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ 702 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ 703 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ 704 <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */ 705 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ 706 <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */ 707 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ 708 <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */ 709 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */ 710 <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */ 711 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ 712 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ 713 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ 714 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ 715 <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */ 716 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ 717 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ 718 <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */ 719 bias-disable; 720 drive-push-pull; 721 slew-rate = <1>; 722 }; 723 }; 724 725 ltdc_sleep_pins_a: ltdc-sleep-0 { 726 pins { 727 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ 728 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ 729 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ 730 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */ 731 <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */ 732 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ 733 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ 734 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ 735 <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */ 736 <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */ 737 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ 738 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ 739 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ 740 <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */ 741 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ 742 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */ 743 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ 744 <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */ 745 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */ 746 <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */ 747 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ 748 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ 749 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ 750 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ 751 <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */ 752 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ 753 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ 754 <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */ 755 }; 756 }; 757 758 ltdc_pins_b: ltdc-1 { 759 pins { 760 pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ 761 <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ 762 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ 763 <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */ 764 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ 765 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ 766 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ 767 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ 768 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ 769 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ 770 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */ 771 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ 772 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ 773 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ 774 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ 775 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ 776 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ 777 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ 778 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ 779 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ 780 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ 781 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ 782 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ 783 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */ 784 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ 785 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ 786 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ 787 <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */ 788 bias-disable; 789 drive-push-pull; 790 slew-rate = <1>; 791 }; 792 }; 793 794 ltdc_sleep_pins_b: ltdc-sleep-1 { 795 pins { 796 pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */ 797 <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */ 798 <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */ 799 <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */ 800 <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */ 801 <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */ 802 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */ 803 <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */ 804 <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */ 805 <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */ 806 <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */ 807 <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */ 808 <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */ 809 <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */ 810 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */ 811 <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */ 812 <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */ 813 <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */ 814 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */ 815 <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */ 816 <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */ 817 <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */ 818 <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */ 819 <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */ 820 <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */ 821 <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */ 822 <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */ 823 <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */ 824 }; 825 }; 826 827 ltdc_pins_c: ltdc-2 { 828 pins1 { 829 pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */ 830 <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */ 831 <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */ 832 <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */ 833 <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */ 834 <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */ 835 <STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */ 836 <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */ 837 <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */ 838 <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */ 839 <STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */ 840 <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */ 841 <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */ 842 <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */ 843 <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */ 844 <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */ 845 <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */ 846 <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */ 847 <STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */ 848 <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */ 849 <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */ 850 bias-disable; 851 drive-push-pull; 852 slew-rate = <0>; 853 }; 854 pins2 { 855 pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */ 856 bias-disable; 857 drive-push-pull; 858 slew-rate = <1>; 859 }; 860 }; 861 862 ltdc_sleep_pins_c: ltdc-sleep-2 { 863 pins1 { 864 pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */ 865 <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */ 866 <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */ 867 <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */ 868 <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */ 869 <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */ 870 <STM32_PINMUX('E', 11, ANALOG)>, /* LTDC_G3 */ 871 <STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */ 872 <STM32_PINMUX('E', 13, ANALOG)>, /* LTDC_DE */ 873 <STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */ 874 <STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G5 */ 875 <STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */ 876 <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */ 877 <STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */ 878 <STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */ 879 <STM32_PINMUX('H', 15, ANALOG)>, /* LTDC_G4 */ 880 <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */ 881 <STM32_PINMUX('I', 5, ANALOG)>, /* LTDC_B5 */ 882 <STM32_PINMUX('I', 6, ANALOG)>, /* LTDC_B6 */ 883 <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */ 884 <STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */ 885 <STM32_PINMUX('E', 14, ANALOG)>; /* LTDC_CLK */ 886 }; 887 }; 888 889 ltdc_pins_d: ltdc-3 { 890 pins1 { 891 pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */ 892 bias-disable; 893 drive-push-pull; 894 slew-rate = <3>; 895 }; 896 pins2 { 897 pinmux = <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ 898 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ 899 <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */ 900 <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */ 901 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ 902 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ 903 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ 904 <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */ 905 <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */ 906 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ 907 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ 908 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ 909 <STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */ 910 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ 911 <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */ 912 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ 913 <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */ 914 <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */ 915 <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */ 916 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ 917 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ 918 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ 919 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ 920 <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */ 921 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ 922 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ 923 <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */ 924 bias-disable; 925 drive-push-pull; 926 slew-rate = <2>; 927 }; 928 }; 929 930 ltdc_sleep_pins_d: ltdc-sleep-3 { 931 pins { 932 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ 933 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ 934 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ 935 <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */ 936 <STM32_PINMUX('G', 13, ANALOG)>, /* LCD_R0 */ 937 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ 938 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ 939 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ 940 <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */ 941 <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */ 942 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ 943 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ 944 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ 945 <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */ 946 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ 947 <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */ 948 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ 949 <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */ 950 <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */ 951 <STM32_PINMUX('G', 8, ANALOG)>, /* LCD_G7 */ 952 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ 953 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ 954 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ 955 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ 956 <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */ 957 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ 958 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ 959 <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */ 960 }; 961 }; 962 963 mco1_pins_a: mco1-0 { 964 pins { 965 pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */ 966 bias-disable; 967 drive-push-pull; 968 slew-rate = <1>; 969 }; 970 }; 971 972 mco1_sleep_pins_a: mco1-sleep-0 { 973 pins { 974 pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */ 975 }; 976 }; 977 978 mco2_pins_a: mco2-0 { 979 pins { 980 pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */ 981 bias-disable; 982 drive-push-pull; 983 slew-rate = <2>; 984 }; 985 }; 986 987 mco2_sleep_pins_a: mco2-sleep-0 { 988 pins { 989 pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */ 990 }; 991 }; 992 993 m_can1_pins_a: m-can1-0 { 994 pins1 { 995 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ 996 slew-rate = <1>; 997 drive-push-pull; 998 bias-disable; 999 }; 1000 pins2 { 1001 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */ 1002 bias-disable; 1003 }; 1004 }; 1005 1006 m_can1_sleep_pins_a: m_can1-sleep-0 { 1007 pins { 1008 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ 1009 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */ 1010 }; 1011 }; 1012 1013 m_can1_pins_b: m-can1-1 { 1014 pins1 { 1015 pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */ 1016 slew-rate = <1>; 1017 drive-push-pull; 1018 bias-disable; 1019 }; 1020 pins2 { 1021 pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */ 1022 bias-disable; 1023 }; 1024 }; 1025 1026 m_can1_sleep_pins_b: m_can1-sleep-1 { 1027 pins { 1028 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */ 1029 <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */ 1030 }; 1031 }; 1032 1033 m_can1_pins_c: m-can1-2 { 1034 pins1 { 1035 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ 1036 slew-rate = <1>; 1037 drive-push-pull; 1038 bias-disable; 1039 }; 1040 pins2 { 1041 pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */ 1042 bias-disable; 1043 }; 1044 }; 1045 1046 m_can1_sleep_pins_c: m_can1-sleep-2 { 1047 pins { 1048 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ 1049 <STM32_PINMUX('H', 14, ANALOG)>; /* CAN1_RX */ 1050 }; 1051 }; 1052 1053 m_can2_pins_a: m-can2-0 { 1054 pins1 { 1055 pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ 1056 slew-rate = <1>; 1057 drive-push-pull; 1058 bias-disable; 1059 }; 1060 pins2 { 1061 pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */ 1062 bias-disable; 1063 }; 1064 }; 1065 1066 m_can2_sleep_pins_a: m_can2-sleep-0 { 1067 pins { 1068 pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */ 1069 <STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */ 1070 }; 1071 }; 1072 1073 pwm1_pins_a: pwm1-0 { 1074 pins { 1075 pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */ 1076 <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */ 1077 <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */ 1078 bias-pull-down; 1079 drive-push-pull; 1080 slew-rate = <0>; 1081 }; 1082 }; 1083 1084 pwm1_sleep_pins_a: pwm1-sleep-0 { 1085 pins { 1086 pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */ 1087 <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */ 1088 <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */ 1089 }; 1090 }; 1091 1092 pwm1_pins_b: pwm1-1 { 1093 pins { 1094 pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */ 1095 bias-pull-down; 1096 drive-push-pull; 1097 slew-rate = <0>; 1098 }; 1099 }; 1100 1101 pwm1_sleep_pins_b: pwm1-sleep-1 { 1102 pins { 1103 pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */ 1104 }; 1105 }; 1106 1107 pwm2_pins_a: pwm2-0 { 1108 pins { 1109 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ 1110 bias-pull-down; 1111 drive-push-pull; 1112 slew-rate = <0>; 1113 }; 1114 }; 1115 1116 pwm2_sleep_pins_a: pwm2-sleep-0 { 1117 pins { 1118 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */ 1119 }; 1120 }; 1121 1122 pwm3_pins_a: pwm3-0 { 1123 pins { 1124 pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */ 1125 bias-pull-down; 1126 drive-push-pull; 1127 slew-rate = <0>; 1128 }; 1129 }; 1130 1131 pwm3_sleep_pins_a: pwm3-sleep-0 { 1132 pins { 1133 pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */ 1134 }; 1135 }; 1136 1137 pwm3_pins_b: pwm3-1 { 1138 pins { 1139 pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ 1140 bias-disable; 1141 drive-push-pull; 1142 slew-rate = <0>; 1143 }; 1144 }; 1145 1146 pwm3_sleep_pins_b: pwm3-sleep-1 { 1147 pins { 1148 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */ 1149 }; 1150 }; 1151 1152 pwm4_pins_a: pwm4-0 { 1153 pins { 1154 pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */ 1155 <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */ 1156 bias-pull-down; 1157 drive-push-pull; 1158 slew-rate = <0>; 1159 }; 1160 }; 1161 1162 pwm4_sleep_pins_a: pwm4-sleep-0 { 1163 pins { 1164 pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */ 1165 <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */ 1166 }; 1167 }; 1168 1169 pwm4_pins_b: pwm4-1 { 1170 pins { 1171 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ 1172 bias-pull-down; 1173 drive-push-pull; 1174 slew-rate = <0>; 1175 }; 1176 }; 1177 1178 pwm4_sleep_pins_b: pwm4-sleep-1 { 1179 pins { 1180 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ 1181 }; 1182 }; 1183 1184 pwm5_pins_a: pwm5-0 { 1185 pins { 1186 pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */ 1187 bias-pull-down; 1188 drive-push-pull; 1189 slew-rate = <0>; 1190 }; 1191 }; 1192 1193 pwm5_sleep_pins_a: pwm5-sleep-0 { 1194 pins { 1195 pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */ 1196 }; 1197 }; 1198 1199 pwm5_pins_b: pwm5-1 { 1200 pins { 1201 pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */ 1202 <STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */ 1203 <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */ 1204 bias-disable; 1205 drive-push-pull; 1206 slew-rate = <0>; 1207 }; 1208 }; 1209 1210 pwm5_sleep_pins_b: pwm5-sleep-1 { 1211 pins { 1212 pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */ 1213 <STM32_PINMUX('H', 12, ANALOG)>, /* TIM5_CH3 */ 1214 <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */ 1215 }; 1216 }; 1217 1218 pwm8_pins_a: pwm8-0 { 1219 pins { 1220 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */ 1221 bias-pull-down; 1222 drive-push-pull; 1223 slew-rate = <0>; 1224 }; 1225 }; 1226 1227 pwm8_sleep_pins_a: pwm8-sleep-0 { 1228 pins { 1229 pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */ 1230 }; 1231 }; 1232 1233 pwm12_pins_a: pwm12-0 { 1234 pins { 1235 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */ 1236 bias-pull-down; 1237 drive-push-pull; 1238 slew-rate = <0>; 1239 }; 1240 }; 1241 1242 pwm12_sleep_pins_a: pwm12-sleep-0 { 1243 pins { 1244 pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */ 1245 }; 1246 }; 1247 1248 qspi_clk_pins_a: qspi-clk-0 { 1249 pins { 1250 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ 1251 bias-disable; 1252 drive-push-pull; 1253 slew-rate = <3>; 1254 }; 1255 }; 1256 1257 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { 1258 pins { 1259 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ 1260 }; 1261 }; 1262 1263 qspi_bk1_pins_a: qspi-bk1-0 { 1264 pins1 { 1265 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ 1266 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ 1267 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ 1268 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ 1269 bias-disable; 1270 drive-push-pull; 1271 slew-rate = <1>; 1272 }; 1273 pins2 { 1274 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ 1275 bias-pull-up; 1276 drive-push-pull; 1277 slew-rate = <1>; 1278 }; 1279 }; 1280 1281 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { 1282 pins { 1283 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ 1284 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ 1285 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ 1286 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */ 1287 <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ 1288 }; 1289 }; 1290 1291 qspi_bk2_pins_a: qspi-bk2-0 { 1292 pins1 { 1293 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ 1294 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ 1295 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ 1296 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */ 1297 bias-disable; 1298 drive-push-pull; 1299 slew-rate = <1>; 1300 }; 1301 pins2 { 1302 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ 1303 bias-pull-up; 1304 drive-push-pull; 1305 slew-rate = <1>; 1306 }; 1307 }; 1308 1309 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { 1310 pins { 1311 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ 1312 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ 1313 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ 1314 <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */ 1315 <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ 1316 }; 1317 }; 1318 1319 sai2a_pins_a: sai2a-0 { 1320 pins { 1321 pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */ 1322 <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ 1323 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ 1324 <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */ 1325 slew-rate = <0>; 1326 drive-push-pull; 1327 bias-disable; 1328 }; 1329 }; 1330 1331 sai2a_sleep_pins_a: sai2a-sleep-0 { 1332 pins { 1333 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ 1334 <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ 1335 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ 1336 <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */ 1337 }; 1338 }; 1339 1340 sai2a_pins_b: sai2a-1 { 1341 pins1 { 1342 pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ 1343 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ 1344 <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */ 1345 slew-rate = <0>; 1346 drive-push-pull; 1347 bias-disable; 1348 }; 1349 }; 1350 1351 sai2a_sleep_pins_b: sai2a-sleep-1 { 1352 pins { 1353 pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ 1354 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ 1355 <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */ 1356 }; 1357 }; 1358 1359 sai2a_pins_c: sai2a-2 { 1360 pins { 1361 pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */ 1362 <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */ 1363 <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */ 1364 slew-rate = <0>; 1365 drive-push-pull; 1366 bias-disable; 1367 }; 1368 }; 1369 1370 sai2a_sleep_pins_c: sai2a-sleep-2 { 1371 pins { 1372 pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */ 1373 <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */ 1374 <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */ 1375 }; 1376 }; 1377 1378 sai2b_pins_a: sai2b-0 { 1379 pins1 { 1380 pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */ 1381 <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */ 1382 <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */ 1383 slew-rate = <0>; 1384 drive-push-pull; 1385 bias-disable; 1386 }; 1387 pins2 { 1388 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1389 bias-disable; 1390 }; 1391 }; 1392 1393 sai2b_sleep_pins_a: sai2b-sleep-0 { 1394 pins { 1395 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */ 1396 <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */ 1397 <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */ 1398 <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */ 1399 }; 1400 }; 1401 1402 sai2b_pins_b: sai2b-1 { 1403 pins { 1404 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1405 bias-disable; 1406 }; 1407 }; 1408 1409 sai2b_sleep_pins_b: sai2b-sleep-1 { 1410 pins { 1411 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ 1412 }; 1413 }; 1414 1415 sai2b_pins_c: sai2b-2 { 1416 pins1 { 1417 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ 1418 bias-disable; 1419 }; 1420 }; 1421 1422 sai2b_sleep_pins_c: sai2b-sleep-2 { 1423 pins { 1424 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ 1425 }; 1426 }; 1427 1428 sai4a_pins_a: sai4a-0 { 1429 pins { 1430 pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */ 1431 slew-rate = <0>; 1432 drive-push-pull; 1433 bias-disable; 1434 }; 1435 }; 1436 1437 sai4a_sleep_pins_a: sai4a-sleep-0 { 1438 pins { 1439 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */ 1440 }; 1441 }; 1442 1443 sdmmc1_b4_pins_a: sdmmc1-b4-0 { 1444 pins1 { 1445 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1446 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1447 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 1448 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ 1449 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 1450 slew-rate = <1>; 1451 drive-push-pull; 1452 bias-disable; 1453 }; 1454 pins2 { 1455 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 1456 slew-rate = <2>; 1457 drive-push-pull; 1458 bias-disable; 1459 }; 1460 }; 1461 1462 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { 1463 pins1 { 1464 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1465 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1466 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 1467 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ 1468 slew-rate = <1>; 1469 drive-push-pull; 1470 bias-disable; 1471 }; 1472 pins2 { 1473 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ 1474 slew-rate = <2>; 1475 drive-push-pull; 1476 bias-disable; 1477 }; 1478 pins3 { 1479 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ 1480 slew-rate = <1>; 1481 drive-open-drain; 1482 bias-disable; 1483 }; 1484 }; 1485 1486 sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 { 1487 pins1 { 1488 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ 1489 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ 1490 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ 1491 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ 1492 slew-rate = <1>; 1493 drive-push-pull; 1494 bias-disable; 1495 }; 1496 }; 1497 1498 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { 1499 pins { 1500 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ 1501 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ 1502 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ 1503 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ 1504 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ 1505 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ 1506 }; 1507 }; 1508 1509 sdmmc1_dir_pins_a: sdmmc1-dir-0 { 1510 pins1 { 1511 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 1512 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ 1513 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 1514 slew-rate = <1>; 1515 drive-push-pull; 1516 bias-pull-up; 1517 }; 1518 pins2{ 1519 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ 1520 bias-pull-up; 1521 }; 1522 }; 1523 1524 sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 { 1525 pins1 { 1526 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 1527 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ 1528 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 1529 slew-rate = <1>; 1530 drive-push-pull; 1531 bias-pull-up; 1532 }; 1533 }; 1534 1535 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { 1536 pins { 1537 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ 1538 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ 1539 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ 1540 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ 1541 }; 1542 }; 1543 1544 sdmmc1_dir_pins_b: sdmmc1-dir-1 { 1545 pins1 { 1546 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ 1547 <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */ 1548 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ 1549 slew-rate = <1>; 1550 drive-push-pull; 1551 bias-pull-up; 1552 }; 1553 pins2{ 1554 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ 1555 bias-pull-up; 1556 }; 1557 }; 1558 1559 sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { 1560 pins { 1561 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ 1562 <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */ 1563 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ 1564 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ 1565 }; 1566 }; 1567 1568 sdmmc2_b4_pins_a: sdmmc2-b4-0 { 1569 pins1 { 1570 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1571 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1572 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1573 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 1574 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1575 slew-rate = <1>; 1576 drive-push-pull; 1577 bias-pull-up; 1578 }; 1579 pins2 { 1580 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1581 slew-rate = <2>; 1582 drive-push-pull; 1583 bias-pull-up; 1584 }; 1585 }; 1586 1587 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { 1588 pins1 { 1589 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1590 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1591 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1592 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ 1593 slew-rate = <1>; 1594 drive-push-pull; 1595 bias-pull-up; 1596 }; 1597 pins2 { 1598 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1599 slew-rate = <2>; 1600 drive-push-pull; 1601 bias-pull-up; 1602 }; 1603 pins3 { 1604 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1605 slew-rate = <1>; 1606 drive-open-drain; 1607 bias-pull-up; 1608 }; 1609 }; 1610 1611 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { 1612 pins { 1613 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ 1614 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ 1615 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ 1616 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ 1617 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ 1618 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ 1619 }; 1620 }; 1621 1622 sdmmc2_b4_pins_b: sdmmc2-b4-1 { 1623 pins1 { 1624 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1625 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1626 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1627 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ 1628 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1629 slew-rate = <1>; 1630 drive-push-pull; 1631 bias-disable; 1632 }; 1633 pins2 { 1634 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1635 slew-rate = <2>; 1636 drive-push-pull; 1637 bias-disable; 1638 }; 1639 }; 1640 1641 sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { 1642 pins1 { 1643 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ 1644 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ 1645 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ 1646 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ 1647 slew-rate = <1>; 1648 drive-push-pull; 1649 bias-disable; 1650 }; 1651 pins2 { 1652 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ 1653 slew-rate = <2>; 1654 drive-push-pull; 1655 bias-disable; 1656 }; 1657 pins3 { 1658 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ 1659 slew-rate = <1>; 1660 drive-open-drain; 1661 bias-disable; 1662 }; 1663 }; 1664 1665 sdmmc2_d47_pins_a: sdmmc2-d47-0 { 1666 pins { 1667 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1668 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1669 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ 1670 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ 1671 slew-rate = <1>; 1672 drive-push-pull; 1673 bias-pull-up; 1674 }; 1675 }; 1676 1677 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { 1678 pins { 1679 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1680 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1681 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ 1682 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ 1683 }; 1684 }; 1685 1686 sdmmc2_d47_pins_b: sdmmc2-d47-1 { 1687 pins { 1688 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1689 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1690 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 1691 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 1692 slew-rate = <1>; 1693 drive-push-pull; 1694 bias-disable; 1695 }; 1696 }; 1697 1698 sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { 1699 pins { 1700 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1701 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1702 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ 1703 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 1704 }; 1705 }; 1706 1707 sdmmc2_d47_pins_c: sdmmc2-d47-2 { 1708 pins { 1709 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1710 <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */ 1711 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ 1712 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 1713 slew-rate = <1>; 1714 drive-push-pull; 1715 bias-pull-up; 1716 }; 1717 }; 1718 1719 sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 { 1720 pins { 1721 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1722 <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */ 1723 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ 1724 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 1725 }; 1726 }; 1727 1728 sdmmc2_d47_pins_d: sdmmc2-d47-3 { 1729 pins { 1730 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ 1731 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ 1732 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ 1733 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ 1734 }; 1735 }; 1736 1737 sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { 1738 pins { 1739 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ 1740 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ 1741 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ 1742 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ 1743 }; 1744 }; 1745 1746 sdmmc3_b4_pins_a: sdmmc3-b4-0 { 1747 pins1 { 1748 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1749 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1750 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ 1751 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ 1752 <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */ 1753 slew-rate = <1>; 1754 drive-push-pull; 1755 bias-pull-up; 1756 }; 1757 pins2 { 1758 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1759 slew-rate = <2>; 1760 drive-push-pull; 1761 bias-pull-up; 1762 }; 1763 }; 1764 1765 sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { 1766 pins1 { 1767 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1768 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1769 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ 1770 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ 1771 slew-rate = <1>; 1772 drive-push-pull; 1773 bias-pull-up; 1774 }; 1775 pins2 { 1776 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1777 slew-rate = <2>; 1778 drive-push-pull; 1779 bias-pull-up; 1780 }; 1781 pins3 { 1782 pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */ 1783 slew-rate = <1>; 1784 drive-open-drain; 1785 bias-pull-up; 1786 }; 1787 }; 1788 1789 sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { 1790 pins { 1791 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ 1792 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ 1793 <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */ 1794 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ 1795 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ 1796 <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */ 1797 }; 1798 }; 1799 1800 sdmmc3_b4_pins_b: sdmmc3-b4-1 { 1801 pins1 { 1802 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1803 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1804 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ 1805 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ 1806 <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ 1807 slew-rate = <1>; 1808 drive-push-pull; 1809 bias-pull-up; 1810 }; 1811 pins2 { 1812 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1813 slew-rate = <2>; 1814 drive-push-pull; 1815 bias-pull-up; 1816 }; 1817 }; 1818 1819 sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { 1820 pins1 { 1821 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ 1822 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ 1823 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ 1824 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ 1825 slew-rate = <1>; 1826 drive-push-pull; 1827 bias-pull-up; 1828 }; 1829 pins2 { 1830 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ 1831 slew-rate = <2>; 1832 drive-push-pull; 1833 bias-pull-up; 1834 }; 1835 pins3 { 1836 pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */ 1837 slew-rate = <1>; 1838 drive-open-drain; 1839 bias-pull-up; 1840 }; 1841 }; 1842 1843 sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { 1844 pins { 1845 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ 1846 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ 1847 <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */ 1848 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ 1849 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ 1850 <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */ 1851 }; 1852 }; 1853 1854 spdifrx_pins_a: spdifrx-0 { 1855 pins { 1856 pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ 1857 bias-disable; 1858 }; 1859 }; 1860 1861 spdifrx_sleep_pins_a: spdifrx-sleep-0 { 1862 pins { 1863 pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */ 1864 }; 1865 }; 1866 1867 spi2_pins_a: spi2-0 { 1868 pins1 { 1869 pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */ 1870 <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ 1871 bias-disable; 1872 drive-push-pull; 1873 slew-rate = <1>; 1874 }; 1875 1876 pins2 { 1877 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ 1878 bias-disable; 1879 }; 1880 }; 1881 1882 spi2_pins_b: spi2-1 { 1883 pins1 { 1884 pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */ 1885 <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ 1886 bias-disable; 1887 drive-push-pull; 1888 slew-rate = <1>; 1889 }; 1890 1891 pins2 { 1892 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ 1893 bias-disable; 1894 }; 1895 }; 1896 1897 spi4_pins_a: spi4-0 { 1898 pins { 1899 pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ 1900 <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */ 1901 bias-disable; 1902 drive-push-pull; 1903 slew-rate = <1>; 1904 }; 1905 pins2 { 1906 pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */ 1907 bias-disable; 1908 }; 1909 }; 1910 1911 stusb1600_pins_a: stusb1600-0 { 1912 pins { 1913 pinmux = <STM32_PINMUX('I', 11, GPIO)>; 1914 bias-pull-up; 1915 }; 1916 }; 1917 1918 uart4_pins_a: uart4-0 { 1919 pins1 { 1920 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ 1921 bias-disable; 1922 drive-push-pull; 1923 slew-rate = <0>; 1924 }; 1925 pins2 { 1926 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1927 bias-disable; 1928 }; 1929 }; 1930 1931 uart4_idle_pins_a: uart4-idle-0 { 1932 pins1 { 1933 pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ 1934 }; 1935 pins2 { 1936 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1937 bias-disable; 1938 }; 1939 }; 1940 1941 uart4_sleep_pins_a: uart4-sleep-0 { 1942 pins { 1943 pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ 1944 <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ 1945 }; 1946 }; 1947 1948 uart4_pins_b: uart4-1 { 1949 pins1 { 1950 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ 1951 bias-disable; 1952 drive-push-pull; 1953 slew-rate = <0>; 1954 }; 1955 pins2 { 1956 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1957 bias-disable; 1958 }; 1959 }; 1960 1961 uart4_pins_c: uart4-2 { 1962 pins1 { 1963 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ 1964 bias-disable; 1965 drive-push-pull; 1966 slew-rate = <0>; 1967 }; 1968 pins2 { 1969 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1970 bias-disable; 1971 }; 1972 }; 1973 1974 uart4_pins_d: uart4-3 { 1975 pins1 { 1976 pinmux = <STM32_PINMUX('A', 13, AF8)>; /* UART4_TX */ 1977 bias-disable; 1978 drive-push-pull; 1979 slew-rate = <0>; 1980 }; 1981 pins2 { 1982 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1983 bias-disable; 1984 }; 1985 }; 1986 1987 uart4_idle_pins_d: uart4-idle-3 { 1988 pins1 { 1989 pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* UART4_TX */ 1990 }; 1991 pins2 { 1992 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ 1993 bias-disable; 1994 }; 1995 }; 1996 1997 uart4_sleep_pins_d: uart4-sleep-3 { 1998 pins { 1999 pinmux = <STM32_PINMUX('A', 13, ANALOG)>, /* UART4_TX */ 2000 <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ 2001 }; 2002 }; 2003 2004 uart5_pins_a: uart5-0 { 2005 pins1 { 2006 pinmux = <STM32_PINMUX('B', 13, AF14)>; /* UART5_TX */ 2007 bias-disable; 2008 drive-push-pull; 2009 slew-rate = <0>; 2010 }; 2011 pins2 { 2012 pinmux = <STM32_PINMUX('B', 5, AF12)>; /* UART5_RX */ 2013 bias-disable; 2014 }; 2015 }; 2016 2017 uart7_pins_a: uart7-0 { 2018 pins1 { 2019 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ 2020 bias-disable; 2021 drive-push-pull; 2022 slew-rate = <0>; 2023 }; 2024 pins2 { 2025 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */ 2026 <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */ 2027 <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */ 2028 bias-disable; 2029 }; 2030 }; 2031 2032 uart7_pins_b: uart7-1 { 2033 pins1 { 2034 pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ 2035 bias-disable; 2036 drive-push-pull; 2037 slew-rate = <0>; 2038 }; 2039 pins2 { 2040 pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */ 2041 bias-disable; 2042 }; 2043 }; 2044 2045 uart7_pins_c: uart7-2 { 2046 pins1 { 2047 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ 2048 bias-disable; 2049 drive-push-pull; 2050 slew-rate = <0>; 2051 }; 2052 pins2 { 2053 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ 2054 bias-pull-up; 2055 }; 2056 }; 2057 2058 uart7_idle_pins_c: uart7-idle-2 { 2059 pins1 { 2060 pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */ 2061 }; 2062 pins2 { 2063 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ 2064 bias-pull-up; 2065 }; 2066 }; 2067 2068 uart7_sleep_pins_c: uart7-sleep-2 { 2069 pins { 2070 pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */ 2071 <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */ 2072 }; 2073 }; 2074 2075 uart8_pins_a: uart8-0 { 2076 pins1 { 2077 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ 2078 bias-disable; 2079 drive-push-pull; 2080 slew-rate = <0>; 2081 }; 2082 pins2 { 2083 pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */ 2084 bias-disable; 2085 }; 2086 }; 2087 2088 uart8_rtscts_pins_a: uart8rtscts-0 { 2089 pins { 2090 pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */ 2091 <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */ 2092 bias-disable; 2093 }; 2094 }; 2095 2096 usart2_pins_a: usart2-0 { 2097 pins1 { 2098 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ 2099 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ 2100 bias-disable; 2101 drive-push-pull; 2102 slew-rate = <0>; 2103 }; 2104 pins2 { 2105 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ 2106 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ 2107 bias-disable; 2108 }; 2109 }; 2110 2111 usart2_sleep_pins_a: usart2-sleep-0 { 2112 pins { 2113 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ 2114 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ 2115 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ 2116 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ 2117 }; 2118 }; 2119 2120 usart2_pins_b: usart2-1 { 2121 pins1 { 2122 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ 2123 <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ 2124 bias-disable; 2125 drive-push-pull; 2126 slew-rate = <0>; 2127 }; 2128 pins2 { 2129 pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */ 2130 <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */ 2131 bias-disable; 2132 }; 2133 }; 2134 2135 usart2_sleep_pins_b: usart2-sleep-1 { 2136 pins { 2137 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ 2138 <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ 2139 <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */ 2140 <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ 2141 }; 2142 }; 2143 2144 usart2_pins_c: usart2-2 { 2145 pins1 { 2146 pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */ 2147 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ 2148 bias-disable; 2149 drive-push-pull; 2150 slew-rate = <3>; 2151 }; 2152 pins2 { 2153 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ 2154 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ 2155 bias-disable; 2156 }; 2157 }; 2158 2159 usart2_idle_pins_c: usart2-idle-2 { 2160 pins1 { 2161 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ 2162 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ 2163 }; 2164 pins2 { 2165 pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ 2166 bias-disable; 2167 drive-push-pull; 2168 slew-rate = <3>; 2169 }; 2170 pins3 { 2171 pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ 2172 bias-disable; 2173 }; 2174 }; 2175 2176 usart2_sleep_pins_c: usart2-sleep-2 { 2177 pins { 2178 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ 2179 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ 2180 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ 2181 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ 2182 }; 2183 }; 2184 2185 usart3_pins_a: usart3-0 { 2186 pins1 { 2187 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ 2188 bias-disable; 2189 drive-push-pull; 2190 slew-rate = <0>; 2191 }; 2192 pins2 { 2193 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 2194 bias-disable; 2195 }; 2196 }; 2197 2198 usart3_pins_b: usart3-1 { 2199 pins1 { 2200 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 2201 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2202 bias-disable; 2203 drive-push-pull; 2204 slew-rate = <0>; 2205 }; 2206 pins2 { 2207 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ 2208 <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */ 2209 bias-pull-up; 2210 }; 2211 }; 2212 2213 usart3_idle_pins_b: usart3-idle-1 { 2214 pins1 { 2215 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2216 <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */ 2217 }; 2218 pins2 { 2219 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2220 bias-disable; 2221 drive-push-pull; 2222 slew-rate = <0>; 2223 }; 2224 pins3 { 2225 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 2226 bias-pull-up; 2227 }; 2228 }; 2229 2230 usart3_sleep_pins_b: usart3-sleep-1 { 2231 pins { 2232 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2233 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2234 <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */ 2235 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ 2236 }; 2237 }; 2238 2239 usart3_pins_c: usart3-2 { 2240 pins1 { 2241 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 2242 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2243 bias-disable; 2244 drive-push-pull; 2245 slew-rate = <0>; 2246 }; 2247 pins2 { 2248 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ 2249 <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */ 2250 bias-pull-up; 2251 }; 2252 }; 2253 2254 usart3_idle_pins_c: usart3-idle-2 { 2255 pins1 { 2256 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2257 <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */ 2258 }; 2259 pins2 { 2260 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2261 bias-disable; 2262 drive-push-pull; 2263 slew-rate = <0>; 2264 }; 2265 pins3 { 2266 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ 2267 bias-pull-up; 2268 }; 2269 }; 2270 2271 usart3_sleep_pins_c: usart3-sleep-2 { 2272 pins { 2273 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2274 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2275 <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */ 2276 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ 2277 }; 2278 }; 2279 2280 usart3_pins_d: usart3-3 { 2281 pins1 { 2282 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 2283 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2284 bias-disable; 2285 drive-push-pull; 2286 slew-rate = <0>; 2287 }; 2288 pins2 { 2289 pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */ 2290 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ 2291 bias-disable; 2292 }; 2293 }; 2294 2295 usart3_idle_pins_d: usart3-idle-3 { 2296 pins1 { 2297 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2298 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2299 <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */ 2300 }; 2301 pins2 { 2302 pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */ 2303 bias-disable; 2304 }; 2305 }; 2306 2307 usart3_sleep_pins_d: usart3-sleep-3 { 2308 pins { 2309 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2310 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2311 <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */ 2312 <STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */ 2313 }; 2314 }; 2315 2316 usart3_pins_e: usart3-4 { 2317 pins1 { 2318 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ 2319 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2320 bias-disable; 2321 drive-push-pull; 2322 slew-rate = <0>; 2323 }; 2324 pins2 { 2325 pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */ 2326 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ 2327 bias-pull-up; 2328 }; 2329 }; 2330 2331 usart3_idle_pins_e: usart3-idle-4 { 2332 pins1 { 2333 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2334 <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */ 2335 }; 2336 pins2 { 2337 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ 2338 bias-disable; 2339 drive-push-pull; 2340 slew-rate = <0>; 2341 }; 2342 pins3 { 2343 pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */ 2344 bias-pull-up; 2345 }; 2346 }; 2347 2348 usart3_sleep_pins_e: usart3-sleep-4 { 2349 pins { 2350 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ 2351 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ 2352 <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */ 2353 <STM32_PINMUX('B', 11, ANALOG)>; /* USART3_RX */ 2354 }; 2355 }; 2356 2357 usbotg_hs_pins_a: usbotg-hs-0 { 2358 pins { 2359 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ 2360 }; 2361 }; 2362 2363 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { 2364 pins { 2365 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */ 2366 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */ 2367 }; 2368 }; 2369 }; 2370 2371 &pinctrl_z { 2372 i2c2_pins_b2: i2c2-0 { 2373 pins { 2374 pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */ 2375 bias-disable; 2376 drive-open-drain; 2377 slew-rate = <0>; 2378 }; 2379 }; 2380 2381 i2c2_sleep_pins_b2: i2c2-sleep-0 { 2382 pins { 2383 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */ 2384 }; 2385 }; 2386 2387 i2c4_pins_a: i2c4-0 { 2388 pins { 2389 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ 2390 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ 2391 bias-disable; 2392 drive-open-drain; 2393 slew-rate = <0>; 2394 }; 2395 }; 2396 2397 i2c4_sleep_pins_a: i2c4-sleep-0 { 2398 pins { 2399 pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ 2400 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */ 2401 }; 2402 }; 2403 2404 i2c6_pins_a: i2c6-0 { 2405 pins { 2406 pinmux = <STM32_PINMUX('Z', 6, AF2)>, /* I2C6_SCL */ 2407 <STM32_PINMUX('Z', 7, AF2)>; /* I2C6_SDA */ 2408 bias-disable; 2409 drive-open-drain; 2410 slew-rate = <0>; 2411 }; 2412 }; 2413 2414 i2c6_sleep_pins_a: i2c6-sleep-0 { 2415 pins { 2416 pinmux = <STM32_PINMUX('Z', 6, ANALOG)>, /* I2C6_SCL */ 2417 <STM32_PINMUX('Z', 7, ANALOG)>; /* I2C6_SDA */ 2418 }; 2419 }; 2420 2421 spi1_pins_a: spi1-0 { 2422 pins1 { 2423 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ 2424 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */ 2425 bias-disable; 2426 drive-push-pull; 2427 slew-rate = <1>; 2428 }; 2429 2430 pins2 { 2431 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */ 2432 bias-disable; 2433 }; 2434 }; 2435 2436 spi1_pins_b: spi1-1 { 2437 pins1 { 2438 pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */ 2439 <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */ 2440 bias-disable; 2441 drive-push-pull; 2442 slew-rate = <1>; 2443 }; 2444 2445 pins2 { 2446 pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */ 2447 bias-disable; 2448 }; 2449 }; 2450 };
Cache object: 1ba8698d6f08bf56e1f65a1a6e81504c
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