stm32mp151a-prtt1c.dts

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    1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
    2 /*
    3  * Copyright (C) Protonic Holland
    4  * Author: David Jander <david@protonic.nl>
    5  */
    6 /dts-v1/;
    7 
    8 #include "stm32mp151a-prtt1l.dtsi"
    9 
   10 / {
   11         model = "Protonic PRTT1C";
   12         compatible = "prt,prtt1c", "st,stm32mp151";
   13 
   14         clock_ksz9031: clock-ksz9031 {
   15                 compatible = "fixed-clock";
   16                 #clock-cells = <0>;
   17                 clock-frequency = <25000000>;
   18         };
   19 
   20         clock_sja1105: clock-sja1105 {
   21                 compatible = "fixed-clock";
   22                 #clock-cells = <0>;
   23                 clock-frequency = <25000000>;
   24         };
   25 
   26         mdio0: mdio {
   27                 compatible = "virtual,mdio-gpio";
   28                 #address-cells = <1>;
   29                 #size-cells = <0>;
   30                 gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
   31                          &gpioa 2 GPIO_ACTIVE_HIGH>;
   32 
   33         };
   34 
   35         wifi_pwrseq: wifi-pwrseq {
   36                 compatible = "mmc-pwrseq-simple";
   37                 reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>;
   38         };
   39 };
   40 
   41 &ethernet0 {
   42         fixed-link {
   43                 speed = <100>;
   44                 full-duplex;
   45         };
   46 };
   47 
   48 &gpioa {
   49         gpio-line-names =
   50                 "", "", "", "PHY0_nRESET", "PHY0_nINT", "", "", "",
   51                 "", "", "", "", "", "", "", "SPI1_nSS";
   52 };
   53 
   54 &gpiod {
   55         gpio-line-names =
   56                 "", "", "", "", "", "", "", "",
   57                 "WFM_RESET", "", "", "", "", "", "", "";
   58 };
   59 
   60 &gpioe {
   61         gpio-line-names =
   62                 "SDMMC2_nRESET", "", "", "", "", "", "SPI1_nRESET", "",
   63                 "", "", "", "", "WFM_nIRQ", "", "", "";
   64 };
   65 
   66 &gpiog {
   67         gpio-line-names =
   68                 "", "", "", "", "", "", "", "PHY3_nINT",
   69                 "PHY1_nINT", "PHY3_nRESET", "PHY2_nINT", "PHY2_nRESET",
   70                 "PHY1_nRESET", "SPE1_PWR", "SPE0_PWR", "";
   71 };
   72 
   73 &mdio0 {
   74         /* All this DP83TD510E PHYs can't be probed before switch@0 is
   75          * probed so we need to use compatible with PHYid
   76          */
   77         /* TI DP83TD510E */
   78         t1l0_phy: ethernet-phy@6 {
   79                 compatible = "ethernet-phy-id2000.0181";
   80                 reg = <6>;
   81                 interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
   82                 reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
   83                 reset-assert-us = <10>;
   84                 reset-deassert-us = <35>;
   85         };
   86 
   87         /* TI DP83TD510E */
   88         t1l1_phy: ethernet-phy@7 {
   89                 compatible = "ethernet-phy-id2000.0181";
   90                 reg = <7>;
   91                 interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>;
   92                 reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>;
   93                 reset-assert-us = <10>;
   94                 reset-deassert-us = <35>;
   95         };
   96 
   97         /* TI DP83TD510E */
   98         t1l2_phy: ethernet-phy@10 {
   99                 compatible = "ethernet-phy-id2000.0181";
  100                 reg = <10>;
  101                 interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>;
  102                 reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>;
  103                 reset-assert-us = <10>;
  104                 reset-deassert-us = <35>;
  105         };
  106 
  107         /* Micrel KSZ9031 */
  108         rj45_phy: ethernet-phy@2 {
  109                 reg = <2>;
  110                 interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>;
  111                 reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
  112                 reset-assert-us = <10000>;
  113                 reset-deassert-us = <1000>;
  114 
  115                 clocks = <&clock_ksz9031>;
  116         };
  117 };
  118 
  119 &qspi {
  120         status = "disabled";
  121 };
  122 
  123 &sdmmc2 {
  124         pinctrl-names = "default", "opendrain", "sleep";
  125         pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
  126         pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
  127         pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
  128         non-removable;
  129         no-sd;
  130         no-sdio;
  131         no-1-8-v;
  132         st,neg-edge;
  133         bus-width = <8>;
  134         vmmc-supply = <&reg_3v3>;
  135         vqmmc-supply = <&reg_3v3>;
  136         status = "okay";
  137 };
  138 
  139 &sdmmc2_b4_od_pins_a {
  140         pins1 {
  141                 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
  142                          <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
  143                          <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
  144                          <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
  145         };
  146 };
  147 
  148 &sdmmc2_b4_pins_a {
  149         pins1 {
  150                 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
  151                          <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
  152                          <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
  153                          <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
  154                          <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
  155         };
  156 };
  157 
  158 &sdmmc2_b4_sleep_pins_a {
  159         pins {
  160                 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
  161                          <STM32_PINMUX('B', 7, ANALOG)>, /* SDMMC2_D1 */
  162                          <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
  163                          <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
  164                          <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
  165                          <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
  166         };
  167 };
  168 
  169 &sdmmc2_d47_pins_a {
  170         pins {
  171                 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
  172                          <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
  173                          <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
  174                          <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
  175         };
  176 };
  177 
  178 &sdmmc2_d47_sleep_pins_a {
  179         pins {
  180                 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
  181                          <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
  182                          <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
  183                          <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
  184         };
  185 };
  186 
  187 &sdmmc3 {
  188         pinctrl-names = "default", "opendrain", "sleep";
  189         pinctrl-0 = <&sdmmc3_b4_pins_b>;
  190         pinctrl-1 = <&sdmmc3_b4_od_pins_b>;
  191         pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>;
  192         non-removable;
  193         no-1-8-v;
  194         st,neg-edge;
  195         bus-width = <4>;
  196         vmmc-supply = <&reg_3v3>;
  197         vqmmc-supply = <&reg_3v3>;
  198         mmc-pwrseq = <&wifi_pwrseq>;
  199         #address-cells = <1>;
  200         #size-cells = <0>;
  201         status = "okay";
  202 
  203         mmc@1 {
  204                 compatible = "prt,prtt1c-wfm200", "silabs,wf200";
  205                 reg = <1>;
  206         };
  207 };
  208 
  209 &sdmmc3_b4_od_pins_b {
  210         pins1 {
  211                 pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
  212                          <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
  213                          <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
  214                          <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
  215         };
  216 };
  217 
  218 &sdmmc3_b4_pins_b {
  219         pins1 {
  220                 pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
  221                          <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
  222                          <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
  223                          <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
  224                          <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
  225         };
  226 };
  227 
  228 &sdmmc3_b4_sleep_pins_b {
  229         pins {
  230                 pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* SDMMC3_D0 */
  231                          <STM32_PINMUX('D', 4, ANALOG)>, /* SDMMC3_D1 */
  232                          <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
  233                          <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
  234                          <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
  235                          <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
  236         };
  237 };
  238 
  239 &spi1 {
  240         pinctrl-0 = <&spi1_pins_b>;
  241         pinctrl-names = "default";
  242         cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
  243         /delete-property/dmas;
  244         /delete-property/dma-names;
  245         status = "okay";
  246 
  247         switch@0 {
  248                 compatible = "nxp,sja1105q";
  249                 reg = <0>;
  250                 spi-max-frequency = <4000000>;
  251                 spi-rx-delay-us = <1>;
  252                 spi-tx-delay-us = <1>;
  253                 spi-cpha;
  254 
  255                 reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>;
  256 
  257                 clocks = <&clock_sja1105>;
  258 
  259                 ports {
  260                         #address-cells = <1>;
  261                         #size-cells = <0>;
  262 
  263                         port@0 {
  264                                 reg = <0>;
  265                                 label = "t1l0";
  266                                 phy-mode = "rmii";
  267                                 phy-handle = <&t1l0_phy>;
  268                         };
  269 
  270                         port@1 {
  271                                 reg = <1>;
  272                                 label = "t1l1";
  273                                 phy-mode = "rmii";
  274                                 phy-handle = <&t1l1_phy>;
  275                         };
  276 
  277                         port@2 {
  278                                 reg = <2>;
  279                                 label = "t1l2";
  280                                 phy-mode = "rmii";
  281                                 phy-handle = <&t1l2_phy>;
  282                         };
  283 
  284                         port@3 {
  285                                 reg = <3>;
  286                                 label = "rj45";
  287                                 phy-handle = <&rj45_phy>;
  288                                 phy-mode = "rgmii-id";
  289                         };
  290 
  291                         port@4 {
  292                                 reg = <4>;
  293                                 label = "cpu";
  294                                 ethernet = <&ethernet0>;
  295                                 phy-mode = "rmii";
  296 
  297                                 fixed-link {
  298                                         speed = <100>;
  299                                         full-duplex;
  300                                 };
  301                         };
  302                 };
  303         };
  304 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/stm32mp151a-prtt1c.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/stm32mp151a-prtt1c.dts