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sys/contrib/device-tree/src/arm/sun8i-a23-a33.dtsi
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1 /* 2 * Copyright 2014 Chen-Yu Tsai 3 * 4 * Chen-Yu Tsai <wens@csie.org> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45 #include <dt-bindings/interrupt-controller/arm-gic.h> 46 47 #include <dt-bindings/clock/sun6i-rtc.h> 48 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h> 49 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h> 50 51 / { 52 interrupt-parent = <&gic>; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 56 chosen { 57 #address-cells = <1>; 58 #size-cells = <1>; 59 ranges; 60 61 simplefb_lcd: framebuffer-lcd0 { 62 compatible = "allwinner,simple-framebuffer", 63 "simple-framebuffer"; 64 allwinner,pipeline = "de_be0-lcd0"; 65 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>, 66 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>, 67 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>; 68 status = "disabled"; 69 }; 70 }; 71 72 de: display-engine { 73 /* compatible gets set in SoC specific dtsi file */ 74 allwinner,pipelines = <&fe0>; 75 status = "disabled"; 76 }; 77 78 timer { 79 compatible = "arm,armv7-timer"; 80 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 81 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 82 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 83 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 84 clock-frequency = <24000000>; 85 arm,cpu-registers-not-fw-configured; 86 }; 87 88 cpus { 89 enable-method = "allwinner,sun8i-a23"; 90 #address-cells = <1>; 91 #size-cells = <0>; 92 93 cpu0: cpu@0 { 94 compatible = "arm,cortex-a7"; 95 device_type = "cpu"; 96 reg = <0>; 97 }; 98 99 cpu@1 { 100 compatible = "arm,cortex-a7"; 101 device_type = "cpu"; 102 reg = <1>; 103 }; 104 }; 105 106 clocks { 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges; 110 111 osc24M: osc24M_clk { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 clock-frequency = <24000000>; 115 clock-accuracy = <50000>; 116 clock-output-names = "osc24M"; 117 }; 118 119 ext_osc32k: ext_osc32k_clk { 120 #clock-cells = <0>; 121 compatible = "fixed-clock"; 122 clock-frequency = <32768>; 123 clock-accuracy = <50000>; 124 clock-output-names = "ext-osc32k"; 125 }; 126 }; 127 128 soc { 129 compatible = "simple-bus"; 130 #address-cells = <1>; 131 #size-cells = <1>; 132 ranges; 133 134 system-control@1c00000 { 135 compatible = "allwinner,sun8i-a23-system-control"; 136 reg = <0x01c00000 0x30>; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 ranges; 140 141 sram_c: sram@1d00000 { 142 compatible = "mmio-sram"; 143 reg = <0x01d00000 0x80000>; 144 #address-cells = <1>; 145 #size-cells = <1>; 146 ranges = <0 0x01d00000 0x80000>; 147 148 ve_sram: sram-section@0 { 149 compatible = "allwinner,sun8i-a23-sram-c1", 150 "allwinner,sun4i-a10-sram-c1"; 151 reg = <0x000000 0x80000>; 152 }; 153 }; 154 }; 155 156 dma: dma-controller@1c02000 { 157 compatible = "allwinner,sun8i-a23-dma"; 158 reg = <0x01c02000 0x1000>; 159 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&ccu CLK_BUS_DMA>; 161 resets = <&ccu RST_BUS_DMA>; 162 #dma-cells = <1>; 163 }; 164 165 nfc: nand-controller@1c03000 { 166 compatible = "allwinner,sun8i-a23-nand-controller"; 167 reg = <0x01c03000 0x1000>; 168 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; 170 clock-names = "ahb", "mod"; 171 resets = <&ccu RST_BUS_NAND>; 172 reset-names = "ahb"; 173 dmas = <&dma 5>; 174 dma-names = "rxtx"; 175 pinctrl-names = "default"; 176 pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>; 177 status = "disabled"; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 }; 181 182 tcon0: lcd-controller@1c0c000 { 183 /* compatible gets set in SoC specific dtsi file */ 184 reg = <0x01c0c000 0x1000>; 185 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 186 dmas = <&dma 12>; 187 clocks = <&ccu CLK_BUS_LCD>, 188 <&ccu CLK_LCD_CH0>, 189 <&ccu 13>; 190 clock-names = "ahb", 191 "tcon-ch0", 192 "lvds-alt"; 193 clock-output-names = "tcon-pixel-clock"; 194 #clock-cells = <0>; 195 resets = <&ccu RST_BUS_LCD>, 196 <&ccu RST_BUS_LVDS>; 197 reset-names = "lcd", 198 "lvds"; 199 status = "disabled"; 200 201 ports { 202 #address-cells = <1>; 203 #size-cells = <0>; 204 205 tcon0_in: port@0 { 206 reg = <0>; 207 208 tcon0_in_drc0: endpoint { 209 remote-endpoint = <&drc0_out_tcon0>; 210 }; 211 }; 212 213 tcon0_out: port@1 { 214 reg = <1>; 215 }; 216 }; 217 }; 218 219 mmc0: mmc@1c0f000 { 220 compatible = "allwinner,sun7i-a20-mmc"; 221 reg = <0x01c0f000 0x1000>; 222 clocks = <&ccu CLK_BUS_MMC0>, 223 <&ccu CLK_MMC0>, 224 <&ccu CLK_MMC0_OUTPUT>, 225 <&ccu CLK_MMC0_SAMPLE>; 226 clock-names = "ahb", 227 "mmc", 228 "output", 229 "sample"; 230 resets = <&ccu RST_BUS_MMC0>; 231 reset-names = "ahb"; 232 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&mmc0_pins>; 235 status = "disabled"; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 }; 239 240 mmc1: mmc@1c10000 { 241 compatible = "allwinner,sun7i-a20-mmc"; 242 reg = <0x01c10000 0x1000>; 243 clocks = <&ccu CLK_BUS_MMC1>, 244 <&ccu CLK_MMC1>, 245 <&ccu CLK_MMC1_OUTPUT>, 246 <&ccu CLK_MMC1_SAMPLE>; 247 clock-names = "ahb", 248 "mmc", 249 "output", 250 "sample"; 251 resets = <&ccu RST_BUS_MMC1>; 252 reset-names = "ahb"; 253 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 254 status = "disabled"; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 }; 258 259 mmc2: mmc@1c11000 { 260 compatible = "allwinner,sun7i-a20-mmc"; 261 reg = <0x01c11000 0x1000>; 262 clocks = <&ccu CLK_BUS_MMC2>, 263 <&ccu CLK_MMC2>, 264 <&ccu CLK_MMC2_OUTPUT>, 265 <&ccu CLK_MMC2_SAMPLE>; 266 clock-names = "ahb", 267 "mmc", 268 "output", 269 "sample"; 270 resets = <&ccu RST_BUS_MMC2>; 271 reset-names = "ahb"; 272 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 273 status = "disabled"; 274 #address-cells = <1>; 275 #size-cells = <0>; 276 }; 277 278 usb_otg: usb@1c19000 { 279 /* compatible gets set in SoC specific dtsi file */ 280 reg = <0x01c19000 0x0400>; 281 clocks = <&ccu CLK_BUS_OTG>; 282 resets = <&ccu RST_BUS_OTG>; 283 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 284 interrupt-names = "mc"; 285 phys = <&usbphy 0>; 286 phy-names = "usb"; 287 extcon = <&usbphy 0>; 288 dr_mode = "otg"; 289 status = "disabled"; 290 }; 291 292 usbphy: phy@1c19400 { 293 /* 294 * compatible and address regions get set in 295 * SoC specific dtsi file 296 */ 297 clocks = <&ccu CLK_USB_PHY0>, 298 <&ccu CLK_USB_PHY1>; 299 clock-names = "usb0_phy", 300 "usb1_phy"; 301 resets = <&ccu RST_USB_PHY0>, 302 <&ccu RST_USB_PHY1>; 303 reset-names = "usb0_reset", 304 "usb1_reset"; 305 status = "disabled"; 306 #phy-cells = <1>; 307 }; 308 309 ehci0: usb@1c1a000 { 310 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; 311 reg = <0x01c1a000 0x100>; 312 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&ccu CLK_BUS_EHCI>; 314 resets = <&ccu RST_BUS_EHCI>; 315 phys = <&usbphy 1>; 316 phy-names = "usb"; 317 status = "disabled"; 318 }; 319 320 ohci0: usb@1c1a400 { 321 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; 322 reg = <0x01c1a400 0x100>; 323 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>; 325 resets = <&ccu RST_BUS_OHCI>; 326 phys = <&usbphy 1>; 327 phy-names = "usb"; 328 status = "disabled"; 329 }; 330 331 ccu: clock@1c20000 { 332 reg = <0x01c20000 0x400>; 333 clocks = <&osc24M>, <&rtc CLK_OSC32K>; 334 clock-names = "hosc", "losc"; 335 #clock-cells = <1>; 336 #reset-cells = <1>; 337 }; 338 339 pio: pinctrl@1c20800 { 340 /* compatible gets set in SoC specific dtsi file */ 341 reg = <0x01c20800 0x400>; 342 interrupt-parent = <&r_intc>; 343 /* interrupts get set in SoC specific dtsi file */ 344 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, 345 <&rtc CLK_OSC32K>; 346 clock-names = "apb", "hosc", "losc"; 347 gpio-controller; 348 interrupt-controller; 349 #interrupt-cells = <3>; 350 #gpio-cells = <3>; 351 352 i2c0_pins: i2c0-pins { 353 pins = "PH2", "PH3"; 354 function = "i2c0"; 355 }; 356 357 i2c1_pins: i2c1-pins { 358 pins = "PH4", "PH5"; 359 function = "i2c1"; 360 }; 361 362 i2c2_pins: i2c2-pins { 363 pins = "PE12", "PE13"; 364 function = "i2c2"; 365 }; 366 367 lcd_rgb666_pins: lcd-rgb666-pins { 368 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 369 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", 370 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", 371 "PD24", "PD25", "PD26", "PD27"; 372 function = "lcd0"; 373 }; 374 375 mmc0_pins: mmc0-pins { 376 pins = "PF0", "PF1", "PF2", 377 "PF3", "PF4", "PF5"; 378 function = "mmc0"; 379 drive-strength = <30>; 380 bias-pull-up; 381 }; 382 383 mmc1_pg_pins: mmc1-pg-pins { 384 pins = "PG0", "PG1", "PG2", 385 "PG3", "PG4", "PG5"; 386 function = "mmc1"; 387 drive-strength = <30>; 388 bias-pull-up; 389 }; 390 391 mmc2_8bit_pins: mmc2-8bit-pins { 392 pins = "PC5", "PC6", "PC8", 393 "PC9", "PC10", "PC11", 394 "PC12", "PC13", "PC14", 395 "PC15", "PC16"; 396 function = "mmc2"; 397 drive-strength = <30>; 398 bias-pull-up; 399 }; 400 401 nand_pins: nand-pins { 402 pins = "PC0", "PC1", "PC2", "PC5", 403 "PC8", "PC9", "PC10", "PC11", 404 "PC12", "PC13", "PC14", "PC15"; 405 function = "nand0"; 406 }; 407 408 nand_cs0_pin: nand-cs0-pin { 409 pins = "PC4"; 410 function = "nand0"; 411 bias-pull-up; 412 }; 413 414 nand_cs1_pin: nand-cs1-pin { 415 pins = "PC3"; 416 function = "nand0"; 417 bias-pull-up; 418 }; 419 420 nand_rb0_pin: nand-rb0-pin { 421 pins = "PC6"; 422 function = "nand0"; 423 bias-pull-up; 424 }; 425 426 nand_rb1_pin: nand-rb1-pin { 427 pins = "PC7"; 428 function = "nand0"; 429 bias-pull-up; 430 }; 431 432 pwm0_pin: pwm0-pin { 433 pins = "PH0"; 434 function = "pwm0"; 435 }; 436 437 uart0_pf_pins: uart0-pf-pins { 438 pins = "PF2", "PF4"; 439 function = "uart0"; 440 }; 441 442 uart1_pg_pins: uart1-pg-pins { 443 pins = "PG6", "PG7"; 444 function = "uart1"; 445 }; 446 447 uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins { 448 pins = "PG8", "PG9"; 449 function = "uart1"; 450 }; 451 }; 452 453 timer@1c20c00 { 454 compatible = "allwinner,sun8i-a23-timer"; 455 reg = <0x01c20c00 0xa0>; 456 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&osc24M>; 459 }; 460 461 wdt0: watchdog@1c20ca0 { 462 compatible = "allwinner,sun6i-a31-wdt"; 463 reg = <0x01c20ca0 0x20>; 464 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&osc24M>; 466 }; 467 468 pwm: pwm@1c21400 { 469 compatible = "allwinner,sun7i-a20-pwm"; 470 reg = <0x01c21400 0xc>; 471 clocks = <&osc24M>; 472 #pwm-cells = <3>; 473 status = "disabled"; 474 }; 475 476 lradc: lradc@1c22800 { 477 compatible = "allwinner,sun4i-a10-lradc-keys"; 478 reg = <0x01c22800 0x100>; 479 interrupt-parent = <&r_intc>; 480 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 481 status = "disabled"; 482 }; 483 484 uart0: serial@1c28000 { 485 compatible = "snps,dw-apb-uart"; 486 reg = <0x01c28000 0x400>; 487 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 488 reg-shift = <2>; 489 reg-io-width = <4>; 490 clocks = <&ccu CLK_BUS_UART0>; 491 resets = <&ccu RST_BUS_UART0>; 492 dmas = <&dma 6>, <&dma 6>; 493 dma-names = "rx", "tx"; 494 status = "disabled"; 495 }; 496 497 uart1: serial@1c28400 { 498 compatible = "snps,dw-apb-uart"; 499 reg = <0x01c28400 0x400>; 500 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 501 reg-shift = <2>; 502 reg-io-width = <4>; 503 clocks = <&ccu CLK_BUS_UART1>; 504 resets = <&ccu RST_BUS_UART1>; 505 dmas = <&dma 7>, <&dma 7>; 506 dma-names = "rx", "tx"; 507 status = "disabled"; 508 }; 509 510 uart2: serial@1c28800 { 511 compatible = "snps,dw-apb-uart"; 512 reg = <0x01c28800 0x400>; 513 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 514 reg-shift = <2>; 515 reg-io-width = <4>; 516 clocks = <&ccu CLK_BUS_UART2>; 517 resets = <&ccu RST_BUS_UART2>; 518 dmas = <&dma 8>, <&dma 8>; 519 dma-names = "rx", "tx"; 520 status = "disabled"; 521 }; 522 523 uart3: serial@1c28c00 { 524 compatible = "snps,dw-apb-uart"; 525 reg = <0x01c28c00 0x400>; 526 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 527 reg-shift = <2>; 528 reg-io-width = <4>; 529 clocks = <&ccu CLK_BUS_UART3>; 530 resets = <&ccu RST_BUS_UART3>; 531 dmas = <&dma 9>, <&dma 9>; 532 dma-names = "rx", "tx"; 533 status = "disabled"; 534 }; 535 536 uart4: serial@1c29000 { 537 compatible = "snps,dw-apb-uart"; 538 reg = <0x01c29000 0x400>; 539 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 540 reg-shift = <2>; 541 reg-io-width = <4>; 542 clocks = <&ccu CLK_BUS_UART4>; 543 resets = <&ccu RST_BUS_UART4>; 544 dmas = <&dma 10>, <&dma 10>; 545 dma-names = "rx", "tx"; 546 status = "disabled"; 547 }; 548 549 i2c0: i2c@1c2ac00 { 550 compatible = "allwinner,sun6i-a31-i2c"; 551 reg = <0x01c2ac00 0x400>; 552 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&ccu CLK_BUS_I2C0>; 554 resets = <&ccu RST_BUS_I2C0>; 555 pinctrl-names = "default"; 556 pinctrl-0 = <&i2c0_pins>; 557 status = "disabled"; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 }; 561 562 i2c1: i2c@1c2b000 { 563 compatible = "allwinner,sun6i-a31-i2c"; 564 reg = <0x01c2b000 0x400>; 565 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&ccu CLK_BUS_I2C1>; 567 resets = <&ccu RST_BUS_I2C1>; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&i2c1_pins>; 570 status = "disabled"; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 }; 574 575 i2c2: i2c@1c2b400 { 576 compatible = "allwinner,sun6i-a31-i2c"; 577 reg = <0x01c2b400 0x400>; 578 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&ccu CLK_BUS_I2C2>; 580 resets = <&ccu RST_BUS_I2C2>; 581 pinctrl-names = "default"; 582 pinctrl-0 = <&i2c2_pins>; 583 status = "disabled"; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 }; 587 588 mali: gpu@1c40000 { 589 compatible = "allwinner,sun8i-a23-mali", 590 "allwinner,sun7i-a20-mali", "arm,mali-400"; 591 reg = <0x01c40000 0x10000>; 592 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 599 interrupt-names = "gp", 600 "gpmmu", 601 "pp0", 602 "ppmmu0", 603 "pp1", 604 "ppmmu1", 605 "pmu"; 606 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 607 clock-names = "bus", "core"; 608 resets = <&ccu RST_BUS_GPU>; 609 #cooling-cells = <2>; 610 611 assigned-clocks = <&ccu CLK_GPU>; 612 assigned-clock-rates = <384000000>; 613 }; 614 615 gic: interrupt-controller@1c81000 { 616 compatible = "arm,gic-400"; 617 reg = <0x01c81000 0x1000>, 618 <0x01c82000 0x2000>, 619 <0x01c84000 0x2000>, 620 <0x01c86000 0x2000>; 621 interrupt-controller; 622 #interrupt-cells = <3>; 623 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 624 }; 625 626 fe0: display-frontend@1e00000 { 627 /* compatible gets set in SoC specific dtsi file */ 628 reg = <0x01e00000 0x20000>; 629 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, 631 <&ccu CLK_DRAM_DE_FE>; 632 clock-names = "ahb", "mod", 633 "ram"; 634 resets = <&ccu RST_BUS_DE_FE>; 635 636 ports { 637 #address-cells = <1>; 638 #size-cells = <0>; 639 640 fe0_out: port@1 { 641 reg = <1>; 642 643 fe0_out_be0: endpoint { 644 remote-endpoint = <&be0_in_fe0>; 645 }; 646 }; 647 }; 648 }; 649 650 be0: display-backend@1e60000 { 651 /* compatible gets set in SoC specific dtsi file */ 652 reg = <0x01e60000 0x10000>; 653 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, 655 <&ccu CLK_DRAM_DE_BE>; 656 clock-names = "ahb", "mod", 657 "ram"; 658 resets = <&ccu RST_BUS_DE_BE>; 659 660 ports { 661 #address-cells = <1>; 662 #size-cells = <0>; 663 664 be0_in: port@0 { 665 reg = <0>; 666 667 be0_in_fe0: endpoint { 668 remote-endpoint = <&fe0_out_be0>; 669 }; 670 }; 671 672 be0_out: port@1 { 673 reg = <1>; 674 675 be0_out_drc0: endpoint { 676 remote-endpoint = <&drc0_in_be0>; 677 }; 678 }; 679 }; 680 }; 681 682 drc0: drc@1e70000 { 683 /* compatible gets set in SoC specific dtsi file */ 684 reg = <0x01e70000 0x10000>; 685 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, 687 <&ccu CLK_DRAM_DRC>; 688 clock-names = "ahb", "mod", "ram"; 689 resets = <&ccu RST_BUS_DRC>; 690 691 ports { 692 #address-cells = <1>; 693 #size-cells = <0>; 694 695 drc0_in: port@0 { 696 reg = <0>; 697 698 drc0_in_be0: endpoint { 699 remote-endpoint = <&be0_out_drc0>; 700 }; 701 }; 702 703 drc0_out: port@1 { 704 reg = <1>; 705 706 drc0_out_tcon0: endpoint { 707 remote-endpoint = <&tcon0_in_drc0>; 708 }; 709 }; 710 }; 711 }; 712 713 rtc: rtc@1f00000 { 714 compatible = "allwinner,sun8i-a23-rtc"; 715 reg = <0x01f00000 0x400>; 716 interrupt-parent = <&r_intc>; 717 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 719 clock-output-names = "osc32k", "osc32k-out"; 720 clocks = <&ext_osc32k>; 721 #clock-cells = <1>; 722 }; 723 724 r_intc: interrupt-controller@1f00c00 { 725 compatible = "allwinner,sun6i-a31-r-intc"; 726 interrupt-controller; 727 #interrupt-cells = <3>; 728 reg = <0x01f00c00 0x400>; 729 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 730 }; 731 732 prcm@1f01400 { 733 compatible = "allwinner,sun8i-a23-prcm"; 734 reg = <0x01f01400 0x200>; 735 736 ar100: ar100_clk { 737 compatible = "fixed-factor-clock"; 738 #clock-cells = <0>; 739 clock-div = <1>; 740 clock-mult = <1>; 741 clocks = <&osc24M>; 742 clock-output-names = "ar100"; 743 }; 744 745 ahb0: ahb0_clk { 746 compatible = "fixed-factor-clock"; 747 #clock-cells = <0>; 748 clock-div = <1>; 749 clock-mult = <1>; 750 clocks = <&ar100>; 751 clock-output-names = "ahb0"; 752 }; 753 754 apb0: apb0_clk { 755 compatible = "allwinner,sun8i-a23-apb0-clk"; 756 #clock-cells = <0>; 757 clocks = <&ahb0>; 758 clock-output-names = "apb0"; 759 }; 760 761 apb0_gates: apb0_gates_clk { 762 compatible = "allwinner,sun8i-a23-apb0-gates-clk"; 763 #clock-cells = <1>; 764 clocks = <&apb0>; 765 clock-output-names = "apb0_pio", "apb0_timer", 766 "apb0_rsb", "apb0_uart", 767 "apb0_i2c"; 768 }; 769 770 apb0_rst: apb0_rst { 771 compatible = "allwinner,sun6i-a31-clock-reset"; 772 #reset-cells = <1>; 773 }; 774 775 codec_analog: codec-analog { 776 compatible = "allwinner,sun8i-a23-codec-analog"; 777 }; 778 }; 779 780 cpucfg@1f01c00 { 781 compatible = "allwinner,sun8i-a23-cpuconfig"; 782 reg = <0x01f01c00 0x300>; 783 }; 784 785 r_uart: serial@1f02800 { 786 compatible = "snps,dw-apb-uart"; 787 reg = <0x01f02800 0x400>; 788 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 789 reg-shift = <2>; 790 reg-io-width = <4>; 791 clocks = <&apb0_gates 4>; 792 resets = <&apb0_rst 4>; 793 status = "disabled"; 794 }; 795 796 r_i2c: i2c@1f02400 { 797 compatible = "allwinner,sun8i-a23-i2c", 798 "allwinner,sun6i-a31-i2c"; 799 reg = <0x01f02400 0x400>; 800 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 801 pinctrl-names = "default"; 802 pinctrl-0 = <&r_i2c_pins>; 803 clocks = <&apb0_gates 6>; 804 resets = <&apb0_rst 6>; 805 status = "disabled"; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 }; 809 810 r_pio: pinctrl@1f02c00 { 811 compatible = "allwinner,sun8i-a23-r-pinctrl"; 812 reg = <0x01f02c00 0x400>; 813 interrupt-parent = <&r_intc>; 814 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>; 816 clock-names = "apb", "hosc", "losc"; 817 gpio-controller; 818 interrupt-controller; 819 #interrupt-cells = <3>; 820 #gpio-cells = <3>; 821 822 r_i2c_pins: r-i2c-pins { 823 pins = "PL0", "PL1"; 824 function = "s_i2c"; 825 bias-pull-up; 826 }; 827 828 r_rsb_pins: r-rsb-pins { 829 pins = "PL0", "PL1"; 830 function = "s_rsb"; 831 drive-strength = <20>; 832 bias-pull-up; 833 }; 834 835 r_uart_pins_a: r-uart-pins { 836 pins = "PL2", "PL3"; 837 function = "s_uart"; 838 }; 839 }; 840 841 r_rsb: rsb@1f03400 { 842 compatible = "allwinner,sun8i-a23-rsb"; 843 reg = <0x01f03400 0x400>; 844 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&apb0_gates 3>; 846 clock-frequency = <3000000>; 847 resets = <&apb0_rst 3>; 848 pinctrl-names = "default"; 849 pinctrl-0 = <&r_rsb_pins>; 850 status = "disabled"; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 }; 854 }; 855 };
Cache object: 952125ba2851fbc61225be59cd7c0dc8
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