Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/tango4-common.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on Mans Rullgard's Tango3 DT 4 * https://github.com/mansr/linux-tangox 5 */ 6 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 9 #define CPU_CLK 0 10 #define SYS_CLK 1 11 #define USB_CLK 2 12 #define SDIO_CLK 3 13 14 / { 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 periph_clk: periph_clk { 20 compatible = "fixed-factor-clock"; 21 clocks = <&clkgen CPU_CLK>; 22 clock-mult = <1>; 23 clock-div = <2>; 24 #clock-cells = <0>; 25 }; 26 27 mpcore { 28 compatible = "simple-bus"; 29 ranges = <0x00000000 0x20000000 0x2000>; 30 #address-cells = <1>; 31 #size-cells = <1>; 32 33 scu@0 { 34 compatible = "arm,cortex-a9-scu"; 35 reg = <0x0 0x100>; 36 }; 37 38 twd@600 { 39 compatible = "arm,cortex-a9-twd-timer"; 40 reg = <0x600 0x10>; 41 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>; 42 clocks = <&periph_clk>; 43 always-on; 44 }; 45 46 gic: interrupt-controller@1000 { 47 compatible = "arm,cortex-a9-gic"; 48 #interrupt-cells = <3>; 49 interrupt-controller; 50 reg = <0x1000 0x1000>, <0x100 0x100>; 51 }; 52 }; 53 54 l2cc: cache-controller@20100000 { 55 compatible = "arm,pl310-cache"; 56 reg = <0x20100000 0x1000>; 57 cache-level = <2>; 58 cache-unified; 59 }; 60 61 soc { 62 compatible = "simple-bus"; 63 interrupt-parent = <&irq0>; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 ranges; 67 68 xtal: xtal { 69 compatible = "fixed-clock"; 70 clock-frequency = <27000000>; 71 #clock-cells = <0>; 72 }; 73 74 clkgen: clkgen@10000 { 75 compatible = "sigma,tango4-clkgen"; 76 reg = <0x10000 0x100>; 77 clocks = <&xtal>; 78 #clock-cells = <1>; 79 }; 80 81 tick-counter@10048 { 82 compatible = "sigma,tick-counter"; 83 reg = <0x10048 0x4>; 84 clocks = <&xtal>; 85 }; 86 87 uart: serial@10700 { 88 compatible = "ralink,rt2880-uart", "ns16550a"; 89 reg = <0x10700 0x30>; 90 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 91 clock-frequency = <7372800>; 92 reg-shift = <2>; 93 }; 94 95 watchdog@1fd00 { 96 compatible = "sigma,smp8759-wdt"; 97 reg = <0x1fd00 8>; 98 clocks = <&xtal>; 99 }; 100 101 mmc0: mmc@21000 { 102 compatible = "arasan,sdhci-8.9a"; 103 reg = <0x21000 0x200>; 104 clock-names = "clk_xin", "clk_ahb"; 105 clocks = <&clkgen SDIO_CLK>, <&clkgen SYS_CLK>; 106 interrupts = <60 IRQ_TYPE_LEVEL_HIGH>; 107 }; 108 109 mmc1: mmc@21200 { 110 compatible = "arasan,sdhci-8.9a"; 111 reg = <0x21200 0x200>; 112 clock-names = "clk_xin", "clk_ahb"; 113 clocks = <&clkgen SDIO_CLK>, <&clkgen SYS_CLK>; 114 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 115 }; 116 117 usb0: usb@21400 { 118 compatible = "chipidea,usb2"; 119 reg = <0x21400 0x200>; 120 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; 121 phys = <&usb0_phy>; 122 phy-names = "usb-phy"; 123 }; 124 125 usb0_phy: phy@21700 { 126 compatible = "sigma,smp8642-usb-phy"; 127 reg = <0x21700 0x100>; 128 #phy-cells = <0>; 129 clocks = <&clkgen USB_CLK>; 130 }; 131 132 usb1: usb@25400 { 133 compatible = "chipidea,usb2"; 134 reg = <0x25400 0x200>; 135 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 136 phys = <&usb1_phy>; 137 phy-names = "usb-phy"; 138 }; 139 140 usb1_phy: phy@25700 { 141 compatible = "sigma,smp8642-usb-phy"; 142 reg = <0x25700 0x100>; 143 #phy-cells = <0>; 144 clocks = <&clkgen USB_CLK>; 145 }; 146 147 eth0: ethernet@26000 { 148 compatible = "sigma,smp8734-ethernet"; 149 reg = <0x26000 0x800>; 150 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 151 clocks = <&clkgen SYS_CLK>; 152 }; 153 154 intc: interrupt-controller@6e000 { 155 compatible = "sigma,smp8642-intc"; 156 reg = <0x6e000 0x400>; 157 ranges = <0 0x6e000 0x400>; 158 interrupt-parent = <&gic>; 159 #address-cells = <1>; 160 #size-cells = <1>; 161 162 irq0: irq0@0 { 163 reg = <0x000 0x100>; 164 interrupt-controller; 165 #interrupt-cells = <2>; 166 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 167 }; 168 169 irq1: irq1@100 { 170 reg = <0x100 0x100>; 171 interrupt-controller; 172 #interrupt-cells = <2>; 173 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 174 }; 175 176 irq2: irq2@300 { 177 reg = <0x300 0x100>; 178 interrupt-controller; 179 #interrupt-cells = <2>; 180 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 181 }; 182 }; 183 }; 184 };
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