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sys/contrib/device-tree/src/arm/tegra20-acer-a500-picasso.dts
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1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 3 4 #include <dt-bindings/input/atmel-maxtouch.h> 5 #include <dt-bindings/input/gpio-keys.h> 6 #include <dt-bindings/input/input.h> 7 #include <dt-bindings/thermal/thermal.h> 8 9 #include "tegra20.dtsi" 10 #include "tegra20-cpu-opp.dtsi" 11 #include "tegra20-cpu-opp-microvolt.dtsi" 12 13 / { 14 model = "Acer Iconia Tab A500"; 15 compatible = "acer,picasso", "nvidia,tegra20"; 16 17 aliases { 18 mmc0 = &sdmmc4; /* eMMC */ 19 mmc1 = &sdmmc3; /* MicroSD */ 20 mmc2 = &sdmmc1; /* WiFi */ 21 22 rtc0 = &pmic; 23 rtc1 = "/rtc@7000e000"; 24 25 serial0 = &uartd; /* Docking station */ 26 serial1 = &uartc; /* Bluetooth */ 27 serial2 = &uartb; /* GPS */ 28 }; 29 30 /* 31 * The decompressor and also some bootloaders rely on a 32 * pre-existing /chosen node to be available to insert the 33 * command line and merge other ATAGS info. 34 */ 35 chosen {}; 36 37 memory@0 { 38 reg = <0x00000000 0x40000000>; 39 }; 40 41 reserved-memory { 42 #address-cells = <1>; 43 #size-cells = <1>; 44 ranges; 45 46 ramoops@2ffe0000 { 47 compatible = "ramoops"; 48 reg = <0x2ffe0000 0x10000>; /* 64kB */ 49 console-size = <0x8000>; /* 32kB */ 50 record-size = <0x400>; /* 1kB */ 51 ecc-size = <16>; 52 }; 53 54 linux,cma@30000000 { 55 compatible = "shared-dma-pool"; 56 alloc-ranges = <0x30000000 0x10000000>; 57 size = <0x10000000>; /* 256MiB */ 58 linux,cma-default; 59 reusable; 60 }; 61 }; 62 63 host1x@50000000 { 64 dc@54200000 { 65 rgb { 66 status = "okay"; 67 68 port@0 { 69 lcd_output: endpoint { 70 remote-endpoint = <&lvds_encoder_input>; 71 bus-width = <18>; 72 }; 73 }; 74 }; 75 }; 76 77 hdmi@54280000 { 78 status = "okay"; 79 80 vdd-supply = <&hdmi_vdd_reg>; 81 pll-supply = <&hdmi_pll_reg>; 82 hdmi-supply = <&vdd_5v0_sys>; 83 84 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 85 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 86 GPIO_ACTIVE_HIGH>; 87 }; 88 }; 89 90 pinmux@70000014 { 91 pinctrl-names = "default"; 92 pinctrl-0 = <&state_default>; 93 94 state_default: pinmux { 95 ata { 96 nvidia,pins = "ata"; 97 nvidia,function = "ide"; 98 }; 99 atb { 100 nvidia,pins = "atb", "gma", "gme"; 101 nvidia,function = "sdio4"; 102 }; 103 atc { 104 nvidia,pins = "atc"; 105 nvidia,function = "nand"; 106 }; 107 atd { 108 nvidia,pins = "atd", "ate", "gmb", "spia", 109 "spib", "spic"; 110 nvidia,function = "gmi"; 111 }; 112 cdev1 { 113 nvidia,pins = "cdev1"; 114 nvidia,function = "plla_out"; 115 }; 116 cdev2 { 117 nvidia,pins = "cdev2"; 118 nvidia,function = "pllp_out4"; 119 }; 120 crtp { 121 nvidia,pins = "crtp", "lm1"; 122 nvidia,function = "crt"; 123 }; 124 csus { 125 nvidia,pins = "csus"; 126 nvidia,function = "vi_sensor_clk"; 127 }; 128 dap1 { 129 nvidia,pins = "dap1"; 130 nvidia,function = "dap1"; 131 }; 132 dap2 { 133 nvidia,pins = "dap2"; 134 nvidia,function = "dap2"; 135 }; 136 dap3 { 137 nvidia,pins = "dap3"; 138 nvidia,function = "dap3"; 139 }; 140 dap4 { 141 nvidia,pins = "dap4"; 142 nvidia,function = "dap4"; 143 }; 144 dta { 145 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; 146 nvidia,function = "vi"; 147 }; 148 dtf { 149 nvidia,pins = "dtf"; 150 nvidia,function = "i2c3"; 151 }; 152 gmc { 153 nvidia,pins = "gmc"; 154 nvidia,function = "uartd"; 155 }; 156 gmd { 157 nvidia,pins = "gmd"; 158 nvidia,function = "sflash"; 159 }; 160 gpu { 161 nvidia,pins = "gpu"; 162 nvidia,function = "pwm"; 163 }; 164 gpu7 { 165 nvidia,pins = "gpu7"; 166 nvidia,function = "rtck"; 167 }; 168 gpv { 169 nvidia,pins = "gpv", "slxa"; 170 nvidia,function = "pcie"; 171 }; 172 hdint { 173 nvidia,pins = "hdint"; 174 nvidia,function = "hdmi"; 175 }; 176 i2cp { 177 nvidia,pins = "i2cp"; 178 nvidia,function = "i2cp"; 179 }; 180 irrx { 181 nvidia,pins = "irrx", "irtx"; 182 nvidia,function = "uartb"; 183 }; 184 kbca { 185 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 186 "kbce", "kbcf"; 187 nvidia,function = "kbc"; 188 }; 189 lcsn { 190 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", 191 "lsdi", "lvp0"; 192 nvidia,function = "rsvd4"; 193 }; 194 ld0 { 195 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 196 "ld5", "ld6", "ld7", "ld8", "ld9", 197 "ld10", "ld11", "ld12", "ld13", "ld14", 198 "ld15", "ld16", "ld17", "ldi", "lhp0", 199 "lhp1", "lhp2", "lhs", "lpp", "lsc0", 200 "lsc1", "lsck", "lsda", "lspi", "lvp1", 201 "lvs"; 202 nvidia,function = "displaya"; 203 }; 204 owc { 205 nvidia,pins = "owc", "spdi", "spdo", "uac"; 206 nvidia,function = "rsvd2"; 207 }; 208 pmc { 209 nvidia,pins = "pmc"; 210 nvidia,function = "pwr_on"; 211 }; 212 rm { 213 nvidia,pins = "rm"; 214 nvidia,function = "i2c1"; 215 }; 216 sdb { 217 nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; 218 nvidia,function = "sdio3"; 219 }; 220 sdio1 { 221 nvidia,pins = "sdio1"; 222 nvidia,function = "sdio1"; 223 }; 224 slxd { 225 nvidia,pins = "slxd"; 226 nvidia,function = "spdif"; 227 }; 228 spid { 229 nvidia,pins = "spid", "spie", "spif"; 230 nvidia,function = "spi1"; 231 }; 232 spig { 233 nvidia,pins = "spig", "spih"; 234 nvidia,function = "spi2_alt"; 235 }; 236 uaa { 237 nvidia,pins = "uaa", "uab", "uda"; 238 nvidia,function = "ulpi"; 239 }; 240 uad { 241 nvidia,pins = "uad"; 242 nvidia,function = "irda"; 243 }; 244 uca { 245 nvidia,pins = "uca", "ucb"; 246 nvidia,function = "uartc"; 247 }; 248 conf_ata { 249 nvidia,pins = "ata", "atb", "atc", "atd", 250 "cdev1", "cdev2", "csus", "dap1", 251 "dap4", "dte", "dtf", "gma", "gmc", 252 "gme", "gpu", "gpu7", "gpv", "i2cp", 253 "irrx", "irtx", "pta", "rm", 254 "sdc", "sdd", "slxc", "slxd", "slxk", 255 "spdi", "spdo", "uac", "uad", "uda"; 256 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 257 nvidia,tristate = <TEGRA_PIN_DISABLE>; 258 }; 259 conf_ate { 260 nvidia,pins = "ate", "dap2", "dap3", 261 "gmd", "owc", "spia", "spib", "spic", 262 "spid", "spie"; 263 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 264 nvidia,tristate = <TEGRA_PIN_ENABLE>; 265 }; 266 conf_ck32 { 267 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 268 "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 269 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 270 }; 271 conf_crtp { 272 nvidia,pins = "crtp", "gmb", "slxa", "spig", 273 "spih"; 274 nvidia,pull = <TEGRA_PIN_PULL_UP>; 275 nvidia,tristate = <TEGRA_PIN_ENABLE>; 276 }; 277 conf_dta { 278 nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb"; 279 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 280 nvidia,tristate = <TEGRA_PIN_DISABLE>; 281 }; 282 conf_dte { 283 nvidia,pins = "spif"; 284 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 285 nvidia,tristate = <TEGRA_PIN_ENABLE>; 286 }; 287 conf_hdint { 288 nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 289 "lpw1", "lsck", "lsda", "lsdi", 290 "lvp0"; 291 nvidia,tristate = <TEGRA_PIN_ENABLE>; 292 }; 293 conf_kbca { 294 nvidia,pins = "kbca", "kbcc", "kbcd", 295 "kbce", "kbcf", "sdio1", "uaa", 296 "uab", "uca", "ucb"; 297 nvidia,pull = <TEGRA_PIN_PULL_UP>; 298 nvidia,tristate = <TEGRA_PIN_DISABLE>; 299 }; 300 conf_lc { 301 nvidia,pins = "lc", "ls"; 302 nvidia,pull = <TEGRA_PIN_PULL_UP>; 303 }; 304 conf_ld0 { 305 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 306 "ld5", "ld6", "ld7", "ld8", "ld9", 307 "ld10", "ld11", "ld12", "ld13", "ld14", 308 "ld15", "ld16", "ld17", "ldi", "lhp0", 309 "lhp1", "lhp2", "lhs", "lm0", "lpp", 310 "lpw0", "lpw2", "lsc0", "lsc1", "lspi", 311 "lvp1", "lvs", "pmc", "sdb"; 312 nvidia,tristate = <TEGRA_PIN_DISABLE>; 313 }; 314 conf_ld17_0 { 315 nvidia,pins = "ld17_0"; 316 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 317 }; 318 drive_ddc { 319 nvidia,pins = "drive_ddc", 320 "drive_vi1", 321 "drive_sdio1"; 322 nvidia,pull-up-strength = <31>; 323 nvidia,pull-down-strength = <31>; 324 nvidia,schmitt = <TEGRA_PIN_ENABLE>; 325 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; 326 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 327 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 328 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 329 }; 330 drive_dbg { 331 nvidia,pins = "drive_dbg", 332 "drive_vi2", 333 "drive_at1", 334 "drive_ao1"; 335 nvidia,pull-up-strength = <31>; 336 nvidia,pull-down-strength = <31>; 337 nvidia,schmitt = <TEGRA_PIN_ENABLE>; 338 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; 339 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 340 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 341 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 342 }; 343 }; 344 345 state_i2cmux_ddc: pinmux_i2cmux_ddc { 346 ddc { 347 nvidia,pins = "ddc"; 348 nvidia,function = "i2c2"; 349 }; 350 pta { 351 nvidia,pins = "pta"; 352 nvidia,function = "rsvd4"; 353 }; 354 }; 355 356 state_i2cmux_pta: pinmux_i2cmux_pta { 357 ddc { 358 nvidia,pins = "ddc"; 359 nvidia,function = "rsvd4"; 360 }; 361 pta { 362 nvidia,pins = "pta"; 363 nvidia,function = "i2c2"; 364 }; 365 }; 366 367 state_i2cmux_idle: pinmux_i2cmux_idle { 368 ddc { 369 nvidia,pins = "ddc"; 370 nvidia,function = "rsvd4"; 371 }; 372 pta { 373 nvidia,pins = "pta"; 374 nvidia,function = "rsvd4"; 375 }; 376 }; 377 }; 378 379 tegra_spdif: spdif@70002400 { 380 status = "okay"; 381 382 nvidia,fixed-parent-rate; 383 }; 384 385 tegra_i2s1: i2s@70002800 { 386 status = "okay"; 387 388 nvidia,fixed-parent-rate; 389 }; 390 391 uartb: serial@70006040 { 392 compatible = "nvidia,tegra20-hsuart"; 393 /delete-property/ reg-shift; 394 /* GPS BCM4751 */ 395 }; 396 397 uartc: serial@70006200 { 398 compatible = "nvidia,tegra20-hsuart"; 399 /delete-property/ reg-shift; 400 status = "okay"; 401 402 /* Azurewave AW-NH665 BCM4329B1 */ 403 bluetooth { 404 compatible = "brcm,bcm4329-bt"; 405 406 interrupt-parent = <&gpio>; 407 interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>; 408 interrupt-names = "host-wakeup"; 409 410 /* PLLP 216MHz / 16 / 4 */ 411 max-speed = <3375000>; 412 413 clocks = <&rtc_32k_wifi>; 414 clock-names = "txco"; 415 416 vbat-supply = <&vdd_3v3_sys>; 417 vddio-supply = <&vdd_1v8_sys>; 418 419 device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; 420 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; 421 }; 422 }; 423 424 uartd: serial@70006300 { 425 /* Docking station */ 426 }; 427 428 i2c@7000c000 { 429 clock-frequency = <400000>; 430 status = "okay"; 431 432 wm8903: audio-codec@1a { 433 compatible = "wlf,wm8903"; 434 reg = <0x1a>; 435 436 interrupt-parent = <&gpio>; 437 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_BOTH>; 438 439 gpio-controller; 440 #gpio-cells = <2>; 441 442 micdet-cfg = <0>; 443 micdet-delay = <100>; 444 445 gpio-cfg = < 446 0x0000 /* MIC_LR_OUT# GPIO, output, low */ 447 0x0000 /* FM2018-enable GPIO, output, low */ 448 0x0000 /* Speaker-enable GPIO, output, low */ 449 0x0200 /* Interrupt, output */ 450 0x01a0 /* BCLK, input, active high */ 451 >; 452 453 AVDD-supply = <&vdd_1v8_sys>; 454 CPVDD-supply = <&vdd_1v8_sys>; 455 DBVDD-supply = <&vdd_1v8_sys>; 456 DCVDD-supply = <&vdd_1v8_sys>; 457 }; 458 459 touchscreen@4c { 460 compatible = "atmel,maxtouch"; 461 reg = <0x4c>; 462 463 interrupt-parent = <&gpio>; 464 interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>; 465 466 reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; 467 468 vdda-supply = <&vdd_3v3_sys>; 469 vdd-supply = <&vdd_3v3_sys>; 470 471 atmel,wakeup-method = <ATMEL_MXT_WAKEUP_I2C_SCL>; 472 }; 473 474 gyroscope@68 { 475 compatible = "invensense,mpu3050"; 476 reg = <0x68>; 477 478 interrupt-parent = <&gpio>; 479 interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>; 480 481 vdd-supply = <&vdd_3v3_sys>; 482 vlogic-supply = <&vdd_1v8_sys>; 483 484 mount-matrix = "0", "1", "0", 485 "1", "0", "0", 486 "0", "0", "-1"; 487 488 i2c-gate { 489 #address-cells = <1>; 490 #size-cells = <0>; 491 492 accelerometer@f { 493 compatible = "kionix,kxtf9"; 494 reg = <0x0f>; 495 496 interrupt-parent = <&gpio>; 497 interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>; 498 499 vdd-supply = <&vdd_1v8_sys>; 500 vddio-supply = <&vdd_1v8_sys>; 501 502 mount-matrix = "0", "1", "0", 503 "1", "0", "0", 504 "0", "0", "-1"; 505 }; 506 }; 507 }; 508 }; 509 510 i2c@7000c400 { 511 clock-frequency = <10000>; 512 status = "okay"; 513 }; 514 515 i2cmux { 516 compatible = "i2c-mux-pinctrl"; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 520 i2c-parent = <&{/i2c@7000c400}>; 521 522 pinctrl-names = "ddc", "pta", "idle"; 523 pinctrl-0 = <&state_i2cmux_ddc>; 524 pinctrl-1 = <&state_i2cmux_pta>; 525 pinctrl-2 = <&state_i2cmux_idle>; 526 527 hdmi_ddc: i2c@0 { 528 reg = <0>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 }; 532 533 panel_ddc: i2c@1 { 534 reg = <1>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 538 embedded-controller@58 { 539 compatible = "acer,a500-iconia-ec", "ene,kb930"; 540 reg = <0x58>; 541 542 system-power-controller; 543 544 monitored-battery = <&bat1010>; 545 power-supplies = <&mains>; 546 }; 547 }; 548 }; 549 550 pwm: pwm@7000a000 { 551 status = "okay"; 552 }; 553 554 i2c@7000d000 { 555 clock-frequency = <100000>; 556 status = "okay"; 557 558 magnetometer@c { 559 compatible = "asahi-kasei,ak8975"; 560 reg = <0x0c>; 561 562 interrupt-parent = <&gpio>; 563 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>; 564 565 vdd-supply = <&vdd_3v3_sys>; 566 vid-supply = <&vdd_1v8_sys>; 567 568 mount-matrix = "1", "0", "0", 569 "0", "-1", "0", 570 "0", "0", "-1"; 571 }; 572 573 pmic: pmic@34 { 574 compatible = "ti,tps6586x"; 575 reg = <0x34>; 576 577 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 578 579 #gpio-cells = <2>; 580 gpio-controller; 581 582 sys-supply = <&vdd_5v0_sys>; 583 vin-sm0-supply = <&sys_reg>; 584 vin-sm1-supply = <&sys_reg>; 585 vin-sm2-supply = <&sys_reg>; 586 vinldo01-supply = <&sm2_reg>; 587 vinldo23-supply = <&sm2_reg>; 588 vinldo4-supply = <&sm2_reg>; 589 vinldo678-supply = <&sm2_reg>; 590 vinldo9-supply = <&sm2_reg>; 591 592 regulators { 593 sys_reg: sys { 594 regulator-name = "vdd_sys"; 595 regulator-always-on; 596 }; 597 598 vdd_core: sm0 { 599 regulator-name = "vdd_sm0,vdd_core"; 600 regulator-min-microvolt = <950000>; 601 regulator-max-microvolt = <1300000>; 602 regulator-coupled-with = <&rtc_vdd &vdd_cpu>; 603 regulator-coupled-max-spread = <170000 550000>; 604 regulator-always-on; 605 regulator-boot-on; 606 607 nvidia,tegra-core-regulator; 608 }; 609 610 vdd_cpu: sm1 { 611 regulator-name = "vdd_sm1,vdd_cpu"; 612 regulator-min-microvolt = <750000>; 613 regulator-max-microvolt = <1125000>; 614 regulator-coupled-with = <&vdd_core &rtc_vdd>; 615 regulator-coupled-max-spread = <550000 550000>; 616 regulator-always-on; 617 regulator-boot-on; 618 619 nvidia,tegra-cpu-regulator; 620 }; 621 622 sm2_reg: sm2 { 623 regulator-name = "vdd_sm2,vin_ldo*"; 624 regulator-min-microvolt = <3700000>; 625 regulator-max-microvolt = <3700000>; 626 regulator-always-on; 627 }; 628 629 /* LDO0 is not connected to anything */ 630 631 ldo1 { 632 regulator-name = "vdd_ldo1,avdd_pll*"; 633 regulator-min-microvolt = <1100000>; 634 regulator-max-microvolt = <1100000>; 635 regulator-always-on; 636 regulator-boot-on; 637 }; 638 639 rtc_vdd: ldo2 { 640 regulator-name = "vdd_ldo2,vdd_rtc"; 641 regulator-min-microvolt = <950000>; 642 regulator-max-microvolt = <1300000>; 643 regulator-coupled-with = <&vdd_core &vdd_cpu>; 644 regulator-coupled-max-spread = <170000 550000>; 645 regulator-always-on; 646 regulator-boot-on; 647 648 nvidia,tegra-rtc-regulator; 649 }; 650 651 ldo3 { 652 regulator-name = "vdd_ldo3,avdd_usb*"; 653 regulator-min-microvolt = <3300000>; 654 regulator-max-microvolt = <3300000>; 655 regulator-always-on; 656 }; 657 658 ldo4 { 659 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 660 regulator-min-microvolt = <1800000>; 661 regulator-max-microvolt = <1800000>; 662 regulator-always-on; 663 regulator-boot-on; 664 }; 665 666 vcore_emmc: ldo5 { 667 regulator-name = "vdd_ldo5,vcore_mmc"; 668 regulator-min-microvolt = <2850000>; 669 regulator-max-microvolt = <2850000>; 670 regulator-always-on; 671 }; 672 673 avdd_vdac_reg: ldo6 { 674 regulator-name = "vdd_ldo6,avdd_vdac"; 675 regulator-min-microvolt = <2850000>; 676 regulator-max-microvolt = <2850000>; 677 }; 678 679 hdmi_vdd_reg: ldo7 { 680 regulator-name = "vdd_ldo7,avdd_hdmi"; 681 regulator-min-microvolt = <3300000>; 682 regulator-max-microvolt = <3300000>; 683 }; 684 685 hdmi_pll_reg: ldo8 { 686 regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 687 regulator-min-microvolt = <1800000>; 688 regulator-max-microvolt = <1800000>; 689 }; 690 691 ldo9 { 692 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; 693 regulator-min-microvolt = <2850000>; 694 regulator-max-microvolt = <2850000>; 695 regulator-always-on; 696 regulator-boot-on; 697 }; 698 699 ldo_rtc { 700 regulator-name = "vdd_rtc_out,vdd_cell"; 701 regulator-min-microvolt = <3300000>; 702 regulator-max-microvolt = <3300000>; 703 regulator-always-on; 704 regulator-boot-on; 705 }; 706 }; 707 }; 708 709 nct1008: temperature-sensor@4c { 710 compatible = "onnn,nct1008"; 711 reg = <0x4c>; 712 vcc-supply = <&vdd_3v3_sys>; 713 714 interrupt-parent = <&gpio>; 715 interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>; 716 717 #thermal-sensor-cells = <1>; 718 }; 719 }; 720 721 pmc@7000e400 { 722 nvidia,invert-interrupt; 723 nvidia,suspend-mode = <1>; 724 nvidia,cpu-pwr-good-time = <2000>; 725 nvidia,cpu-pwr-off-time = <100>; 726 nvidia,core-pwr-good-time = <3845 3845>; 727 nvidia,core-pwr-off-time = <458>; 728 nvidia,sys-clock-req-active-high; 729 core-supply = <&vdd_core>; 730 }; 731 732 usb@c5000000 { 733 compatible = "nvidia,tegra20-udc"; 734 status = "okay"; 735 dr_mode = "peripheral"; 736 }; 737 738 usb-phy@c5000000 { 739 status = "okay"; 740 dr_mode = "peripheral"; 741 nvidia,xcvr-setup-use-fuses; 742 nvidia,xcvr-lsfslew = <2>; 743 nvidia,xcvr-lsrslew = <2>; 744 }; 745 746 usb@c5008000 { 747 status = "okay"; 748 }; 749 750 usb-phy@c5008000 { 751 status = "okay"; 752 nvidia,xcvr-setup-use-fuses; 753 nvidia,xcvr-lsfslew = <2>; 754 nvidia,xcvr-lsrslew = <2>; 755 vbus-supply = <&vdd_5v0_sys>; 756 }; 757 758 brcm_wifi_pwrseq: wifi-pwrseq { 759 compatible = "mmc-pwrseq-simple"; 760 761 clocks = <&rtc_32k_wifi>; 762 clock-names = "ext_clock"; 763 764 reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; 765 post-power-on-delay-ms = <300>; 766 power-off-delay-us = <300>; 767 }; 768 769 sdmmc1: mmc@c8000000 { 770 status = "okay"; 771 772 #address-cells = <1>; 773 #size-cells = <0>; 774 775 assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; 776 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; 777 assigned-clock-rates = <50000000>; 778 779 max-frequency = <50000000>; 780 keep-power-in-suspend; 781 bus-width = <4>; 782 non-removable; 783 784 mmc-pwrseq = <&brcm_wifi_pwrseq>; 785 vmmc-supply = <&vdd_3v3_sys>; 786 vqmmc-supply = <&vdd_1v8_sys>; 787 788 /* Azurewave AW-NH611 BCM4329 */ 789 wifi@1 { 790 reg = <1>; 791 compatible = "brcm,bcm4329-fmac"; 792 interrupt-parent = <&gpio>; 793 interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>; 794 interrupt-names = "host-wake"; 795 }; 796 }; 797 798 sdmmc3: mmc@c8000400 { 799 status = "okay"; 800 bus-width = <4>; 801 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 802 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 803 vmmc-supply = <&vdd_3v3_sys>; 804 vqmmc-supply = <&vdd_3v3_sys>; 805 }; 806 807 sdmmc4: mmc@c8000600 { 808 status = "okay"; 809 bus-width = <8>; 810 vmmc-supply = <&vcore_emmc>; 811 vqmmc-supply = <&vdd_3v3_sys>; 812 non-removable; 813 }; 814 815 mains: ac-adapter-detect { 816 compatible = "gpio-charger"; 817 charger-type = "mains"; 818 gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; 819 }; 820 821 backlight: backlight { 822 compatible = "pwm-backlight"; 823 824 enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; 825 power-supply = <&vdd_3v3_sys>; 826 pwms = <&pwm 2 41667>; 827 828 brightness-levels = <7 255>; 829 num-interpolated-steps = <248>; 830 default-brightness-level = <20>; 831 }; 832 833 bat1010: battery-2s1p { 834 compatible = "simple-battery"; 835 charge-full-design-microamp-hours = <3260000>; 836 energy-full-design-microwatt-hours = <24000000>; 837 operating-range-celsius = <0 40>; 838 }; 839 840 /* PMIC has a built-in 32KHz oscillator which is used by PMC */ 841 clk32k_in: clock-32k-in { 842 compatible = "fixed-clock"; 843 #clock-cells = <0>; 844 clock-frequency = <32768>; 845 clock-output-names = "tps658621-out32k"; 846 }; 847 848 /* 849 * This standalone onboard fixed-clock always-ON 32KHz 850 * oscillator is used as a reference clock-source by the 851 * Azurewave WiFi/BT module. 852 */ 853 rtc_32k_wifi: clock-32k-wifi { 854 compatible = "fixed-clock"; 855 #clock-cells = <0>; 856 clock-frequency = <32768>; 857 clock-output-names = "kk3270032"; 858 }; 859 860 cpus { 861 cpu0: cpu@0 { 862 cpu-supply = <&vdd_cpu>; 863 operating-points-v2 = <&cpu0_opp_table>; 864 #cooling-cells = <2>; 865 }; 866 867 cpu1: cpu@1 { 868 cpu-supply = <&vdd_cpu>; 869 operating-points-v2 = <&cpu0_opp_table>; 870 #cooling-cells = <2>; 871 }; 872 }; 873 874 display-panel { 875 compatible = "auo,b101ew05", "panel-lvds"; 876 877 ddc-i2c-bus = <&panel_ddc>; 878 power-supply = <&vdd_pnl>; 879 backlight = <&backlight>; 880 881 width-mm = <218>; 882 height-mm = <135>; 883 884 data-mapping = "jeida-18"; 885 886 panel-timing { 887 clock-frequency = <71200000>; 888 hactive = <1280>; 889 vactive = <800>; 890 hfront-porch = <8>; 891 hback-porch = <18>; 892 hsync-len = <184>; 893 vsync-len = <3>; 894 vfront-porch = <4>; 895 vback-porch = <8>; 896 }; 897 898 port { 899 panel_input: endpoint { 900 remote-endpoint = <&lvds_encoder_output>; 901 }; 902 }; 903 }; 904 905 gpio-keys { 906 compatible = "gpio-keys"; 907 908 key-power { 909 label = "Power"; 910 gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; 911 linux,code = <KEY_POWER>; 912 debounce-interval = <10>; 913 wakeup-event-action = <EV_ACT_ASSERTED>; 914 wakeup-source; 915 }; 916 917 key-rotation-lock { 918 label = "Rotate-lock"; 919 gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>; 920 linux,code = <SW_ROTATE_LOCK>; 921 linux,input-type = <EV_SW>; 922 debounce-interval = <10>; 923 }; 924 925 key-volume-up { 926 label = "Volume Up"; 927 gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; 928 linux,code = <KEY_VOLUMEUP>; 929 debounce-interval = <10>; 930 wakeup-event-action = <EV_ACT_ASSERTED>; 931 wakeup-source; 932 }; 933 934 key-volume-down { 935 label = "Volume Down"; 936 gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; 937 linux,code = <KEY_VOLUMEDOWN>; 938 debounce-interval = <10>; 939 wakeup-event-action = <EV_ACT_ASSERTED>; 940 wakeup-source; 941 }; 942 }; 943 944 haptic-feedback { 945 compatible = "gpio-vibrator"; 946 enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; 947 vcc-supply = <&vdd_3v3_sys>; 948 }; 949 950 lvds-encoder { 951 compatible = "ti,sn75lvds83", "lvds-encoder"; 952 953 powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; 954 power-supply = <&vdd_3v3_sys>; 955 956 ports { 957 #address-cells = <1>; 958 #size-cells = <0>; 959 960 port@0 { 961 reg = <0>; 962 963 lvds_encoder_input: endpoint { 964 remote-endpoint = <&lcd_output>; 965 }; 966 }; 967 968 port@1 { 969 reg = <1>; 970 971 lvds_encoder_output: endpoint { 972 remote-endpoint = <&panel_input>; 973 }; 974 }; 975 }; 976 }; 977 978 vdd_5v0_sys: regulator-5v0 { 979 compatible = "regulator-fixed"; 980 regulator-name = "vdd_5v0"; 981 regulator-min-microvolt = <5000000>; 982 regulator-max-microvolt = <5000000>; 983 regulator-always-on; 984 }; 985 986 vdd_3v3_sys: regulator-3v3 { 987 compatible = "regulator-fixed"; 988 regulator-name = "vdd_3v3_vs"; 989 regulator-min-microvolt = <3300000>; 990 regulator-max-microvolt = <3300000>; 991 regulator-always-on; 992 vin-supply = <&vdd_5v0_sys>; 993 }; 994 995 vdd_1v8_sys: regulator-1v8 { 996 compatible = "regulator-fixed"; 997 regulator-name = "vdd_1v8_vs"; 998 regulator-min-microvolt = <1800000>; 999 regulator-max-microvolt = <1800000>; 1000 regulator-always-on; 1001 vin-supply = <&vdd_5v0_sys>; 1002 }; 1003 1004 vdd_pnl: regulator-panel { 1005 compatible = "regulator-fixed"; 1006 regulator-name = "vdd_panel"; 1007 regulator-min-microvolt = <3300000>; 1008 regulator-max-microvolt = <3300000>; 1009 regulator-enable-ramp-delay = <300000>; 1010 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; 1011 enable-active-high; 1012 vin-supply = <&vdd_5v0_sys>; 1013 }; 1014 1015 sound { 1016 compatible = "nvidia,tegra-audio-wm8903-picasso", 1017 "nvidia,tegra-audio-wm8903"; 1018 nvidia,model = "Acer Iconia Tab A500 WM8903"; 1019 1020 nvidia,audio-routing = 1021 "Headphone Jack", "HPOUTR", 1022 "Headphone Jack", "HPOUTL", 1023 "Int Spk", "LINEOUTL", 1024 "Int Spk", "LINEOUTR", 1025 "Mic Jack", "MICBIAS", 1026 "IN2L", "Mic Jack", 1027 "IN2R", "Mic Jack", 1028 "IN1L", "Int Mic", 1029 "IN1R", "Int Mic"; 1030 1031 nvidia,i2s-controller = <&tegra_i2s1>; 1032 nvidia,audio-codec = <&wm8903>; 1033 1034 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 1035 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; 1036 nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>; 1037 nvidia,headset; 1038 1039 clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 1040 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 1041 <&tegra_car TEGRA20_CLK_CDEV1>; 1042 clock-names = "pll_a", "pll_a_out0", "mclk"; 1043 }; 1044 1045 thermal-zones { 1046 /* 1047 * NCT1008 has two sensors: 1048 * 1049 * 0: internal that monitors ambient/skin temperature 1050 * 1: external that is connected to the CPU's diode 1051 * 1052 * Ideally we should use userspace thermal governor, 1053 * but it's a much more complex solution. The "skin" 1054 * zone is a simpler solution which prevents A500 from 1055 * getting too hot from a user's tactile perspective. 1056 * The CPU zone is intended to protect silicon from damage. 1057 */ 1058 1059 skin-thermal { 1060 polling-delay-passive = <1000>; /* milliseconds */ 1061 polling-delay = <5000>; /* milliseconds */ 1062 1063 thermal-sensors = <&nct1008 0>; 1064 1065 trips { 1066 trip0: skin-alert { 1067 /* start throttling at 60C */ 1068 temperature = <60000>; 1069 hysteresis = <200>; 1070 type = "passive"; 1071 }; 1072 1073 trip1: skin-crit { 1074 /* shut down at 70C */ 1075 temperature = <70000>; 1076 hysteresis = <2000>; 1077 type = "critical"; 1078 }; 1079 }; 1080 1081 cooling-maps { 1082 map0 { 1083 trip = <&trip0>; 1084 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1085 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1086 }; 1087 }; 1088 }; 1089 1090 cpu-thermal { 1091 polling-delay-passive = <1000>; /* milliseconds */ 1092 polling-delay = <5000>; /* milliseconds */ 1093 1094 thermal-sensors = <&nct1008 1>; 1095 1096 trips { 1097 trip2: cpu-alert { 1098 /* throttle at 85C until temperature drops to 84.8C */ 1099 temperature = <85000>; 1100 hysteresis = <200>; 1101 type = "passive"; 1102 }; 1103 1104 trip3: cpu-crit { 1105 /* shut down at 90C */ 1106 temperature = <90000>; 1107 hysteresis = <2000>; 1108 type = "critical"; 1109 }; 1110 }; 1111 1112 cooling-maps { 1113 map1 { 1114 trip = <&trip2>; 1115 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1116 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1117 }; 1118 }; 1119 }; 1120 }; 1121 1122 memory-controller@7000f400 { 1123 nvidia,use-ram-code; 1124 1125 emc-tables@0 { 1126 nvidia,ram-code = <0>; /* elpida-8gb */ 1127 reg = <0>; 1128 1129 #address-cells = <1>; 1130 #size-cells = <0>; 1131 1132 emc-table@25000 { 1133 reg = <25000>; 1134 compatible = "nvidia,tegra20-emc-table"; 1135 clock-frequency = <25000>; 1136 nvidia,emc-registers = <0x00000002 0x00000006 1137 0x00000003 0x00000003 0x00000006 0x00000004 1138 0x00000002 0x00000009 0x00000003 0x00000003 1139 0x00000002 0x00000002 0x00000002 0x00000004 1140 0x00000003 0x00000008 0x0000000b 0x0000004d 1141 0x00000000 0x00000003 0x00000003 0x00000003 1142 0x00000008 0x00000001 0x0000000a 0x00000004 1143 0x00000003 0x00000008 0x00000004 0x00000006 1144 0x00000002 0x00000068 0x00000000 0x00000003 1145 0x00000000 0x00000000 0x00000282 0xa0ae04ae 1146 0x00070000 0x00000000 0x00000000 0x00000003 1147 0x00000000 0x00000000 0x00000000 0x00000000>; 1148 }; 1149 1150 emc-table@50000 { 1151 reg = <50000>; 1152 compatible = "nvidia,tegra20-emc-table"; 1153 clock-frequency = <50000>; 1154 nvidia,emc-registers = <0x00000003 0x00000007 1155 0x00000003 0x00000003 0x00000006 0x00000004 1156 0x00000002 0x00000009 0x00000003 0x00000003 1157 0x00000002 0x00000002 0x00000002 0x00000005 1158 0x00000003 0x00000008 0x0000000b 0x0000009f 1159 0x00000000 0x00000003 0x00000003 0x00000003 1160 0x00000008 0x00000001 0x0000000a 0x00000007 1161 0x00000003 0x00000008 0x00000004 0x00000006 1162 0x00000002 0x000000d0 0x00000000 0x00000000 1163 0x00000000 0x00000000 0x00000282 0xa0ae04ae 1164 0x00070000 0x00000000 0x00000000 0x00000005 1165 0x00000000 0x00000000 0x00000000 0x00000000>; 1166 }; 1167 1168 emc-table@75000 { 1169 reg = <75000>; 1170 compatible = "nvidia,tegra20-emc-table"; 1171 clock-frequency = <75000>; 1172 nvidia,emc-registers = <0x00000005 0x0000000a 1173 0x00000004 0x00000003 0x00000006 0x00000004 1174 0x00000002 0x00000009 0x00000003 0x00000003 1175 0x00000002 0x00000002 0x00000002 0x00000005 1176 0x00000003 0x00000008 0x0000000b 0x000000ff 1177 0x00000000 0x00000003 0x00000003 0x00000003 1178 0x00000008 0x00000001 0x0000000a 0x0000000b 1179 0x00000003 0x00000008 0x00000004 0x00000006 1180 0x00000002 0x00000138 0x00000000 0x00000000 1181 0x00000000 0x00000000 0x00000282 0xa0ae04ae 1182 0x00070000 0x00000000 0x00000000 0x00000007 1183 0x00000000 0x00000000 0x00000000 0x00000000>; 1184 }; 1185 1186 emc-table@150000 { 1187 reg = <150000>; 1188 compatible = "nvidia,tegra20-emc-table"; 1189 clock-frequency = <150000>; 1190 nvidia,emc-registers = <0x00000009 0x00000014 1191 0x00000007 0x00000003 0x00000006 0x00000004 1192 0x00000002 0x00000009 0x00000003 0x00000003 1193 0x00000002 0x00000002 0x00000002 0x00000005 1194 0x00000003 0x00000008 0x0000000b 0x0000021f 1195 0x00000000 0x00000003 0x00000003 0x00000003 1196 0x00000008 0x00000001 0x0000000a 0x00000015 1197 0x00000003 0x00000008 0x00000004 0x00000006 1198 0x00000002 0x00000270 0x00000000 0x00000001 1199 0x00000000 0x00000000 0x00000282 0xa07c04ae 1200 0x007dd510 0x00000000 0x00000000 0x0000000e 1201 0x00000000 0x00000000 0x00000000 0x00000000>; 1202 }; 1203 1204 emc-table@300000 { 1205 reg = <300000>; 1206 compatible = "nvidia,tegra20-emc-table"; 1207 clock-frequency = <300000>; 1208 nvidia,emc-registers = <0x00000012 0x00000027 1209 0x0000000d 0x00000006 0x00000007 0x00000005 1210 0x00000003 0x00000009 0x00000006 0x00000006 1211 0x00000003 0x00000003 0x00000002 0x00000006 1212 0x00000003 0x00000009 0x0000000c 0x0000045f 1213 0x00000000 0x00000004 0x00000004 0x00000006 1214 0x00000008 0x00000001 0x0000000e 0x0000002a 1215 0x00000003 0x0000000f 0x00000007 0x00000005 1216 0x00000002 0x000004e1 0x00000005 0x00000002 1217 0x00000000 0x00000000 0x00000282 0xe059048b 1218 0x007e1510 0x00000000 0x00000000 0x0000001b 1219 0x00000000 0x00000000 0x00000000 0x00000000>; 1220 }; 1221 }; 1222 1223 emc-tables@1 { 1224 nvidia,ram-code = <1>; /* elpida-4gb */ 1225 reg = <1>; 1226 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 1230 emc-table@25000 { 1231 reg = <25000>; 1232 compatible = "nvidia,tegra20-emc-table"; 1233 clock-frequency = <25000>; 1234 nvidia,emc-registers = <0x00000002 0x00000006 1235 0x00000003 0x00000003 0x00000006 0x00000004 1236 0x00000002 0x00000009 0x00000003 0x00000003 1237 0x00000002 0x00000002 0x00000002 0x00000004 1238 0x00000003 0x00000008 0x0000000b 0x0000004d 1239 0x00000000 0x00000003 0x00000003 0x00000003 1240 0x00000008 0x00000001 0x0000000a 0x00000004 1241 0x00000003 0x00000008 0x00000004 0x00000006 1242 0x00000002 0x00000068 0x00000000 0x00000003 1243 0x00000000 0x00000000 0x00000282 0xa0ae04ae 1244 0x0007c000 0x00000000 0x00000000 0x00000003 1245 0x00000000 0x00000000 0x00000000 0x00000000>; 1246 }; 1247 1248 emc-table@50000 { 1249 reg = <50000>; 1250 compatible = "nvidia,tegra20-emc-table"; 1251 clock-frequency = <50000>; 1252 nvidia,emc-registers = <0x00000003 0x00000007 1253 0x00000003 0x00000003 0x00000006 0x00000004 1254 0x00000002 0x00000009 0x00000003 0x00000003 1255 0x00000002 0x00000002 0x00000002 0x00000005 1256 0x00000003 0x00000008 0x0000000b 0x0000009f 1257 0x00000000 0x00000003 0x00000003 0x00000003 1258 0x00000008 0x00000001 0x0000000a 0x00000007 1259 0x00000003 0x00000008 0x00000004 0x00000006 1260 0x00000002 0x000000d0 0x00000000 0x00000000 1261 0x00000000 0x00000000 0x00000282 0xa0ae04ae 1262 0x0007c000 0x00000000 0x00000000 0x00000005 1263 0x00000000 0x00000000 0x00000000 0x00000000>; 1264 }; 1265 1266 emc-table@75000 { 1267 reg = <75000>; 1268 compatible = "nvidia,tegra20-emc-table"; 1269 clock-frequency = <75000>; 1270 nvidia,emc-registers = <0x00000005 0x0000000a 1271 0x00000004 0x00000003 0x00000006 0x00000004 1272 0x00000002 0x00000009 0x00000003 0x00000003 1273 0x00000002 0x00000002 0x00000002 0x00000005 1274 0x00000003 0x00000008 0x0000000b 0x000000ff 1275 0x00000000 0x00000003 0x00000003 0x00000003 1276 0x00000008 0x00000001 0x0000000a 0x0000000b 1277 0x00000003 0x00000008 0x00000004 0x00000006 1278 0x00000002 0x00000138 0x00000000 0x00000000 1279 0x00000000 0x00000000 0x00000282 0xa0ae04ae 1280 0x0007c000 0x00000000 0x00000000 0x00000007 1281 0x00000000 0x00000000 0x00000000 0x00000000>; 1282 }; 1283 1284 emc-table@150000 { 1285 reg = <150000>; 1286 compatible = "nvidia,tegra20-emc-table"; 1287 clock-frequency = <150000>; 1288 nvidia,emc-registers = <0x00000009 0x00000014 1289 0x00000007 0x00000003 0x00000006 0x00000004 1290 0x00000002 0x00000009 0x00000003 0x00000003 1291 0x00000002 0x00000002 0x00000002 0x00000005 1292 0x00000003 0x00000008 0x0000000b 0x0000021f 1293 0x00000000 0x00000003 0x00000003 0x00000003 1294 0x00000008 0x00000001 0x0000000a 0x00000015 1295 0x00000003 0x00000008 0x00000004 0x00000006 1296 0x00000002 0x00000270 0x00000000 0x00000001 1297 0x00000000 0x00000000 0x00000282 0xa07c04ae 1298 0x007e4010 0x00000000 0x00000000 0x0000000e 1299 0x00000000 0x00000000 0x00000000 0x00000000>; 1300 }; 1301 1302 emc-table@300000 { 1303 reg = <300000>; 1304 compatible = "nvidia,tegra20-emc-table"; 1305 clock-frequency = <300000>; 1306 nvidia,emc-registers = <0x00000012 0x00000027 1307 0x0000000d 0x00000006 0x00000007 0x00000005 1308 0x00000003 0x00000009 0x00000006 0x00000006 1309 0x00000003 0x00000003 0x00000002 0x00000006 1310 0x00000003 0x00000009 0x0000000c 0x0000045f 1311 0x00000000 0x00000004 0x00000004 0x00000006 1312 0x00000008 0x00000001 0x0000000e 0x0000002a 1313 0x00000003 0x0000000f 0x00000007 0x00000005 1314 0x00000002 0x000004e1 0x00000005 0x00000002 1315 0x00000000 0x00000000 0x00000282 0xe059048b 1316 0x007e0010 0x00000000 0x00000000 0x0000001b 1317 0x00000000 0x00000000 0x00000000 0x00000000>; 1318 }; 1319 }; 1320 1321 emc-tables@2 { 1322 nvidia,ram-code = <2>; /* hynix-8gb */ 1323 reg = <2>; 1324 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 1328 emc-table@25000 { 1329 reg = <25000>; 1330 compatible = "nvidia,tegra20-emc-table"; 1331 clock-frequency = <25000>; 1332 nvidia,emc-registers = <0x00000002 0x00000006 1333 0x00000003 0x00000003 0x00000006 0x00000004 1334 0x00000002 0x00000009 0x00000003 0x00000003 1335 0x00000002 0x00000002 0x00000002 0x00000004 1336 0x00000003 0x00000008 0x0000000b 0x0000004d 1337 0x00000000 0x00000003 0x00000003 0x00000003 1338 0x00000008 0x00000001 0x0000000a 0x00000004 1339 0x00000003 0x00000008 0x00000004 0x00000006 1340 0x00000002 0x00000068 0x00000000 0x00000003 1341 0x00000000 0x00000000 0x00000282 0xa0ae04ae 1342 0x00070000 0x00000000 0x00000000 0x00000003 1343 0x00000000 0x00000000 0x00000000 0x00000000>; 1344 }; 1345 1346 emc-table@50000 { 1347 reg = <50000>; 1348 compatible = "nvidia,tegra20-emc-table"; 1349 clock-frequency = <50000>; 1350 nvidia,emc-registers = <0x00000003 0x00000007 1351 0x00000003 0x00000003 0x00000006 0x00000004 1352 0x00000002 0x00000009 0x00000003 0x00000003 1353 0x00000002 0x00000002 0x00000002 0x00000005 1354 0x00000003 0x00000008 0x0000000b 0x0000009f 1355 0x00000000 0x00000003 0x00000003 0x00000003 1356 0x00000008 0x00000001 0x0000000a 0x00000007 1357 0x00000003 0x00000008 0x00000004 0x00000006 1358 0x00000002 0x000000d0 0x00000000 0x00000000 1359 0x00000000 0x00000000 0x00000282 0xa0ae04ae 1360 0x00070000 0x00000000 0x00000000 0x00000005 1361 0x00000000 0x00000000 0x00000000 0x00000000>; 1362 }; 1363 1364 emc-table@75000 { 1365 reg = <75000>; 1366 compatible = "nvidia,tegra20-emc-table"; 1367 clock-frequency = <75000>; 1368 nvidia,emc-registers = <0x00000005 0x0000000a 1369 0x00000004 0x00000003 0x00000006 0x00000004 1370 0x00000002 0x00000009 0x00000003 0x00000003 1371 0x00000002 0x00000002 0x00000002 0x00000005 1372 0x00000003 0x00000008 0x0000000b 0x000000ff 1373 0x00000000 0x00000003 0x00000003 0x00000003 1374 0x00000008 0x00000001 0x0000000a 0x0000000b 1375 0x00000003 0x00000008 0x00000004 0x00000006 1376 0x00000002 0x00000138 0x00000000 0x00000000 1377 0x00000000 0x00000000 0x00000282 0xa0ae04ae 1378 0x00070000 0x00000000 0x00000000 0x00000007 1379 0x00000000 0x00000000 0x00000000 0x00000000>; 1380 }; 1381 1382 emc-table@150000 { 1383 reg = <150000>; 1384 compatible = "nvidia,tegra20-emc-table"; 1385 clock-frequency = <150000>; 1386 nvidia,emc-registers = <0x00000009 0x00000014 1387 0x00000007 0x00000003 0x00000006 0x00000004 1388 0x00000002 0x00000009 0x00000003 0x00000003 1389 0x00000002 0x00000002 0x00000002 0x00000005 1390 0x00000003 0x00000008 0x0000000b 0x0000021f 1391 0x00000000 0x00000003 0x00000003 0x00000003 1392 0x00000008 0x00000001 0x0000000a 0x00000015 1393 0x00000003 0x00000008 0x00000004 0x00000006 1394 0x00000002 0x00000270 0x00000000 0x00000001 1395 0x00000000 0x00000000 0x00000282 0xa07c04ae 1396 0x007dd010 0x00000000 0x00000000 0x0000000e 1397 0x00000000 0x00000000 0x00000000 0x00000000>; 1398 }; 1399 1400 emc-table@300000 { 1401 reg = <300000>; 1402 compatible = "nvidia,tegra20-emc-table"; 1403 clock-frequency = <300000>; 1404 nvidia,emc-registers = <0x00000012 0x00000027 1405 0x0000000d 0x00000006 0x00000007 0x00000005 1406 0x00000003 0x00000009 0x00000006 0x00000006 1407 0x00000003 0x00000003 0x00000002 0x00000006 1408 0x00000003 0x00000009 0x0000000c 0x0000045f 1409 0x00000000 0x00000004 0x00000004 0x00000006 1410 0x00000008 0x00000001 0x0000000e 0x0000002a 1411 0x00000003 0x0000000f 0x00000007 0x00000005 1412 0x00000002 0x000004e1 0x00000005 0x00000002 1413 0x00000000 0x00000000 0x00000282 0xe059048b 1414 0x007e2010 0x00000000 0x00000000 0x0000001b 1415 0x00000000 0x00000000 0x00000000 0x00000000>; 1416 }; 1417 }; 1418 1419 emc-tables@3 { 1420 nvidia,ram-code = <3>; /* hynix-4gb */ 1421 reg = <3>; 1422 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 1426 emc-table@25000 { 1427 reg = <25000>; 1428 compatible = "nvidia,tegra20-emc-table"; 1429 clock-frequency = <25000>; 1430 nvidia,emc-registers = <0x00000002 0x00000006 1431 0x00000003 0x00000003 0x00000006 0x00000004 1432 0x00000002 0x00000009 0x00000003 0x00000003 1433 0x00000002 0x00000002 0x00000002 0x00000004 1434 0x00000003 0x00000008 0x0000000b 0x0000004d 1435 0x00000000 0x00000003 0x00000003 0x00000003 1436 0x00000008 0x00000001 0x0000000a 0x00000004 1437 0x00000003 0x00000008 0x00000004 0x00000006 1438 0x00000002 0x00000068 0x00000000 0x00000003 1439 0x00000000 0x00000000 0x00000282 0xa0ae04ae 1440 0x0007c000 0x00000000 0x00000000 0x00000003 1441 0x00000000 0x00000000 0x00000000 0x00000000>; 1442 }; 1443 1444 emc-table@50000 { 1445 reg = <50000>; 1446 compatible = "nvidia,tegra20-emc-table"; 1447 clock-frequency = <50000>; 1448 nvidia,emc-registers = <0x00000003 0x00000007 1449 0x00000003 0x00000003 0x00000006 0x00000004 1450 0x00000002 0x00000009 0x00000003 0x00000003 1451 0x00000002 0x00000002 0x00000002 0x00000005 1452 0x00000003 0x00000008 0x0000000b 0x0000009f 1453 0x00000000 0x00000003 0x00000003 0x00000003 1454 0x00000008 0x00000001 0x0000000a 0x00000007 1455 0x00000003 0x00000008 0x00000004 0x00000006 1456 0x00000002 0x000000d0 0x00000000 0x00000000 1457 0x00000000 0x00000000 0x00000282 0xa0ae04ae 1458 0x0007c000 0x00078000 0x00000000 0x00000005 1459 0x00000000 0x00000000 0x00000000 0x00000000>; 1460 }; 1461 1462 emc-table@75000 { 1463 reg = <75000>; 1464 compatible = "nvidia,tegra20-emc-table"; 1465 clock-frequency = <75000>; 1466 nvidia,emc-registers = <0x00000005 0x0000000a 1467 0x00000004 0x00000003 0x00000006 0x00000004 1468 0x00000002 0x00000009 0x00000003 0x00000003 1469 0x00000002 0x00000002 0x00000002 0x00000005 1470 0x00000003 0x00000008 0x0000000b 0x000000ff 1471 0x00000000 0x00000003 0x00000003 0x00000003 1472 0x00000008 0x00000001 0x0000000a 0x0000000b 1473 0x00000003 0x00000008 0x00000004 0x00000006 1474 0x00000002 0x00000138 0x00000000 0x00000000 1475 0x00000000 0x00000000 0x00000282 0xa0ae04ae 1476 0x0007c000 0x00000000 0x00000000 0x00000007 1477 0x00000000 0x00000000 0x00000000 0x00000000>; 1478 }; 1479 1480 emc-table@150000 { 1481 reg = <150000>; 1482 compatible = "nvidia,tegra20-emc-table"; 1483 clock-frequency = <150000>; 1484 nvidia,emc-registers = <0x00000009 0x00000014 1485 0x00000007 0x00000003 0x00000006 0x00000004 1486 0x00000002 0x00000009 0x00000003 0x00000003 1487 0x00000002 0x00000002 0x00000002 0x00000005 1488 0x00000003 0x00000008 0x0000000b 0x0000021f 1489 0x00000000 0x00000003 0x00000003 0x00000003 1490 0x00000008 0x00000001 0x0000000a 0x00000015 1491 0x00000003 0x00000008 0x00000004 0x00000006 1492 0x00000002 0x00000270 0x00000000 0x00000001 1493 0x00000000 0x00000000 0x00000282 0xa07c04ae 1494 0x007e4010 0x00000000 0x00000000 0x0000000e 1495 0x00000000 0x00000000 0x00000000 0x00000000>; 1496 }; 1497 1498 emc-table@300000 { 1499 reg = <300000>; 1500 compatible = "nvidia,tegra20-emc-table"; 1501 clock-frequency = <300000>; 1502 nvidia,emc-registers = <0x00000012 0x00000027 1503 0x0000000d 0x00000006 0x00000007 0x00000005 1504 0x00000003 0x00000009 0x00000006 0x00000006 1505 0x00000003 0x00000003 0x00000002 0x00000006 1506 0x00000003 0x00000009 0x0000000c 0x0000045f 1507 0x00000000 0x00000004 0x00000004 0x00000006 1508 0x00000008 0x00000001 0x0000000e 0x0000002a 1509 0x00000003 0x0000000f 0x00000007 0x00000005 1510 0x00000002 0x000004e1 0x00000005 0x00000002 1511 0x00000000 0x00000000 0x00000282 0xe059048b 1512 0x007e0010 0x00000000 0x00000000 0x0000001b 1513 0x00000000 0x00000000 0x00000000 0x00000000>; 1514 }; 1515 }; 1516 }; 1517 }; 1518 1519 &emc_icc_dvfs_opp_table { 1520 /delete-node/ opp-666000000; 1521 /delete-node/ opp-760000000; 1522 };
Cache object: af8f32804646729bed7483f4f1d05f18
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