| 
     1 // SPDX-License-Identifier: GPL-2.0
    2 /dts-v1/;
    3 
    4 #include "tegra20-tamonten.dtsi"
    5 
    6 / {
    7         model = "Avionic Design Plutux board";
    8         compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
    9 
   10         host1x@50000000 {
   11                 hdmi@54280000 {
   12                         status = "okay";
   13                 };
   14         };
   15 
   16         i2c@7000c000 {
   17                 wm8903: wm8903@1a {
   18                         compatible = "wlf,wm8903";
   19                         reg = <0x1a>;
   20                         interrupt-parent = <&gpio>;
   21                         interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
   22 
   23                         gpio-controller;
   24                         #gpio-cells = <2>;
   25 
   26                         micdet-cfg = <0>;
   27                         micdet-delay = <100>;
   28                         gpio-cfg = <0xffffffff
   29                                     0xffffffff
   30                                     0
   31                                     0xffffffff
   32                                     0xffffffff>;
   33                 };
   34         };
   35 
   36         sound {
   37                 compatible = "ad,tegra-audio-plutux",
   38                              "nvidia,tegra-audio-wm8903";
   39                 nvidia,model = "Avionic Design Plutux";
   40 
   41                 nvidia,audio-routing =
   42                         "Headphone Jack", "HPOUTR",
   43                         "Headphone Jack", "HPOUTL",
   44                         "Int Spk", "ROP",
   45                         "Int Spk", "RON",
   46                         "Int Spk", "LOP",
   47                         "Int Spk", "LON",
   48                         "Mic Jack", "MICBIAS",
   49                         "IN1L", "Mic Jack";
   50 
   51                 nvidia,i2s-controller = <&tegra_i2s1>;
   52                 nvidia,audio-codec = <&wm8903>;
   53 
   54                 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
   55                 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
   56 
   57                 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
   58                          <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
   59                          <&tegra_car TEGRA20_CLK_CDEV1>;
   60                 clock-names = "pll_a", "pll_a_out0", "mclk";
   61         };
   62 
   63         vcc_24v_reg: regulator-24v0 {
   64                 compatible = "regulator-fixed";
   65                 regulator-name = "vcc_24v";
   66                 regulator-min-microvolt = <24000000>;
   67                 regulator-max-microvolt = <24000000>;
   68                 regulator-always-on;
   69         };
   70 
   71         vdd_5v0_reg: regulator-5v0 {
   72                 compatible = "regulator-fixed";
   73                 regulator-name = "vdd_5v0";
   74                 vin-supply = <&vcc_24v_reg>;
   75                 regulator-min-microvolt = <5000000>;
   76                 regulator-max-microvolt = <5000000>;
   77                 regulator-always-on;
   78         };
   79 
   80         vdd_3v3_reg: regulator-3v3 {
   81                 compatible = "regulator-fixed";
   82                 regulator-name = "vdd_3v3";
   83                 vin-supply = <&vcc_24v_reg>;
   84                 regulator-min-microvolt = <3300000>;
   85                 regulator-max-microvolt = <3300000>;
   86                 regulator-always-on;
   87         };
   88 
   89         vdd_1v8_reg: regulator-1v8 {
   90                 compatible = "regulator-fixed";
   91                 regulator-name = "vdd_1v8";
   92                 vin-supply = <&vdd_3v3_reg>;
   93                 regulator-min-microvolt = <1800000>;
   94                 regulator-max-microvolt = <1800000>;
   95                 regulator-always-on;
   96         };
   97 };
Cache object: 82a22e8bd3725cdb464e2755dc062e3d 
 
 |