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sys/contrib/device-tree/src/arm/tegra30-apalis-v1.1.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 #include "tegra30.dtsi" 3 4 /* 5 * Toradex Apalis T30 Module Device Tree 6 * Compatible for Revisions 1GB: V1.1A, V1.1B; 1GB IT: V1.1A, V1.1B; 7 * 2GB: V1.1A, V1.1B 8 */ 9 / { 10 memory@80000000 { 11 reg = <0x80000000 0x40000000>; 12 }; 13 14 pcie@3000 { 15 status = "okay"; 16 avdd-pexa-supply = <&vdd2_reg>; 17 avdd-pexb-supply = <&vdd2_reg>; 18 avdd-pex-pll-supply = <&vdd2_reg>; 19 avdd-plle-supply = <&ldo6_reg>; 20 hvdd-pex-supply = <®_module_3v3>; 21 vddio-pex-ctl-supply = <®_module_3v3>; 22 vdd-pexa-supply = <&vdd2_reg>; 23 vdd-pexb-supply = <&vdd2_reg>; 24 25 /* Apalis type specific */ 26 pci@1,0 { 27 nvidia,num-lanes = <4>; 28 }; 29 30 /* Apalis PCIe */ 31 pci@2,0 { 32 nvidia,num-lanes = <1>; 33 }; 34 35 /* I210/I211 Gigabit Ethernet Controller (on-module) */ 36 pci@3,0 { 37 status = "okay"; 38 nvidia,num-lanes = <1>; 39 40 ethernet@0,0 { 41 reg = <0 0 0 0 0>; 42 local-mac-address = [00 00 00 00 00 00]; 43 }; 44 }; 45 }; 46 47 host1x@50000000 { 48 hdmi@54280000 { 49 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 50 nvidia,hpd-gpio = 51 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 52 pll-supply = <®_1v8_avdd_hdmi_pll>; 53 vdd-supply = <®_3v3_avdd_hdmi>; 54 }; 55 }; 56 57 pinmux@70000868 { 58 pinctrl-names = "default"; 59 pinctrl-0 = <&state_default>; 60 61 state_default: pinmux { 62 /* Analogue Audio (On-module) */ 63 clk1-out-pw4 { 64 nvidia,pins = "clk1_out_pw4"; 65 nvidia,function = "extperiph1"; 66 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 67 nvidia,tristate = <TEGRA_PIN_DISABLE>; 68 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 69 }; 70 dap3-fs-pp0 { 71 nvidia,pins = "dap3_fs_pp0", 72 "dap3_sclk_pp3", 73 "dap3_din_pp1", 74 "dap3_dout_pp2"; 75 nvidia,function = "i2s2"; 76 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 77 nvidia,tristate = <TEGRA_PIN_DISABLE>; 78 }; 79 80 /* Apalis BKL1_ON */ 81 pv2 { 82 nvidia,pins = "pv2"; 83 nvidia,function = "rsvd4"; 84 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 85 nvidia,tristate = <TEGRA_PIN_DISABLE>; 86 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 87 }; 88 89 /* Apalis BKL1_PWM */ 90 uart3-rts-n-pc0 { 91 nvidia,pins = "uart3_rts_n_pc0"; 92 nvidia,function = "pwm0"; 93 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 94 nvidia,tristate = <TEGRA_PIN_DISABLE>; 95 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 96 }; 97 /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */ 98 uart3-cts-n-pa1 { 99 nvidia,pins = "uart3_cts_n_pa1"; 100 nvidia,function = "rsvd2"; 101 nvidia,pull = <TEGRA_PIN_PULL_UP>; 102 nvidia,tristate = <TEGRA_PIN_DISABLE>; 103 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 104 }; 105 106 /* Apalis CAN1 on SPI6 */ 107 spi2-cs0-n-px3 { 108 nvidia,pins = "spi2_cs0_n_px3", 109 "spi2_miso_px1", 110 "spi2_mosi_px0", 111 "spi2_sck_px2"; 112 nvidia,function = "spi6"; 113 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 114 nvidia,tristate = <TEGRA_PIN_DISABLE>; 115 }; 116 /* CAN_INT1 */ 117 spi2-cs1-n-pw2 { 118 nvidia,pins = "spi2_cs1_n_pw2"; 119 nvidia,function = "spi3"; 120 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 121 nvidia,tristate = <TEGRA_PIN_DISABLE>; 122 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 123 }; 124 125 /* Apalis CAN2 on SPI4 */ 126 gmi-a16-pj7 { 127 nvidia,pins = "gmi_a16_pj7", 128 "gmi_a17_pb0", 129 "gmi_a18_pb1", 130 "gmi_a19_pk7"; 131 nvidia,function = "spi4"; 132 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 133 nvidia,tristate = <TEGRA_PIN_DISABLE>; 134 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 135 }; 136 /* CAN_INT2 */ 137 spi2-cs2-n-pw3 { 138 nvidia,pins = "spi2_cs2_n_pw3"; 139 nvidia,function = "spi3"; 140 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 141 nvidia,tristate = <TEGRA_PIN_DISABLE>; 142 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 143 }; 144 145 /* Apalis Digital Audio */ 146 clk1-req-pee2 { 147 nvidia,pins = "clk1_req_pee2"; 148 nvidia,function = "hda"; 149 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 150 nvidia,tristate = <TEGRA_PIN_DISABLE>; 151 }; 152 clk2-out-pw5 { 153 nvidia,pins = "clk2_out_pw5"; 154 nvidia,function = "extperiph2"; 155 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 156 nvidia,tristate = <TEGRA_PIN_DISABLE>; 157 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 158 }; 159 dap1-fs-pn0 { 160 nvidia,pins = "dap1_fs_pn0", 161 "dap1_din_pn1", 162 "dap1_dout_pn2", 163 "dap1_sclk_pn3"; 164 nvidia,function = "hda"; 165 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 166 nvidia,tristate = <TEGRA_PIN_DISABLE>; 167 }; 168 169 /* Apalis GPIO */ 170 kb-col0-pq0 { 171 nvidia,pins = "kb_col0_pq0", 172 "kb_col1_pq1", 173 "kb_row10_ps2", 174 "kb_row11_ps3", 175 "kb_row12_ps4", 176 "kb_row13_ps5", 177 "kb_row14_ps6", 178 "kb_row15_ps7"; 179 nvidia,function = "kbc"; 180 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 181 nvidia,tristate = <TEGRA_PIN_DISABLE>; 182 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 183 }; 184 /* Multiplexed and therefore disabled */ 185 owr { 186 nvidia,pins = "owr"; 187 nvidia,function = "rsvd3"; 188 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 189 nvidia,tristate = <TEGRA_PIN_ENABLE>; 190 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 191 }; 192 193 /* Apalis HDMI1 */ 194 hdmi-cec-pee3 { 195 nvidia,pins = "hdmi_cec_pee3"; 196 nvidia,function = "cec"; 197 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 198 nvidia,tristate = <TEGRA_PIN_DISABLE>; 199 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 200 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 201 }; 202 hdmi-int-pn7 { 203 nvidia,pins = "hdmi_int_pn7"; 204 nvidia,function = "hdmi"; 205 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 206 nvidia,tristate = <TEGRA_PIN_ENABLE>; 207 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 208 }; 209 210 /* Apalis I2C1 */ 211 gen1-i2c-scl-pc4 { 212 nvidia,pins = "gen1_i2c_scl_pc4", 213 "gen1_i2c_sda_pc5"; 214 nvidia,function = "i2c1"; 215 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 216 nvidia,tristate = <TEGRA_PIN_DISABLE>; 217 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 218 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 219 }; 220 221 /* Apalis I2C2 (DDC) */ 222 ddc-scl-pv4 { 223 nvidia,pins = "ddc_scl_pv4", 224 "ddc_sda_pv5"; 225 nvidia,function = "i2c4"; 226 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 227 nvidia,tristate = <TEGRA_PIN_DISABLE>; 228 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 229 }; 230 231 /* Apalis I2C3 (CAM) */ 232 cam-i2c-scl-pbb1 { 233 nvidia,pins = "cam_i2c_scl_pbb1", 234 "cam_i2c_sda_pbb2"; 235 nvidia,function = "i2c3"; 236 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 237 nvidia,tristate = <TEGRA_PIN_DISABLE>; 238 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 239 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 240 }; 241 242 /* Apalis LCD1 */ 243 lcd-d0-pe0 { 244 nvidia,pins = "lcd_d0_pe0", 245 "lcd_d1_pe1", 246 "lcd_d2_pe2", 247 "lcd_d3_pe3", 248 "lcd_d4_pe4", 249 "lcd_d5_pe5", 250 "lcd_d6_pe6", 251 "lcd_d7_pe7", 252 "lcd_d8_pf0", 253 "lcd_d9_pf1", 254 "lcd_d10_pf2", 255 "lcd_d11_pf3", 256 "lcd_d12_pf4", 257 "lcd_d13_pf5", 258 "lcd_d14_pf6", 259 "lcd_d15_pf7", 260 "lcd_d16_pm0", 261 "lcd_d17_pm1", 262 "lcd_d18_pm2", 263 "lcd_d19_pm3", 264 "lcd_d20_pm4", 265 "lcd_d21_pm5", 266 "lcd_d22_pm6", 267 "lcd_d23_pm7", 268 "lcd_de_pj1", 269 "lcd_hsync_pj3", 270 "lcd_pclk_pb3", 271 "lcd_vsync_pj4"; 272 nvidia,function = "displaya"; 273 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 274 nvidia,tristate = <TEGRA_PIN_DISABLE>; 275 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 276 }; 277 278 /* Apalis MMC1 */ 279 sdmmc3-clk-pa6 { 280 nvidia,pins = "sdmmc3_clk_pa6"; 281 nvidia,function = "sdmmc3"; 282 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 283 nvidia,tristate = <TEGRA_PIN_DISABLE>; 284 }; 285 sdmmc3-dat0-pb7 { 286 nvidia,pins = "sdmmc3_cmd_pa7", 287 "sdmmc3_dat0_pb7", 288 "sdmmc3_dat1_pb6", 289 "sdmmc3_dat2_pb5", 290 "sdmmc3_dat3_pb4", 291 "sdmmc3_dat4_pd1", 292 "sdmmc3_dat5_pd0", 293 "sdmmc3_dat6_pd3", 294 "sdmmc3_dat7_pd4"; 295 nvidia,function = "sdmmc3"; 296 nvidia,pull = <TEGRA_PIN_PULL_UP>; 297 nvidia,tristate = <TEGRA_PIN_DISABLE>; 298 }; 299 /* Apalis MMC1_CD# */ 300 pv3 { 301 nvidia,pins = "pv3"; 302 nvidia,function = "rsvd2"; 303 nvidia,pull = <TEGRA_PIN_PULL_UP>; 304 nvidia,tristate = <TEGRA_PIN_DISABLE>; 305 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 306 }; 307 308 /* Apalis Parallel Camera */ 309 cam-mclk-pcc0 { 310 nvidia,pins = "cam_mclk_pcc0"; 311 nvidia,function = "vi_alt3"; 312 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 313 nvidia,tristate = <TEGRA_PIN_DISABLE>; 314 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 315 }; 316 vi-vsync-pd6 { 317 nvidia,pins = "vi_d0_pt4", 318 "vi_d1_pd5", 319 "vi_d2_pl0", 320 "vi_d3_pl1", 321 "vi_d4_pl2", 322 "vi_d5_pl3", 323 "vi_d6_pl4", 324 "vi_d7_pl5", 325 "vi_d8_pl6", 326 "vi_d9_pl7", 327 "vi_d10_pt2", 328 "vi_d11_pt3", 329 "vi_hsync_pd7", 330 "vi_pclk_pt0", 331 "vi_vsync_pd6"; 332 nvidia,function = "vi"; 333 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 334 nvidia,tristate = <TEGRA_PIN_DISABLE>; 335 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 336 }; 337 /* Multiplexed and therefore disabled */ 338 kb-col2-pq2 { 339 nvidia,pins = "kb_col2_pq2", 340 "kb_col3_pq3", 341 "kb_col4_pq4", 342 "kb_row4_pr4"; 343 nvidia,function = "rsvd4"; 344 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 345 nvidia,tristate = <TEGRA_PIN_ENABLE>; 346 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 347 }; 348 kb-row0-pr0 { 349 nvidia,pins = "kb_row0_pr0", 350 "kb_row1_pr1", 351 "kb_row2_pr2", 352 "kb_row3_pr3"; 353 nvidia,function = "rsvd3"; 354 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 355 nvidia,tristate = <TEGRA_PIN_ENABLE>; 356 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 357 }; 358 kb-row5-pr5 { 359 nvidia,pins = "kb_row5_pr5", 360 "kb_row6_pr6", 361 "kb_row7_pr7"; 362 nvidia,function = "kbc"; 363 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 364 nvidia,tristate = <TEGRA_PIN_ENABLE>; 365 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 366 }; 367 /* 368 * VI level-shifter direction 369 * (pull-down => default direction input) 370 */ 371 vi-mclk-pt1 { 372 nvidia,pins = "vi_mclk_pt1"; 373 nvidia,function = "vi_alt3"; 374 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 375 nvidia,tristate = <TEGRA_PIN_ENABLE>; 376 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 377 }; 378 379 /* Apalis PWM1 */ 380 pu6 { 381 nvidia,pins = "pu6"; 382 nvidia,function = "pwm3"; 383 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 384 nvidia,tristate = <TEGRA_PIN_DISABLE>; 385 }; 386 387 /* Apalis PWM2 */ 388 pu5 { 389 nvidia,pins = "pu5"; 390 nvidia,function = "pwm2"; 391 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 392 nvidia,tristate = <TEGRA_PIN_DISABLE>; 393 }; 394 395 /* Apalis PWM3 */ 396 pu4 { 397 nvidia,pins = "pu4"; 398 nvidia,function = "pwm1"; 399 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 400 nvidia,tristate = <TEGRA_PIN_DISABLE>; 401 }; 402 403 /* Apalis PWM4 */ 404 pu3 { 405 nvidia,pins = "pu3"; 406 nvidia,function = "pwm0"; 407 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 408 nvidia,tristate = <TEGRA_PIN_DISABLE>; 409 }; 410 411 /* Apalis RESET_MOCI# */ 412 gmi-rst-n-pi4 { 413 nvidia,pins = "gmi_rst_n_pi4"; 414 nvidia,function = "gmi"; 415 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 416 nvidia,tristate = <TEGRA_PIN_DISABLE>; 417 }; 418 419 /* Apalis SATA1_ACT# */ 420 pex-l0-prsnt-n-pdd0 { 421 nvidia,pins = "pex_l0_prsnt_n_pdd0"; 422 nvidia,function = "rsvd3"; 423 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 424 nvidia,tristate = <TEGRA_PIN_DISABLE>; 425 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 426 }; 427 428 /* Apalis SD1 */ 429 sdmmc1-clk-pz0 { 430 nvidia,pins = "sdmmc1_clk_pz0"; 431 nvidia,function = "sdmmc1"; 432 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 433 nvidia,tristate = <TEGRA_PIN_DISABLE>; 434 }; 435 sdmmc1-cmd-pz1 { 436 nvidia,pins = "sdmmc1_cmd_pz1", 437 "sdmmc1_dat0_py7", 438 "sdmmc1_dat1_py6", 439 "sdmmc1_dat2_py5", 440 "sdmmc1_dat3_py4"; 441 nvidia,function = "sdmmc1"; 442 nvidia,pull = <TEGRA_PIN_PULL_UP>; 443 nvidia,tristate = <TEGRA_PIN_DISABLE>; 444 }; 445 /* Apalis SD1_CD# */ 446 clk2-req-pcc5 { 447 nvidia,pins = "clk2_req_pcc5"; 448 nvidia,function = "rsvd2"; 449 nvidia,pull = <TEGRA_PIN_PULL_UP>; 450 nvidia,tristate = <TEGRA_PIN_DISABLE>; 451 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 452 }; 453 454 /* Apalis SPDIF1 */ 455 spdif-out-pk5 { 456 nvidia,pins = "spdif_out_pk5", 457 "spdif_in_pk6"; 458 nvidia,function = "spdif"; 459 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 460 nvidia,tristate = <TEGRA_PIN_DISABLE>; 461 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 462 }; 463 464 /* Apalis SPI1 */ 465 spi1-sck-px5 { 466 nvidia,pins = "spi1_sck_px5", 467 "spi1_mosi_px4", 468 "spi1_miso_px7", 469 "spi1_cs0_n_px6"; 470 nvidia,function = "spi1"; 471 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 472 nvidia,tristate = <TEGRA_PIN_DISABLE>; 473 }; 474 475 /* Apalis SPI2 */ 476 lcd-sck-pz4 { 477 nvidia,pins = "lcd_sck_pz4", 478 "lcd_sdout_pn5", 479 "lcd_sdin_pz2", 480 "lcd_cs0_n_pn4"; 481 nvidia,function = "spi5"; 482 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 483 nvidia,tristate = <TEGRA_PIN_DISABLE>; 484 }; 485 486 /* 487 * Apalis TS (Low-speed type specific) 488 * pins may be used as GPIOs 489 */ 490 kb-col5-pq5 { 491 nvidia,pins = "kb_col5_pq5"; 492 nvidia,function = "rsvd4"; 493 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 494 nvidia,tristate = <TEGRA_PIN_DISABLE>; 495 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 496 }; 497 kb-col6-pq6 { 498 nvidia,pins = "kb_col6_pq6", 499 "kb_col7_pq7", 500 "kb_row8_ps0", 501 "kb_row9_ps1"; 502 nvidia,function = "kbc"; 503 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 504 nvidia,tristate = <TEGRA_PIN_DISABLE>; 505 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 506 }; 507 508 /* Apalis UART1 */ 509 ulpi-data0 { 510 nvidia,pins = "ulpi_data0_po1", 511 "ulpi_data1_po2", 512 "ulpi_data2_po3", 513 "ulpi_data3_po4", 514 "ulpi_data4_po5", 515 "ulpi_data5_po6", 516 "ulpi_data6_po7", 517 "ulpi_data7_po0"; 518 nvidia,function = "uarta"; 519 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 520 nvidia,tristate = <TEGRA_PIN_DISABLE>; 521 }; 522 523 /* Apalis UART2 */ 524 ulpi-clk-py0 { 525 nvidia,pins = "ulpi_clk_py0", 526 "ulpi_dir_py1", 527 "ulpi_nxt_py2", 528 "ulpi_stp_py3"; 529 nvidia,function = "uartd"; 530 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 531 nvidia,tristate = <TEGRA_PIN_DISABLE>; 532 }; 533 534 /* Apalis UART3 */ 535 uart2-rxd-pc3 { 536 nvidia,pins = "uart2_rxd_pc3", 537 "uart2_txd_pc2"; 538 nvidia,function = "uartb"; 539 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 540 nvidia,tristate = <TEGRA_PIN_DISABLE>; 541 }; 542 543 /* Apalis UART4 */ 544 uart3-rxd-pw7 { 545 nvidia,pins = "uart3_rxd_pw7", 546 "uart3_txd_pw6"; 547 nvidia,function = "uartc"; 548 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 549 nvidia,tristate = <TEGRA_PIN_DISABLE>; 550 }; 551 552 /* Apalis USBH_EN */ 553 pex-l0-rst-n-pdd1 { 554 nvidia,pins = "pex_l0_rst_n_pdd1"; 555 nvidia,function = "rsvd3"; 556 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 557 nvidia,tristate = <TEGRA_PIN_DISABLE>; 558 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 559 }; 560 561 /* Apalis USBH_OC# */ 562 pex-l0-clkreq-n-pdd2 { 563 nvidia,pins = "pex_l0_clkreq_n_pdd2"; 564 nvidia,function = "rsvd3"; 565 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 566 nvidia,tristate = <TEGRA_PIN_DISABLE>; 567 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 568 }; 569 570 /* Apalis USBO1_EN */ 571 gen2-i2c-scl-pt5 { 572 nvidia,pins = "gen2_i2c_scl_pt5"; 573 nvidia,function = "rsvd4"; 574 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 575 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 576 nvidia,tristate = <TEGRA_PIN_DISABLE>; 577 }; 578 579 /* Apalis USBO1_OC# */ 580 gen2-i2c-sda-pt6 { 581 nvidia,pins = "gen2_i2c_sda_pt6"; 582 nvidia,function = "rsvd4"; 583 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 584 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 585 nvidia,tristate = <TEGRA_PIN_DISABLE>; 586 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 587 }; 588 589 /* Apalis VGA1 not supported and therefore disabled */ 590 crt-hsync-pv6 { 591 nvidia,pins = "crt_hsync_pv6", 592 "crt_vsync_pv7"; 593 nvidia,function = "rsvd2"; 594 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 595 nvidia,tristate = <TEGRA_PIN_ENABLE>; 596 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 597 }; 598 599 /* Apalis WAKE1_MICO */ 600 pv1 { 601 nvidia,pins = "pv1"; 602 nvidia,function = "rsvd1"; 603 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 604 nvidia,tristate = <TEGRA_PIN_DISABLE>; 605 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 606 }; 607 608 /* eMMC (On-module) */ 609 sdmmc4-clk-pcc4 { 610 nvidia,pins = "sdmmc4_clk_pcc4", 611 "sdmmc4_cmd_pt7", 612 "sdmmc4_rst_n_pcc3"; 613 nvidia,function = "sdmmc4"; 614 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 615 nvidia,tristate = <TEGRA_PIN_DISABLE>; 616 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 617 }; 618 sdmmc4-dat0-paa0 { 619 nvidia,pins = "sdmmc4_dat0_paa0", 620 "sdmmc4_dat1_paa1", 621 "sdmmc4_dat2_paa2", 622 "sdmmc4_dat3_paa3", 623 "sdmmc4_dat4_paa4", 624 "sdmmc4_dat5_paa5", 625 "sdmmc4_dat6_paa6", 626 "sdmmc4_dat7_paa7"; 627 nvidia,function = "sdmmc4"; 628 nvidia,pull = <TEGRA_PIN_PULL_UP>; 629 nvidia,tristate = <TEGRA_PIN_DISABLE>; 630 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 631 }; 632 633 /* EN_+3.3_SDMMC3 */ 634 uart2-cts-n-pj5 { 635 nvidia,pins = "uart2_cts_n_pj5"; 636 nvidia,function = "gmi"; 637 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 638 nvidia,tristate = <TEGRA_PIN_DISABLE>; 639 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 640 }; 641 642 /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */ 643 pex-l2-prsnt-n-pdd7 { 644 nvidia,pins = "pex_l2_prsnt_n_pdd7", 645 "pex_l2_rst_n_pcc6"; 646 nvidia,function = "pcie"; 647 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 648 nvidia,tristate = <TEGRA_PIN_DISABLE>; 649 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 650 }; 651 /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */ 652 pex-wake-n-pdd3 { 653 nvidia,pins = "pex_wake_n_pdd3", 654 "pex_l2_clkreq_n_pcc7"; 655 nvidia,function = "pcie"; 656 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 657 nvidia,tristate = <TEGRA_PIN_DISABLE>; 658 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 659 }; 660 /* LAN i210/i211 SMB_ALERT_N (On-module) */ 661 sys-clk-req-pz5 { 662 nvidia,pins = "sys_clk_req_pz5"; 663 nvidia,function = "rsvd2"; 664 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 665 nvidia,tristate = <TEGRA_PIN_DISABLE>; 666 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 667 }; 668 669 /* LVDS Transceiver Configuration */ 670 pbb0 { 671 nvidia,pins = "pbb0", 672 "pbb7", 673 "pcc1", 674 "pcc2"; 675 nvidia,function = "rsvd2"; 676 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 677 nvidia,tristate = <TEGRA_PIN_DISABLE>; 678 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 679 }; 680 pbb3 { 681 nvidia,pins = "pbb3", 682 "pbb4", 683 "pbb5", 684 "pbb6"; 685 nvidia,function = "displayb"; 686 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 687 nvidia,tristate = <TEGRA_PIN_DISABLE>; 688 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 689 }; 690 691 /* Not connected and therefore disabled */ 692 clk-32k-out-pa0 { 693 nvidia,pins = "clk3_out_pee0", 694 "clk3_req_pee1", 695 "clk_32k_out_pa0", 696 "dap4_din_pp5", 697 "dap4_dout_pp6", 698 "dap4_fs_pp4", 699 "dap4_sclk_pp7"; 700 nvidia,function = "rsvd2"; 701 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 702 nvidia,tristate = <TEGRA_PIN_ENABLE>; 703 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 704 }; 705 dap2-fs-pa2 { 706 nvidia,pins = "dap2_fs_pa2", 707 "dap2_sclk_pa3", 708 "dap2_din_pa4", 709 "dap2_dout_pa5", 710 "lcd_dc0_pn6", 711 "lcd_m1_pw1", 712 "lcd_pwr1_pc1", 713 "pex_l1_clkreq_n_pdd6", 714 "pex_l1_prsnt_n_pdd4", 715 "pex_l1_rst_n_pdd5"; 716 nvidia,function = "rsvd3"; 717 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 718 nvidia,tristate = <TEGRA_PIN_ENABLE>; 719 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 720 }; 721 gmi-ad0-pg0 { 722 nvidia,pins = "gmi_ad0_pg0", 723 "gmi_ad2_pg2", 724 "gmi_ad3_pg3", 725 "gmi_ad4_pg4", 726 "gmi_ad5_pg5", 727 "gmi_ad6_pg6", 728 "gmi_ad7_pg7", 729 "gmi_ad8_ph0", 730 "gmi_ad9_ph1", 731 "gmi_ad10_ph2", 732 "gmi_ad11_ph3", 733 "gmi_ad12_ph4", 734 "gmi_ad13_ph5", 735 "gmi_ad14_ph6", 736 "gmi_ad15_ph7", 737 "gmi_adv_n_pk0", 738 "gmi_clk_pk1", 739 "gmi_cs4_n_pk2", 740 "gmi_cs2_n_pk3", 741 "gmi_dqs_pi2", 742 "gmi_iordy_pi5", 743 "gmi_oe_n_pi1", 744 "gmi_wait_pi7", 745 "gmi_wr_n_pi0", 746 "lcd_cs1_n_pw0", 747 "pu0", 748 "pu1", 749 "pu2"; 750 nvidia,function = "rsvd4"; 751 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 752 nvidia,tristate = <TEGRA_PIN_ENABLE>; 753 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 754 }; 755 gmi-cs0-n-pj0 { 756 nvidia,pins = "gmi_cs0_n_pj0", 757 "gmi_cs1_n_pj2", 758 "gmi_cs3_n_pk4"; 759 nvidia,function = "rsvd1"; 760 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 761 nvidia,tristate = <TEGRA_PIN_ENABLE>; 762 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 763 }; 764 gmi-cs6-n-pi3 { 765 nvidia,pins = "gmi_cs6_n_pi3"; 766 nvidia,function = "sata"; 767 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 768 nvidia,tristate = <TEGRA_PIN_ENABLE>; 769 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 770 }; 771 gmi-cs7-n-pi6 { 772 nvidia,pins = "gmi_cs7_n_pi6"; 773 nvidia,function = "gmi_alt"; 774 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 775 nvidia,tristate = <TEGRA_PIN_ENABLE>; 776 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 777 }; 778 lcd-pwr0-pb2 { 779 nvidia,pins = "lcd_pwr0_pb2", 780 "lcd_pwr2_pc6", 781 "lcd_wr_n_pz3"; 782 nvidia,function = "hdcp"; 783 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 784 nvidia,tristate = <TEGRA_PIN_ENABLE>; 785 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 786 }; 787 uart2-rts-n-pj6 { 788 nvidia,pins = "uart2_rts_n_pj6"; 789 nvidia,function = "gmi"; 790 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 791 nvidia,tristate = <TEGRA_PIN_ENABLE>; 792 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 793 }; 794 795 /* Power I2C (On-module) */ 796 pwr-i2c-scl-pz6 { 797 nvidia,pins = "pwr_i2c_scl_pz6", 798 "pwr_i2c_sda_pz7"; 799 nvidia,function = "i2cpwr"; 800 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 801 nvidia,tristate = <TEGRA_PIN_DISABLE>; 802 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 803 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 804 }; 805 806 /* 807 * THERMD_ALERT#, unlatched I2C address pin of LM95245 808 * temperature sensor therefore requires disabling for 809 * now 810 */ 811 lcd-dc1-pd2 { 812 nvidia,pins = "lcd_dc1_pd2"; 813 nvidia,function = "rsvd3"; 814 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 815 nvidia,tristate = <TEGRA_PIN_ENABLE>; 816 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 817 }; 818 819 /* TOUCH_PEN_INT# (On-module) */ 820 pv0 { 821 nvidia,pins = "pv0"; 822 nvidia,function = "rsvd1"; 823 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 824 nvidia,tristate = <TEGRA_PIN_DISABLE>; 825 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 826 }; 827 }; 828 }; 829 830 serial@70006040 { 831 compatible = "nvidia,tegra30-hsuart"; 832 /delete-property/ reg-shift; 833 }; 834 835 serial@70006200 { 836 compatible = "nvidia,tegra30-hsuart"; 837 /delete-property/ reg-shift; 838 }; 839 840 serial@70006300 { 841 compatible = "nvidia,tegra30-hsuart"; 842 /delete-property/ reg-shift; 843 }; 844 845 hdmi_ddc: i2c@7000c700 { 846 clock-frequency = <10000>; 847 }; 848 849 /* 850 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 851 * touch screen controller 852 */ 853 i2c@7000d000 { 854 status = "okay"; 855 clock-frequency = <100000>; 856 857 /* SGTL5000 audio codec */ 858 sgtl5000: codec@a { 859 compatible = "fsl,sgtl5000"; 860 reg = <0x0a>; 861 #sound-dai-cells = <0>; 862 VDDA-supply = <®_module_3v3_audio>; 863 VDDD-supply = <®_1v8_vio>; 864 VDDIO-supply = <®_module_3v3>; 865 clocks = <&tegra_car TEGRA30_CLK_EXTERN1>; 866 }; 867 868 pmic: pmic@2d { 869 compatible = "ti,tps65911"; 870 reg = <0x2d>; 871 872 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 873 #interrupt-cells = <2>; 874 interrupt-controller; 875 876 ti,system-power-controller; 877 878 #gpio-cells = <2>; 879 gpio-controller; 880 881 vcc1-supply = <®_module_3v3>; 882 vcc2-supply = <®_module_3v3>; 883 vcc3-supply = <®_1v8_vio>; 884 vcc4-supply = <®_module_3v3>; 885 vcc5-supply = <®_module_3v3>; 886 vcc6-supply = <®_1v8_vio>; 887 vcc7-supply = <®_5v0_charge_pump>; 888 vccio-supply = <®_module_3v3>; 889 890 regulators { 891 vdd1_reg: vdd1 { 892 regulator-name = "+V1.35_VDDIO_DDR"; 893 regulator-min-microvolt = <1350000>; 894 regulator-max-microvolt = <1350000>; 895 regulator-always-on; 896 }; 897 898 vdd2_reg: vdd2 { 899 regulator-name = "+V1.05"; 900 regulator-min-microvolt = <1050000>; 901 regulator-max-microvolt = <1050000>; 902 }; 903 904 vddctrl_reg: vddctrl { 905 regulator-name = "+V1.0_VDD_CPU"; 906 regulator-min-microvolt = <1150000>; 907 regulator-max-microvolt = <1150000>; 908 regulator-always-on; 909 }; 910 911 reg_1v8_vio: vio { 912 regulator-name = "+V1.8"; 913 regulator-min-microvolt = <1800000>; 914 regulator-max-microvolt = <1800000>; 915 regulator-always-on; 916 }; 917 918 /* 919 * 1.8 volt +VDDIO_SDMMC3 in case EN_+3.3_SDMMC3 920 * is off 921 */ 922 vddio_sdmmc_1v8_reg: ldo1 { 923 regulator-name = "+VDDIO_SDMMC3_1V8"; 924 regulator-min-microvolt = <1800000>; 925 regulator-max-microvolt = <1800000>; 926 regulator-always-on; 927 }; 928 929 /* 930 * EN_+V3.3 switching via FET: 931 * +V3.3_AUDIO_AVDD_S, +V3.3 932 * see also +V3.3 fixed supply 933 */ 934 ldo2_reg: ldo2 { 935 regulator-name = "EN_+V3.3"; 936 regulator-min-microvolt = <3300000>; 937 regulator-max-microvolt = <3300000>; 938 regulator-always-on; 939 }; 940 941 ldo3_reg: ldo3 { 942 regulator-name = "+V1.2_CSI"; 943 regulator-min-microvolt = <1200000>; 944 regulator-max-microvolt = <1200000>; 945 }; 946 947 ldo4_reg: ldo4 { 948 regulator-name = "+V1.2_VDD_RTC"; 949 regulator-min-microvolt = <1200000>; 950 regulator-max-microvolt = <1200000>; 951 regulator-always-on; 952 }; 953 954 /* 955 * +V2.8_AVDD_VDAC: 956 * only required for (unsupported) analog RGB 957 */ 958 ldo5_reg: ldo5 { 959 regulator-name = "+V2.8_AVDD_VDAC"; 960 regulator-min-microvolt = <2800000>; 961 regulator-max-microvolt = <2800000>; 962 regulator-always-on; 963 }; 964 965 /* 966 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V 967 * but LDO6 can't set voltage in 50mV 968 * granularity 969 */ 970 ldo6_reg: ldo6 { 971 regulator-name = "+V1.05_AVDD_PLLE"; 972 regulator-min-microvolt = <1100000>; 973 regulator-max-microvolt = <1100000>; 974 }; 975 976 ldo7_reg: ldo7 { 977 regulator-name = "+V1.2_AVDD_PLL"; 978 regulator-min-microvolt = <1200000>; 979 regulator-max-microvolt = <1200000>; 980 regulator-always-on; 981 }; 982 983 ldo8_reg: ldo8 { 984 regulator-name = "+V1.0_VDD_DDR_HS"; 985 regulator-min-microvolt = <1000000>; 986 regulator-max-microvolt = <1000000>; 987 regulator-always-on; 988 }; 989 }; 990 }; 991 992 /* STMPE811 touch screen controller */ 993 touchscreen@41 { 994 compatible = "st,stmpe811"; 995 reg = <0x41>; 996 irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>; 997 interrupt-controller; 998 id = <0>; 999 blocks = <0x5>; 1000 irq-trigger = <0x1>; 1001 /* 3.25 MHz ADC clock speed */ 1002 st,adc-freq = <1>; 1003 /* 12-bit ADC */ 1004 st,mod-12b = <1>; 1005 /* internal ADC reference */ 1006 st,ref-sel = <0>; 1007 /* ADC converstion time: 80 clocks */ 1008 st,sample-time = <4>; 1009 1010 stmpe_touchscreen { 1011 compatible = "st,stmpe-ts"; 1012 /* 8 sample average control */ 1013 st,ave-ctrl = <3>; 1014 /* 7 length fractional part in z */ 1015 st,fraction-z = <7>; 1016 /* 1017 * 50 mA typical 80 mA max touchscreen drivers 1018 * current limit value 1019 */ 1020 st,i-drive = <1>; 1021 /* 1 ms panel driver settling time */ 1022 st,settling = <3>; 1023 /* 5 ms touch detect interrupt delay */ 1024 st,touch-det-delay = <5>; 1025 }; 1026 1027 stmpe_adc { 1028 compatible = "st,stmpe-adc"; 1029 /* forbid to use ADC channels 3-0 (touch) */ 1030 st,norequest-mask = <0x0F>; 1031 }; 1032 }; 1033 1034 /* 1035 * LM95245 temperature sensor 1036 * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN 1037 */ 1038 temp-sensor@4c { 1039 compatible = "national,lm95245"; 1040 reg = <0x4c>; 1041 }; 1042 1043 /* SW: +V1.2_VDD_CORE */ 1044 regulator@60 { 1045 compatible = "ti,tps62362"; 1046 reg = <0x60>; 1047 1048 regulator-name = "tps62362-vout"; 1049 regulator-min-microvolt = <900000>; 1050 regulator-max-microvolt = <1400000>; 1051 regulator-boot-on; 1052 regulator-always-on; 1053 }; 1054 }; 1055 1056 /* SPI4: CAN2 */ 1057 spi@7000da00 { 1058 status = "okay"; 1059 spi-max-frequency = <10000000>; 1060 1061 can@1 { 1062 compatible = "microchip,mcp2515"; 1063 reg = <1>; 1064 clocks = <&clk16m>; 1065 interrupt-parent = <&gpio>; 1066 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>; 1067 spi-max-frequency = <10000000>; 1068 }; 1069 }; 1070 1071 /* SPI6: CAN1 */ 1072 spi@7000de00 { 1073 status = "okay"; 1074 spi-max-frequency = <10000000>; 1075 1076 can@0 { 1077 compatible = "microchip,mcp2515"; 1078 reg = <0>; 1079 clocks = <&clk16m>; 1080 interrupt-parent = <&gpio>; 1081 interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_FALLING>; 1082 spi-max-frequency = <10000000>; 1083 }; 1084 }; 1085 1086 pmc@7000e400 { 1087 nvidia,invert-interrupt; 1088 nvidia,suspend-mode = <1>; 1089 nvidia,cpu-pwr-good-time = <5000>; 1090 nvidia,cpu-pwr-off-time = <5000>; 1091 nvidia,core-pwr-good-time = <3845 3845>; 1092 nvidia,core-pwr-off-time = <0>; 1093 nvidia,core-power-req-active-high; 1094 nvidia,sys-clock-req-active-high; 1095 1096 /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ 1097 i2c-thermtrip { 1098 nvidia,i2c-controller-id = <4>; 1099 nvidia,bus-addr = <0x2d>; 1100 nvidia,reg-addr = <0x3f>; 1101 nvidia,reg-data = <0x1>; 1102 }; 1103 }; 1104 1105 hda@70030000 { 1106 status = "okay"; 1107 }; 1108 1109 ahub@70080000 { 1110 i2s@70080500 { 1111 status = "okay"; 1112 }; 1113 }; 1114 1115 /* eMMC */ 1116 mmc@78000600 { 1117 status = "okay"; 1118 bus-width = <8>; 1119 non-removable; 1120 vmmc-supply = <®_module_3v3>; /* VCC */ 1121 vqmmc-supply = <®_1v8_vio>; /* VCCQ */ 1122 mmc-ddr-1_8v; 1123 }; 1124 1125 clk32k_in: xtal1 { 1126 compatible = "fixed-clock"; 1127 #clock-cells = <0>; 1128 clock-frequency = <32768>; 1129 }; 1130 1131 clk16m: osc4 { 1132 compatible = "fixed-clock"; 1133 #clock-cells = <0>; 1134 clock-frequency = <16000000>; 1135 }; 1136 1137 reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { 1138 compatible = "regulator-fixed"; 1139 regulator-name = "+V1.8_AVDD_HDMI_PLL"; 1140 regulator-min-microvolt = <1800000>; 1141 regulator-max-microvolt = <1800000>; 1142 enable-active-high; 1143 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; 1144 vin-supply = <®_1v8_vio>; 1145 }; 1146 1147 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { 1148 compatible = "regulator-fixed"; 1149 regulator-name = "+V3.3_AVDD_HDMI"; 1150 regulator-min-microvolt = <3300000>; 1151 regulator-max-microvolt = <3300000>; 1152 enable-active-high; 1153 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; 1154 vin-supply = <®_module_3v3>; 1155 }; 1156 1157 reg_5v0_charge_pump: regulator-5v0-charge-pump { 1158 compatible = "regulator-fixed"; 1159 regulator-name = "+V5.0"; 1160 regulator-min-microvolt = <5000000>; 1161 regulator-max-microvolt = <5000000>; 1162 regulator-always-on; 1163 }; 1164 1165 reg_module_3v3: regulator-module-3v3 { 1166 compatible = "regulator-fixed"; 1167 regulator-name = "+V3.3"; 1168 regulator-min-microvolt = <3300000>; 1169 regulator-max-microvolt = <3300000>; 1170 regulator-always-on; 1171 }; 1172 1173 reg_module_3v3_audio: regulator-module-3v3-audio { 1174 compatible = "regulator-fixed"; 1175 regulator-name = "+V3.3_AUDIO_AVDD_S"; 1176 regulator-min-microvolt = <3300000>; 1177 regulator-max-microvolt = <3300000>; 1178 regulator-always-on; 1179 }; 1180 1181 sound { 1182 compatible = "toradex,tegra-audio-sgtl5000-apalis_t30", 1183 "nvidia,tegra-audio-sgtl5000"; 1184 nvidia,model = "Toradex Apalis T30"; 1185 nvidia,audio-routing = 1186 "Headphone Jack", "HP_OUT", 1187 "LINE_IN", "Line In Jack", 1188 "MIC_IN", "Mic Jack"; 1189 nvidia,i2s-controller = <&tegra_i2s2>; 1190 nvidia,audio-codec = <&sgtl5000>; 1191 clocks = <&tegra_car TEGRA30_CLK_PLL_A>, 1192 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1193 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1194 clock-names = "pll_a", "pll_a_out0", "mclk"; 1195 1196 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, 1197 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1198 1199 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1200 <&tegra_car TEGRA30_CLK_EXTERN1>; 1201 }; 1202 };
Cache object: 19d01081283a99505e6e7a02a7e79ff5
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