Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/tegra30-asus-nexus7-grouper-common.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <dt-bindings/input/gpio-keys.h> 4 #include <dt-bindings/input/input.h> 5 #include <dt-bindings/power/summit,smb347-charger.h> 6 #include <dt-bindings/thermal/thermal.h> 7 8 #include "tegra30.dtsi" 9 #include "tegra30-cpu-opp.dtsi" 10 #include "tegra30-cpu-opp-microvolt.dtsi" 11 #include "tegra30-asus-lvds-display.dtsi" 12 13 / { 14 aliases { 15 mmc0 = &sdmmc4; /* eMMC */ 16 mmc1 = &sdmmc3; /* WiFi */ 17 18 rtc0 = &pmic; 19 rtc1 = "/rtc@7000e000"; 20 21 serial1 = &uartc; /* Bluetooth */ 22 serial2 = &uartb; /* GPS */ 23 }; 24 25 /* 26 * The decompressor and also some bootloaders rely on a 27 * pre-existing /chosen node to be available to insert the 28 * command line and merge other ATAGS info. 29 */ 30 chosen {}; 31 32 memory@80000000 { 33 reg = <0x80000000 0x40000000>; 34 }; 35 36 reserved-memory { 37 #address-cells = <1>; 38 #size-cells = <1>; 39 ranges; 40 41 linux,cma@80000000 { 42 compatible = "shared-dma-pool"; 43 alloc-ranges = <0x80000000 0x30000000>; 44 size = <0x10000000>; /* 256MiB */ 45 linux,cma-default; 46 reusable; 47 }; 48 49 ramoops@bfdf0000 { 50 compatible = "ramoops"; 51 reg = <0xbfdf0000 0x10000>; /* 64kB */ 52 console-size = <0x8000>; /* 32kB */ 53 record-size = <0x400>; /* 1kB */ 54 ecc-size = <16>; 55 }; 56 57 trustzone@bfe00000 { 58 reg = <0xbfe00000 0x200000>; 59 no-map; 60 }; 61 }; 62 63 gpio@6000d000 { 64 init-mode-hog { 65 gpio-hog; 66 gpios = <TEGRA_GPIO(DD, 7) GPIO_ACTIVE_HIGH>, 67 <TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>, 68 <TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 69 output-low; 70 }; 71 72 init-low-power-mode-hog { 73 gpio-hog; 74 gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 75 input; 76 }; 77 }; 78 79 pinmux@70000868 { 80 pinctrl-names = "default"; 81 pinctrl-0 = <&state_default>; 82 83 state_default: pinmux { 84 clk_32k_out_pa0 { 85 nvidia,pins = "clk_32k_out_pa0"; 86 nvidia,function = "blink"; 87 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 88 nvidia,tristate = <TEGRA_PIN_DISABLE>; 89 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 90 }; 91 uart3_cts_n_pa1 { 92 nvidia,pins = "uart3_cts_n_pa1", 93 "uart3_rxd_pw7"; 94 nvidia,function = "uartc"; 95 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 96 nvidia,tristate = <TEGRA_PIN_DISABLE>; 97 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 98 }; 99 dap2_fs_pa2 { 100 nvidia,pins = "dap2_fs_pa2", 101 "dap2_sclk_pa3", 102 "dap2_din_pa4", 103 "dap2_dout_pa5"; 104 nvidia,function = "i2s1"; 105 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 106 nvidia,tristate = <TEGRA_PIN_DISABLE>; 107 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 108 }; 109 sdmmc3_clk_pa6 { 110 nvidia,pins = "sdmmc3_clk_pa6"; 111 nvidia,function = "sdmmc3"; 112 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 113 nvidia,tristate = <TEGRA_PIN_DISABLE>; 114 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 115 }; 116 sdmmc3_cmd_pa7 { 117 nvidia,pins = "sdmmc3_cmd_pa7", 118 "sdmmc3_dat3_pb4", 119 "sdmmc3_dat2_pb5", 120 "sdmmc3_dat1_pb6", 121 "sdmmc3_dat0_pb7", 122 "sdmmc3_dat4_pd1", 123 "sdmmc3_dat6_pd3", 124 "sdmmc3_dat7_pd4"; 125 nvidia,function = "sdmmc3"; 126 nvidia,pull = <TEGRA_PIN_PULL_UP>; 127 nvidia,tristate = <TEGRA_PIN_DISABLE>; 128 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 129 }; 130 gmi_a17_pb0 { 131 nvidia,pins = "gmi_a17_pb0", 132 "gmi_a18_pb1"; 133 nvidia,function = "uartd"; 134 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 135 nvidia,tristate = <TEGRA_PIN_DISABLE>; 136 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 137 }; 138 lcd_pwr0_pb2 { 139 nvidia,pins = "lcd_pwr0_pb2", 140 "lcd_pwr1_pc1", 141 "lcd_m1_pw1"; 142 nvidia,function = "displaya"; 143 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 144 nvidia,tristate = <TEGRA_PIN_DISABLE>; 145 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 146 }; 147 lcd_pclk_pb3 { 148 nvidia,pins = "lcd_pclk_pb3", 149 "lcd_d0_pe0", 150 "lcd_d1_pe1", 151 "lcd_d2_pe2", 152 "lcd_d3_pe3", 153 "lcd_d4_pe4", 154 "lcd_d5_pe5", 155 "lcd_d6_pe6", 156 "lcd_d7_pe7", 157 "lcd_d8_pf0", 158 "lcd_d9_pf1", 159 "lcd_d10_pf2", 160 "lcd_d11_pf3", 161 "lcd_d12_pf4", 162 "lcd_d13_pf5", 163 "lcd_d14_pf6", 164 "lcd_d15_pf7", 165 "lcd_de_pj1", 166 "lcd_hsync_pj3", 167 "lcd_vsync_pj4", 168 "lcd_d16_pm0", 169 "lcd_d17_pm1", 170 "lcd_d18_pm2", 171 "lcd_d19_pm3", 172 "lcd_d20_pm4", 173 "lcd_d21_pm5", 174 "lcd_d22_pm6", 175 "lcd_d23_pm7", 176 "lcd_cs0_n_pn4", 177 "lcd_sdout_pn5", 178 "lcd_dc0_pn6", 179 "lcd_cs1_n_pw0", 180 "lcd_sdin_pz2", 181 "lcd_sck_pz4"; 182 nvidia,function = "displaya"; 183 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 184 nvidia,tristate = <TEGRA_PIN_DISABLE>; 185 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 186 }; 187 uart3_rts_n_pc0 { 188 nvidia,pins = "uart3_rts_n_pc0", 189 "uart3_txd_pw6"; 190 nvidia,function = "uartc"; 191 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 192 nvidia,tristate = <TEGRA_PIN_DISABLE>; 193 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 194 }; 195 uart2_txd_pc2 { 196 nvidia,pins = "uart2_txd_pc2", 197 "uart2_rts_n_pj6"; 198 nvidia,function = "uartb"; 199 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 200 nvidia,tristate = <TEGRA_PIN_DISABLE>; 201 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 202 }; 203 uart2_rxd_pc3 { 204 nvidia,pins = "uart2_rxd_pc3", 205 "uart2_cts_n_pj5"; 206 nvidia,function = "uartb"; 207 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 208 nvidia,tristate = <TEGRA_PIN_DISABLE>; 209 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 210 }; 211 gen1_i2c_scl_pc4 { 212 nvidia,pins = "gen1_i2c_scl_pc4", 213 "gen1_i2c_sda_pc5"; 214 nvidia,function = "i2c1"; 215 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 216 nvidia,tristate = <TEGRA_PIN_DISABLE>; 217 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 218 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 219 }; 220 gmi_wp_n_pc7 { 221 nvidia,pins = "gmi_wp_n_pc7", 222 "gmi_wait_pi7", 223 "gmi_cs4_n_pk2", 224 "gmi_cs3_n_pk4"; 225 nvidia,function = "rsvd1"; 226 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 227 nvidia,tristate = <TEGRA_PIN_ENABLE>; 228 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 229 }; 230 gmi_ad12_ph4 { 231 nvidia,pins = "gmi_ad12_ph4", 232 "gmi_cs0_n_pj0", 233 "gmi_cs1_n_pj2", 234 "gmi_cs2_n_pk3"; 235 nvidia,function = "rsvd1"; 236 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 237 nvidia,tristate = <TEGRA_PIN_ENABLE>; 238 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 239 }; 240 sdmmc3_dat5_pd0 { 241 nvidia,pins = "sdmmc3_dat5_pd0"; 242 nvidia,function = "sdmmc3"; 243 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 244 nvidia,tristate = <TEGRA_PIN_DISABLE>; 245 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 246 }; 247 gmi_ad0_pg0 { 248 nvidia,pins = "gmi_ad0_pg0", 249 "gmi_ad1_pg1", 250 "gmi_ad14_ph6", 251 "pu1"; 252 nvidia,function = "rsvd1"; 253 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 254 nvidia,tristate = <TEGRA_PIN_DISABLE>; 255 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 256 }; 257 gmi_ad2_pg2 { 258 nvidia,pins = "gmi_ad2_pg2", 259 "gmi_ad3_pg3", 260 "gmi_ad6_pg6", 261 "gmi_ad7_pg7"; 262 nvidia,function = "rsvd1"; 263 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 264 nvidia,tristate = <TEGRA_PIN_DISABLE>; 265 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 266 }; 267 gmi_ad4_pg4 { 268 nvidia,pins = "gmi_ad4_pg4", 269 "gmi_ad5_pg5"; 270 nvidia,function = "nand"; 271 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 272 nvidia,tristate = <TEGRA_PIN_DISABLE>; 273 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 274 }; 275 gmi_ad8_ph0 { 276 nvidia,pins = "gmi_ad8_ph0"; 277 nvidia,function = "pwm0"; 278 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 279 nvidia,tristate = <TEGRA_PIN_DISABLE>; 280 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 281 }; 282 gmi_ad9_ph1 { 283 nvidia,pins = "gmi_ad9_ph1"; 284 nvidia,function = "rsvd4"; 285 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 286 nvidia,tristate = <TEGRA_PIN_DISABLE>; 287 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 288 }; 289 gmi_ad10_ph2 { 290 nvidia,pins = "gmi_ad10_ph2"; 291 nvidia,function = "pwm2"; 292 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 293 nvidia,tristate = <TEGRA_PIN_ENABLE>; 294 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 295 }; 296 gmi_ad11_ph3 { 297 nvidia,pins = "gmi_ad11_ph3"; 298 nvidia,function = "pwm3"; 299 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 300 nvidia,tristate = <TEGRA_PIN_DISABLE>; 301 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 302 }; 303 gmi_ad13_ph5 { 304 nvidia,pins = "gmi_ad13_ph5", 305 "gmi_wr_n_pi0", 306 "gmi_oe_n_pi1", 307 "gmi_adv_n_pk0"; 308 nvidia,function = "rsvd1"; 309 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 310 nvidia,tristate = <TEGRA_PIN_ENABLE>; 311 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 312 }; 313 gmi_ad15_ph7 { 314 nvidia,pins = "gmi_ad15_ph7"; 315 nvidia,function = "rsvd1"; 316 nvidia,pull = <TEGRA_PIN_PULL_UP>; 317 nvidia,tristate = <TEGRA_PIN_DISABLE>; 318 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 319 }; 320 gmi_dqs_pi2 { 321 nvidia,pins = "gmi_dqs_pi2", 322 "pu2", 323 "pv1"; 324 nvidia,function = "rsvd1"; 325 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 326 nvidia,tristate = <TEGRA_PIN_DISABLE>; 327 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 328 }; 329 gmi_rst_n_pi4 { 330 nvidia,pins = "gmi_rst_n_pi4"; 331 nvidia,function = "nand"; 332 nvidia,pull = <TEGRA_PIN_PULL_UP>; 333 nvidia,tristate = <TEGRA_PIN_DISABLE>; 334 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 335 }; 336 gmi_iordy_pi5 { 337 nvidia,pins = "gmi_iordy_pi5"; 338 nvidia,function = "rsvd1"; 339 nvidia,pull = <TEGRA_PIN_PULL_UP>; 340 nvidia,tristate = <TEGRA_PIN_DISABLE>; 341 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 342 }; 343 gmi_cs7_n_pi6 { 344 nvidia,pins = "gmi_cs7_n_pi6", 345 "gmi_clk_pk1"; 346 nvidia,function = "nand"; 347 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 348 nvidia,tristate = <TEGRA_PIN_ENABLE>; 349 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 350 }; 351 gmi_a16_pj7 { 352 nvidia,pins = "gmi_a16_pj7", 353 "gmi_a19_pk7"; 354 nvidia,function = "uartd"; 355 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 356 nvidia,tristate = <TEGRA_PIN_DISABLE>; 357 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 358 }; 359 spdif_out_pk5 { 360 nvidia,pins = "spdif_out_pk5"; 361 nvidia,function = "spdif"; 362 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 363 nvidia,tristate = <TEGRA_PIN_DISABLE>; 364 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 365 }; 366 spdif_in_pk6 { 367 nvidia,pins = "spdif_in_pk6"; 368 nvidia,function = "spdif"; 369 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 370 nvidia,tristate = <TEGRA_PIN_DISABLE>; 371 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 372 }; 373 dap1_fs_pn0 { 374 nvidia,pins = "dap1_fs_pn0", 375 "dap1_din_pn1", 376 "dap1_dout_pn2", 377 "dap1_sclk_pn3"; 378 nvidia,function = "i2s0"; 379 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 380 nvidia,tristate = <TEGRA_PIN_DISABLE>; 381 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 382 }; 383 hdmi_int_pn7 { 384 nvidia,pins = "hdmi_int_pn7"; 385 nvidia,function = "hdmi"; 386 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 387 nvidia,tristate = <TEGRA_PIN_ENABLE>; 388 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 389 }; 390 ulpi_data7_po0 { 391 nvidia,pins = "ulpi_data7_po0"; 392 nvidia,function = "uarta"; 393 nvidia,pull = <TEGRA_PIN_PULL_UP>; 394 nvidia,tristate = <TEGRA_PIN_ENABLE>; 395 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 396 }; 397 ulpi_data3_po4 { 398 nvidia,pins = "ulpi_data3_po4"; 399 nvidia,function = "ulpi"; 400 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 401 nvidia,tristate = <TEGRA_PIN_DISABLE>; 402 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 403 }; 404 dap3_fs_pp0 { 405 nvidia,pins = "dap3_fs_pp0"; 406 nvidia,function = "i2s2"; 407 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 408 nvidia,tristate = <TEGRA_PIN_DISABLE>; 409 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 410 }; 411 dap4_fs_pp4 { 412 nvidia,pins = "dap4_fs_pp4", 413 "dap4_din_pp5", 414 "dap4_dout_pp6", 415 "dap4_sclk_pp7"; 416 nvidia,function = "i2s3"; 417 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 418 nvidia,tristate = <TEGRA_PIN_DISABLE>; 419 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 420 }; 421 kb_col0_pq0 { 422 nvidia,pins = "kb_col0_pq0", 423 "kb_col1_pq1", 424 "kb_row1_pr1"; 425 nvidia,function = "kbc"; 426 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 427 nvidia,tristate = <TEGRA_PIN_ENABLE>; 428 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 429 }; 430 kb_col2_pq2 { 431 nvidia,pins = "kb_col2_pq2", 432 "kb_col3_pq3"; 433 nvidia,function = "rsvd4"; 434 nvidia,pull = <TEGRA_PIN_PULL_UP>; 435 nvidia,tristate = <TEGRA_PIN_ENABLE>; 436 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 437 }; 438 kb_col4_pq4 { 439 nvidia,pins = "kb_col4_pq4", 440 "kb_col5_pq5", 441 "kb_col7_pq7", 442 "kb_row2_pr2", 443 "kb_row4_pr4", 444 "kb_row5_pr5", 445 "kb_row14_ps6"; 446 nvidia,function = "kbc"; 447 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 448 nvidia,tristate = <TEGRA_PIN_ENABLE>; 449 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 450 }; 451 kb_row0_pr0 { 452 nvidia,pins = "kb_row0_pr0"; 453 nvidia,function = "rsvd4"; 454 nvidia,pull = <TEGRA_PIN_PULL_UP>; 455 nvidia,tristate = <TEGRA_PIN_DISABLE>; 456 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 457 }; 458 kb_row6_pr6 { 459 nvidia,pins = "kb_row6_pr6", 460 "kb_row8_ps0", 461 "kb_row9_ps1", 462 "kb_row10_ps2"; 463 nvidia,function = "kbc"; 464 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 465 nvidia,tristate = <TEGRA_PIN_DISABLE>; 466 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 467 }; 468 kb_row11_ps3 { 469 nvidia,pins = "kb_row11_ps3", 470 "kb_row12_ps4"; 471 nvidia,function = "kbc"; 472 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 473 nvidia,tristate = <TEGRA_PIN_DISABLE>; 474 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 475 }; 476 gen2_i2c_scl_pt5 { 477 nvidia,pins = "gen2_i2c_scl_pt5", 478 "gen2_i2c_sda_pt6"; 479 nvidia,function = "i2c2"; 480 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 481 nvidia,tristate = <TEGRA_PIN_DISABLE>; 482 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 483 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 484 }; 485 sdmmc4_cmd_pt7 { 486 nvidia,pins = "sdmmc4_cmd_pt7", 487 "sdmmc4_dat0_paa0", 488 "sdmmc4_dat1_paa1", 489 "sdmmc4_dat2_paa2", 490 "sdmmc4_dat3_paa3", 491 "sdmmc4_dat4_paa4", 492 "sdmmc4_dat5_paa5", 493 "sdmmc4_dat6_paa6", 494 "sdmmc4_dat7_paa7"; 495 nvidia,function = "sdmmc4"; 496 nvidia,pull = <TEGRA_PIN_PULL_UP>; 497 nvidia,tristate = <TEGRA_PIN_DISABLE>; 498 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 499 }; 500 pu0 { 501 nvidia,pins = "pu0", 502 "pu6"; 503 nvidia,function = "rsvd4"; 504 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 505 nvidia,tristate = <TEGRA_PIN_DISABLE>; 506 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 507 }; 508 jtag_rtck_pu7 { 509 nvidia,pins = "jtag_rtck_pu7"; 510 nvidia,function = "rtck"; 511 nvidia,pull = <TEGRA_PIN_PULL_UP>; 512 nvidia,tristate = <TEGRA_PIN_DISABLE>; 513 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 514 }; 515 pv0 { 516 nvidia,pins = "pv0"; 517 nvidia,function = "rsvd1"; 518 nvidia,pull = <TEGRA_PIN_PULL_UP>; 519 nvidia,tristate = <TEGRA_PIN_ENABLE>; 520 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 521 }; 522 ddc_scl_pv4 { 523 nvidia,pins = "ddc_scl_pv4", 524 "ddc_sda_pv5"; 525 nvidia,function = "i2c4"; 526 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 527 nvidia,tristate = <TEGRA_PIN_DISABLE>; 528 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 529 }; 530 crt_hsync_pv6 { 531 nvidia,pins = "crt_hsync_pv6", 532 "crt_vsync_pv7"; 533 nvidia,function = "crt"; 534 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 535 nvidia,tristate = <TEGRA_PIN_DISABLE>; 536 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 537 }; 538 spi2_cs1_n_pw2 { 539 nvidia,pins = "spi2_cs1_n_pw2", 540 "spi2_miso_px1", 541 "spi2_sck_px2"; 542 nvidia,function = "spi2"; 543 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 544 nvidia,tristate = <TEGRA_PIN_DISABLE>; 545 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 546 }; 547 clk1_out_pw4 { 548 nvidia,pins = "clk1_out_pw4"; 549 nvidia,function = "extperiph1"; 550 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 551 nvidia,tristate = <TEGRA_PIN_DISABLE>; 552 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 553 }; 554 clk2_out_pw5 { 555 nvidia,pins = "clk2_out_pw5"; 556 nvidia,function = "extperiph2"; 557 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 558 nvidia,tristate = <TEGRA_PIN_DISABLE>; 559 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 560 }; 561 spi2_cs0_n_px3 { 562 nvidia,pins = "spi2_cs0_n_px3"; 563 nvidia,function = "spi6"; 564 nvidia,pull = <TEGRA_PIN_PULL_UP>; 565 nvidia,tristate = <TEGRA_PIN_DISABLE>; 566 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 567 }; 568 spi1_mosi_px4 { 569 nvidia,pins = "spi1_mosi_px4", 570 "spi1_cs0_n_px6"; 571 nvidia,function = "spi1"; 572 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 573 nvidia,tristate = <TEGRA_PIN_DISABLE>; 574 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 575 }; 576 ulpi_clk_py0 { 577 nvidia,pins = "ulpi_clk_py0", 578 "ulpi_dir_py1"; 579 nvidia,function = "ulpi"; 580 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 581 nvidia,tristate = <TEGRA_PIN_ENABLE>; 582 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 583 }; 584 sdmmc1_dat3_py4 { 585 nvidia,pins = "sdmmc1_dat3_py4", 586 "sdmmc1_dat2_py5", 587 "sdmmc1_dat1_py6", 588 "sdmmc1_dat0_py7", 589 "sdmmc1_cmd_pz1"; 590 nvidia,function = "sdmmc1"; 591 nvidia,pull = <TEGRA_PIN_PULL_UP>; 592 nvidia,tristate = <TEGRA_PIN_DISABLE>; 593 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 594 }; 595 sdmmc1_clk_pz0 { 596 nvidia,pins = "sdmmc1_clk_pz0"; 597 nvidia,function = "sdmmc1"; 598 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 599 nvidia,tristate = <TEGRA_PIN_DISABLE>; 600 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 601 }; 602 lcd_wr_n_pz3 { 603 nvidia,pins = "lcd_wr_n_pz3"; 604 nvidia,function = "displaya"; 605 nvidia,pull = <TEGRA_PIN_PULL_UP>; 606 nvidia,tristate = <TEGRA_PIN_DISABLE>; 607 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 608 }; 609 sys_clk_req_pz5 { 610 nvidia,pins = "sys_clk_req_pz5"; 611 nvidia,function = "sysclk"; 612 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 613 nvidia,tristate = <TEGRA_PIN_DISABLE>; 614 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 615 }; 616 pwr_i2c_scl_pz6 { 617 nvidia,pins = "pwr_i2c_scl_pz6", 618 "pwr_i2c_sda_pz7"; 619 nvidia,function = "i2cpwr"; 620 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 621 nvidia,tristate = <TEGRA_PIN_DISABLE>; 622 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 623 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 624 }; 625 pbb0 { 626 nvidia,pins = "pbb0", 627 "pcc1"; 628 nvidia,function = "rsvd2"; 629 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 630 nvidia,tristate = <TEGRA_PIN_DISABLE>; 631 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 632 }; 633 cam_i2c_scl_pbb1 { 634 nvidia,pins = "cam_i2c_scl_pbb1", 635 "cam_i2c_sda_pbb2"; 636 nvidia,function = "i2c3"; 637 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 638 nvidia,tristate = <TEGRA_PIN_DISABLE>; 639 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 640 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 641 }; 642 pbb3 { 643 nvidia,pins = "pbb3"; 644 nvidia,function = "vgp3"; 645 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 646 nvidia,tristate = <TEGRA_PIN_DISABLE>; 647 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 648 }; 649 pbb4 { 650 nvidia,pins = "pbb4"; 651 nvidia,function = "vgp4"; 652 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 653 nvidia,tristate = <TEGRA_PIN_DISABLE>; 654 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 655 }; 656 pbb5 { 657 nvidia,pins = "pbb5"; 658 nvidia,function = "vgp5"; 659 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 660 nvidia,tristate = <TEGRA_PIN_DISABLE>; 661 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 662 }; 663 pbb6 { 664 nvidia,pins = "pbb6"; 665 nvidia,function = "vgp6"; 666 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 667 nvidia,tristate = <TEGRA_PIN_DISABLE>; 668 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 669 }; 670 pbb7 { 671 nvidia,pins = "pbb7", 672 "pcc2"; 673 nvidia,function = "i2s4"; 674 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 675 nvidia,tristate = <TEGRA_PIN_DISABLE>; 676 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 677 }; 678 cam_mclk_pcc0 { 679 nvidia,pins = "cam_mclk_pcc0"; 680 nvidia,function = "vi_alt3"; 681 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 682 nvidia,tristate = <TEGRA_PIN_DISABLE>; 683 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 684 }; 685 sdmmc4_rst_n_pcc3 { 686 nvidia,pins = "sdmmc4_rst_n_pcc3"; 687 nvidia,function = "rsvd2"; 688 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 689 nvidia,tristate = <TEGRA_PIN_DISABLE>; 690 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 691 }; 692 sdmmc4_clk_pcc4 { 693 nvidia,pins = "sdmmc4_clk_pcc4"; 694 nvidia,function = "sdmmc4"; 695 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 696 nvidia,tristate = <TEGRA_PIN_DISABLE>; 697 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 698 }; 699 clk2_req_pcc5 { 700 nvidia,pins = "clk2_req_pcc5"; 701 nvidia,function = "dap"; 702 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 703 nvidia,tristate = <TEGRA_PIN_DISABLE>; 704 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 705 }; 706 pex_l2_rst_n_pcc6 { 707 nvidia,pins = "pex_l2_rst_n_pcc6", 708 "pex_l2_clkreq_n_pcc7"; 709 nvidia,function = "pcie"; 710 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 711 nvidia,tristate = <TEGRA_PIN_DISABLE>; 712 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 713 }; 714 pex_wake_n_pdd3 { 715 nvidia,pins = "pex_wake_n_pdd3", 716 "pex_l2_prsnt_n_pdd7"; 717 nvidia,function = "pcie"; 718 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 719 nvidia,tristate = <TEGRA_PIN_DISABLE>; 720 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 721 }; 722 clk3_out_pee0 { 723 nvidia,pins = "clk3_out_pee0"; 724 nvidia,function = "extperiph3"; 725 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 726 nvidia,tristate = <TEGRA_PIN_DISABLE>; 727 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 728 }; 729 clk1_req_pee2 { 730 nvidia,pins = "clk1_req_pee2"; 731 nvidia,function = "dap"; 732 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 733 nvidia,tristate = <TEGRA_PIN_ENABLE>; 734 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 735 }; 736 hdmi_cec_pee3 { 737 nvidia,pins = "hdmi_cec_pee3"; 738 nvidia,function = "cec"; 739 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 740 nvidia,tristate = <TEGRA_PIN_DISABLE>; 741 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 742 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 743 }; 744 owr { 745 nvidia,pins = "owr"; 746 nvidia,function = "owr"; 747 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 748 nvidia,tristate = <TEGRA_PIN_DISABLE>; 749 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 750 }; 751 drive_dap1 { 752 nvidia,pins = "drive_dap1", 753 "drive_dap2", 754 "drive_dbg", 755 "drive_at5", 756 "drive_gme", 757 "drive_ddc", 758 "drive_ao1", 759 "drive_uart3"; 760 nvidia,high-speed-mode = <0>; 761 nvidia,schmitt = <TEGRA_PIN_ENABLE>; 762 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 763 nvidia,pull-down-strength = <31>; 764 nvidia,pull-up-strength = <31>; 765 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 766 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 767 }; 768 drive_sdio1 { 769 nvidia,pins = "drive_sdio1", 770 "drive_sdio3"; 771 nvidia,high-speed-mode = <0>; 772 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 773 nvidia,pull-down-strength = <46>; 774 nvidia,pull-up-strength = <42>; 775 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; 776 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; 777 }; 778 drive_gma { 779 nvidia,pins = "drive_gma", 780 "drive_gmb", 781 "drive_gmc", 782 "drive_gmd"; 783 nvidia,pull-down-strength = <9>; 784 nvidia,pull-up-strength = <9>; 785 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 786 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 787 }; 788 }; 789 }; 790 791 uartb: serial@70006040 { 792 compatible = "nvidia,tegra30-hsuart"; 793 /delete-property/ reg-shift; 794 /* GPS BCM4751 */ 795 }; 796 797 uartc: serial@70006200 { 798 compatible = "nvidia,tegra30-hsuart"; 799 /delete-property/ reg-shift; 800 status = "okay"; 801 802 nvidia,adjust-baud-rates = <0 9600 100>, 803 <9600 115200 200>, 804 <1000000 4000000 136>; 805 806 /* Azurewave AW-NH665 BCM4330B1 */ 807 bluetooth { 808 compatible = "brcm,bcm4330-bt"; 809 810 interrupt-parent = <&gpio>; 811 interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>; 812 interrupt-names = "host-wakeup"; 813 814 max-speed = <4000000>; 815 816 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 817 clock-names = "txco"; 818 819 vbat-supply = <&vdd_3v3_sys>; 820 vddio-supply = <&vdd_1v8>; 821 822 device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; 823 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; 824 }; 825 }; 826 827 pwm: pwm@7000a000 { 828 status = "okay"; 829 }; 830 831 i2c@7000c400 { 832 clock-frequency = <400000>; 833 status = "okay"; 834 835 touchscreen@10 { 836 compatible = "elan,ektf3624"; 837 reg = <0x10>; 838 839 interrupt-parent = <&gpio>; 840 interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_LEVEL_LOW>; 841 842 reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; 843 844 vcc33-supply = <&vcc_3v3_ts>; 845 vccio-supply = <&vcc_3v3_ts>; 846 847 touchscreen-size-x = <2112>; 848 touchscreen-size-y = <1280>; 849 touchscreen-swapped-x-y; 850 touchscreen-inverted-x; 851 }; 852 }; 853 854 i2c@7000c500 { 855 clock-frequency = <100000>; 856 status = "okay"; 857 858 compass@e { 859 compatible = "asahi-kasei,ak8974"; 860 reg = <0x0e>; 861 862 interrupt-parent = <&gpio>; 863 interrupts = <TEGRA_GPIO(W, 0) IRQ_TYPE_EDGE_RISING>; 864 865 avdd-supply = <&vdd_3v3_sys>; 866 dvdd-supply = <&vdd_1v8>; 867 868 mount-matrix = "0", "-1", "0", 869 "-1", "0", "0", 870 "0", "0", "-1"; 871 }; 872 873 light-sensor@1c { 874 compatible = "dynaimage,al3010"; 875 reg = <0x1c>; 876 877 interrupt-parent = <&gpio>; 878 interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; 879 880 vdd-supply = <&vdd_3v3_sys>; 881 }; 882 883 accelerometer@68 { 884 compatible = "invensense,mpu6050"; 885 reg = <0x68>; 886 887 interrupt-parent = <&gpio>; 888 interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>; 889 890 vdd-supply = <&vdd_3v3_sys>; 891 vddio-supply = <&vdd_1v8>; 892 893 mount-matrix = "0", "-1", "0", 894 "-1", "0", "0", 895 "0", "0", "-1"; 896 }; 897 }; 898 899 i2c@7000d000 { 900 clock-frequency = <100000>; 901 status = "okay"; 902 903 rt5640: audio-codec@1c { 904 compatible = "realtek,rt5640"; 905 reg = <0x1c>; 906 907 realtek,dmic1-data-pin = <1>; 908 }; 909 910 nct72: temperature-sensor@4c { 911 compatible = "onnn,nct1008"; 912 reg = <0x4c>; 913 vcc-supply = <&vdd_3v3_sys>; 914 915 interrupt-parent = <&gpio>; 916 interrupts = <TEGRA_GPIO(S, 3) IRQ_TYPE_EDGE_FALLING>; 917 918 #thermal-sensor-cells = <1>; 919 }; 920 921 fuel-gauge@55 { 922 compatible = "ti,bq27541"; 923 reg = <0x55>; 924 power-supplies = <&power_supply>; 925 }; 926 927 power_supply: charger@6a { 928 compatible = "summit,smb347"; 929 reg = <0x6a>; 930 931 interrupt-parent = <&gpio>; 932 interrupts = <TEGRA_GPIO(V, 1) IRQ_TYPE_EDGE_BOTH>; 933 934 summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW>; 935 summit,inok-polarity = <SMB3XX_SYSOK_INOK_ACTIVE_LOW>; 936 summit,enable-usb-charging; 937 938 monitored-battery = <&battery_cell>; 939 940 usb_vbus: usb-vbus { 941 regulator-name = "usb_vbus"; 942 regulator-min-microvolt = <5000000>; 943 regulator-max-microvolt = <5000000>; 944 regulator-min-microamp = <750000>; 945 regulator-max-microamp = <750000>; 946 947 /* 948 * SMB347 INOK input pin is connected to PMIC's 949 * ACOK output, which is fixed to ACTIVE_LOW as 950 * long as battery voltage is in a good range. 951 * 952 * Active INOK disables SMB347 output, so polarity 953 * needs to be toggled when we want to get the 954 * output. 955 */ 956 summit,needs-inok-toggle; 957 }; 958 }; 959 }; 960 961 pmc@7000e400 { 962 status = "okay"; 963 nvidia,invert-interrupt; 964 nvidia,suspend-mode = <1>; 965 nvidia,cpu-pwr-good-time = <2000>; 966 nvidia,cpu-pwr-off-time = <200>; 967 nvidia,core-pwr-good-time = <3845 3845>; 968 nvidia,core-pwr-off-time = <0>; 969 nvidia,core-power-req-active-high; 970 nvidia,sys-clock-req-active-high; 971 core-supply = <&vdd_core>; 972 }; 973 974 ahub@70080000 { 975 i2s@70080400 { 976 status = "okay"; 977 }; 978 }; 979 980 brcm_wifi_pwrseq: wifi-pwrseq { 981 compatible = "mmc-pwrseq-simple"; 982 983 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 984 clock-names = "ext_clock"; 985 986 reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; 987 post-power-on-delay-ms = <300>; 988 power-off-delay-us = <300>; 989 }; 990 991 sdmmc3: mmc@78000400 { 992 status = "okay"; 993 994 #address-cells = <1>; 995 #size-cells = <0>; 996 997 assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 998 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; 999 assigned-clock-rates = <50000000>; 1000 1001 max-frequency = <50000000>; 1002 keep-power-in-suspend; 1003 bus-width = <4>; 1004 non-removable; 1005 1006 mmc-pwrseq = <&brcm_wifi_pwrseq>; 1007 vmmc-supply = <&vdd_3v3_sys>; 1008 vqmmc-supply = <&vdd_1v8>; 1009 1010 /* Azurewave AW-NH665 BCM4330 */ 1011 wifi@1 { 1012 reg = <1>; 1013 compatible = "brcm,bcm4329-fmac"; 1014 interrupt-parent = <&gpio>; 1015 interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>; 1016 interrupt-names = "host-wake"; 1017 }; 1018 }; 1019 1020 sdmmc4: mmc@78000600 { 1021 status = "okay"; 1022 bus-width = <8>; 1023 vmmc-supply = <&vcore_emmc>; 1024 vqmmc-supply = <&vdd_1v8>; 1025 non-removable; 1026 }; 1027 1028 usb@7d000000 { 1029 compatible = "nvidia,tegra30-udc"; 1030 status = "okay"; 1031 dr_mode = "otg"; 1032 vbus-supply = <&usb_vbus>; 1033 }; 1034 1035 usb-phy@7d000000 { 1036 status = "okay"; 1037 dr_mode = "otg"; 1038 nvidia,hssync-start-delay = <0>; 1039 nvidia,xcvr-lsfslew = <2>; 1040 nvidia,xcvr-lsrslew = <2>; 1041 }; 1042 1043 backlight: backlight { 1044 compatible = "pwm-backlight"; 1045 1046 power-supply = <&vdd_5v0_sys>; 1047 pwms = <&pwm 0 50000>; 1048 1049 brightness-levels = <1 255>; 1050 num-interpolated-steps = <254>; 1051 default-brightness-level = <15>; 1052 }; 1053 1054 battery_cell: battery-cell { 1055 compatible = "simple-battery"; 1056 constant-charge-current-max-microamp = <1800000>; 1057 operating-range-celsius = <0 45>; 1058 }; 1059 1060 /* PMIC has a built-in 32KHz oscillator which is used by PMC */ 1061 clk32k_in: clock-32k { 1062 compatible = "fixed-clock"; 1063 #clock-cells = <0>; 1064 clock-frequency = <32768>; 1065 clock-output-names = "pmic-oscillator"; 1066 }; 1067 1068 cpus { 1069 cpu0: cpu@0 { 1070 cpu-supply = <&vdd_cpu>; 1071 operating-points-v2 = <&cpu0_opp_table>; 1072 #cooling-cells = <2>; 1073 }; 1074 1075 cpu1: cpu@1 { 1076 cpu-supply = <&vdd_cpu>; 1077 operating-points-v2 = <&cpu0_opp_table>; 1078 #cooling-cells = <2>; 1079 }; 1080 1081 cpu2: cpu@2 { 1082 cpu-supply = <&vdd_cpu>; 1083 operating-points-v2 = <&cpu0_opp_table>; 1084 #cooling-cells = <2>; 1085 }; 1086 1087 cpu3: cpu@3 { 1088 cpu-supply = <&vdd_cpu>; 1089 operating-points-v2 = <&cpu0_opp_table>; 1090 #cooling-cells = <2>; 1091 }; 1092 }; 1093 1094 display-panel { 1095 /* 1096 * Nexus 7 supports two compatible panel models: 1097 * 1098 * 1. hydis,hv070wx2-1e0 1099 * 2. chunghwa,claa070wp03xg 1100 * 1101 * We want to use timing which is optimized for Nexus 7, 1102 * hence we need to customize the timing. 1103 */ 1104 compatible = "panel-lvds"; 1105 1106 width-mm = <94>; 1107 height-mm = <150>; 1108 rotation = <180>; 1109 1110 data-mapping = "jeida-24"; 1111 1112 /* DDC unconnected on Nexus 7 */ 1113 /delete-property/ ddc-i2c-bus; 1114 }; 1115 1116 firmware { 1117 trusted-foundations { 1118 compatible = "tlm,trusted-foundations"; 1119 tlm,version-major = <0x0>; 1120 tlm,version-minor = <0x0>; 1121 }; 1122 }; 1123 1124 gpio-keys { 1125 compatible = "gpio-keys"; 1126 1127 switch-hall-sensor { 1128 label = "Lid"; 1129 gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; 1130 linux,input-type = <EV_SW>; 1131 linux,code = <SW_LID>; 1132 debounce-interval = <500>; 1133 wakeup-event-action = <EV_ACT_DEASSERTED>; 1134 wakeup-source; 1135 }; 1136 1137 key-power { 1138 label = "Power"; 1139 gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; 1140 linux,code = <KEY_POWER>; 1141 debounce-interval = <10>; 1142 wakeup-event-action = <EV_ACT_ASSERTED>; 1143 wakeup-source; 1144 }; 1145 1146 key-volume-up { 1147 label = "Volume Up"; 1148 gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; 1149 linux,code = <KEY_VOLUMEUP>; 1150 debounce-interval = <10>; 1151 wakeup-event-action = <EV_ACT_ASSERTED>; 1152 wakeup-source; 1153 }; 1154 1155 key-volume-down { 1156 label = "Volume Down"; 1157 gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; 1158 linux,code = <KEY_VOLUMEDOWN>; 1159 debounce-interval = <10>; 1160 wakeup-event-action = <EV_ACT_ASSERTED>; 1161 wakeup-source; 1162 }; 1163 }; 1164 1165 vdd_5v0_sys: regulator-5v0 { 1166 compatible = "regulator-fixed"; 1167 regulator-name = "vdd_5v0"; 1168 regulator-min-microvolt = <5000000>; 1169 regulator-max-microvolt = <5000000>; 1170 regulator-always-on; 1171 regulator-boot-on; 1172 }; 1173 1174 vdd_3v3_sys: regulator-3v3 { 1175 compatible = "regulator-fixed"; 1176 regulator-name = "vdd_3v3"; 1177 regulator-min-microvolt = <3300000>; 1178 regulator-max-microvolt = <3300000>; 1179 regulator-always-on; 1180 regulator-boot-on; 1181 vin-supply = <&vdd_5v0_sys>; 1182 }; 1183 1184 vdd_pnl: regulator-panel { 1185 compatible = "regulator-fixed"; 1186 regulator-name = "vdd_panel"; 1187 regulator-min-microvolt = <3300000>; 1188 regulator-max-microvolt = <3300000>; 1189 regulator-enable-ramp-delay = <300000>; 1190 gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; 1191 enable-active-high; 1192 vin-supply = <&vdd_3v3_sys>; 1193 }; 1194 1195 vcc_3v3_ts: regulator-ts { 1196 compatible = "regulator-fixed"; 1197 regulator-name = "ldo_s-1167_3v3"; 1198 regulator-min-microvolt = <3300000>; 1199 regulator-max-microvolt = <3300000>; 1200 regulator-always-on; 1201 regulator-boot-on; 1202 vin-supply = <&vdd_5v0_sys>; 1203 }; 1204 1205 sound { 1206 compatible = "nvidia,tegra-audio-rt5640-grouper", 1207 "nvidia,tegra-audio-rt5640"; 1208 nvidia,model = "ASUS Google Nexus 7 ALC5642"; 1209 1210 nvidia,audio-routing = 1211 "Headphones", "HPOR", 1212 "Headphones", "HPOL", 1213 "Speakers", "SPORP", 1214 "Speakers", "SPORN", 1215 "Speakers", "SPOLP", 1216 "Speakers", "SPOLN", 1217 "DMIC1", "Mic Jack"; 1218 1219 nvidia,i2s-controller = <&tegra_i2s1>; 1220 nvidia,audio-codec = <&rt5640>; 1221 1222 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; 1223 1224 clocks = <&tegra_car TEGRA30_CLK_PLL_A>, 1225 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1226 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1227 clock-names = "pll_a", "pll_a_out0", "mclk"; 1228 1229 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>, 1230 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1231 1232 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, 1233 <&tegra_car TEGRA30_CLK_EXTERN1>; 1234 }; 1235 1236 thermal-zones { 1237 /* 1238 * NCT72 has two sensors: 1239 * 1240 * 0: internal that monitors ambient/skin temperature 1241 * 1: external that is connected to the CPU's diode 1242 * 1243 * Ideally we should use userspace thermal governor, 1244 * but it's a much more complex solution. The "skin" 1245 * zone is a simpler solution which prevents Nexus 7 1246 * from getting too hot from a user's tactile perspective. 1247 * The CPU zone is intended to protect silicon from damage. 1248 */ 1249 1250 skin-thermal { 1251 polling-delay-passive = <1000>; /* milliseconds */ 1252 polling-delay = <5000>; /* milliseconds */ 1253 1254 thermal-sensors = <&nct72 0>; 1255 1256 trips { 1257 trip0: skin-alert { 1258 /* throttle at 57C until temperature drops to 56.8C */ 1259 temperature = <57000>; 1260 hysteresis = <200>; 1261 type = "passive"; 1262 }; 1263 1264 trip1: skin-crit { 1265 /* shut down at 65C */ 1266 temperature = <65000>; 1267 hysteresis = <2000>; 1268 type = "critical"; 1269 }; 1270 }; 1271 1272 cooling-maps { 1273 map0 { 1274 trip = <&trip0>; 1275 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1276 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1277 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1278 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1279 <&actmon THERMAL_NO_LIMIT 1280 THERMAL_NO_LIMIT>; 1281 }; 1282 }; 1283 }; 1284 1285 cpu-thermal { 1286 polling-delay-passive = <1000>; /* milliseconds */ 1287 polling-delay = <5000>; /* milliseconds */ 1288 1289 thermal-sensors = <&nct72 1>; 1290 1291 trips { 1292 trip2: cpu-alert { 1293 /* throttle at 85C until temperature drops to 84.8C */ 1294 temperature = <85000>; 1295 hysteresis = <200>; 1296 type = "passive"; 1297 }; 1298 1299 trip3: cpu-crit { 1300 /* shut down at 90C */ 1301 temperature = <90000>; 1302 hysteresis = <2000>; 1303 type = "critical"; 1304 }; 1305 }; 1306 1307 cooling-maps { 1308 map1 { 1309 trip = <&trip2>; 1310 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1311 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1312 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1313 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1314 <&actmon THERMAL_NO_LIMIT 1315 THERMAL_NO_LIMIT>; 1316 }; 1317 }; 1318 }; 1319 }; 1320 };
Cache object: b3776c48672803f2bf0ad270b35b925e
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