tegra30-ouya.dts

Version: - FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
    1 // SPDX-License-Identifier: GPL-2.0
    2 /dts-v1/;
    3 
    4 #include <dt-bindings/input/gpio-keys.h>
    5 #include <dt-bindings/input/input.h>
    6 #include <dt-bindings/thermal/thermal.h>
    7 
    8 #include "tegra30.dtsi"
    9 #include "tegra30-cpu-opp.dtsi"
   10 #include "tegra30-cpu-opp-microvolt.dtsi"
   11 
   12 / {
   13         model = "Ouya Game Console";
   14         compatible = "ouya,ouya", "nvidia,tegra30";
   15 
   16         aliases {
   17                 mmc0 = &sdmmc4; /* eMMC */
   18                 mmc1 = &sdmmc3; /* WiFi */
   19                 rtc0 = &pmic;
   20                 rtc1 = "/rtc@7000e000";
   21                 serial0 = &uartd; /* Debug Port */
   22                 serial1 = &uartc; /* Bluetooth */
   23         };
   24 
   25         chosen {
   26                 stdout-path = "serial0:115200n8";
   27         };
   28 
   29         memory@80000000 {
   30                 reg = <0x80000000 0x40000000>;
   31         };
   32 
   33         reserved-memory {
   34                 #address-cells = <1>;
   35                 #size-cells = <1>;
   36                 ranges;
   37 
   38                 linux,cma@80000000 {
   39                         compatible = "shared-dma-pool";
   40                         alloc-ranges = <0x80000000 0x30000000>;
   41                         size = <0x10000000>; /* 256MiB */
   42                         linux,cma-default;
   43                         reusable;
   44                 };
   45 
   46                 ramoops@bfdf0000 {
   47                         compatible = "ramoops";
   48                         reg = <0xbfdf0000 0x10000>;     /* 64kB */
   49                         console-size = <0x8000>;        /* 32kB */
   50                         record-size = <0x400>;          /*  1kB */
   51                         ecc-size = <16>;
   52                 };
   53 
   54                 trustzone@bfe00000 {
   55                         reg = <0xbfe00000 0x200000>;
   56                         no-map;
   57                 };
   58         };
   59 
   60         host1x@50000000 {
   61                 hdmi@54280000 {
   62                         status = "okay";
   63                         vdd-supply = <&vdd_vid_reg>;
   64                         pll-supply = <&ldo7_reg>;
   65                         hdmi-supply = <&sys_3v3_reg>;
   66                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
   67                         nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
   68                 };
   69         };
   70 
   71         pinmux@70000868 {
   72                 pinctrl-names = "default";
   73                 pinctrl-0 = <&state_default>;
   74 
   75                 state_default: pinmux {
   76                         clk_32k_out_pa0 {
   77                                 nvidia,pins = "clk_32k_out_pa0";
   78                                 nvidia,function = "blink";
   79                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
   80                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
   81                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
   82                         };
   83 
   84                         uart3_cts_n_pa1 {
   85                                 nvidia,pins = "uart3_cts_n_pa1";
   86                                 nvidia,function = "uartc";
   87                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
   88                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
   89                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
   90                         };
   91 
   92                         dap2_fs_pa2 {
   93                                 nvidia,pins = "dap2_fs_pa2";
   94                                 nvidia,function = "i2s1";
   95                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
   96                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
   97                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
   98                         };
   99 
  100                         dap2_sclk_pa3 {
  101                                 nvidia,pins = "dap2_sclk_pa3";
  102                                 nvidia,function = "i2s1";
  103                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  104                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  105                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  106                         };
  107 
  108                         dap2_din_pa4 {
  109                                 nvidia,pins = "dap2_din_pa4";
  110                                 nvidia,function = "i2s1";
  111                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  112                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  113                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  114                         };
  115 
  116                         dap2_dout_pa5 {
  117                                 nvidia,pins = "dap2_dout_pa5";
  118                                 nvidia,function = "i2s1";
  119                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  120                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  121                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  122                         };
  123 
  124                         sdmmc3_clk_pa6 {
  125                                 nvidia,pins = "sdmmc3_clk_pa6";
  126                                 nvidia,function = "sdmmc3";
  127                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  128                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  129                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  130                         };
  131 
  132                         sdmmc3_cmd_pa7 {
  133                                 nvidia,pins = "sdmmc3_cmd_pa7";
  134                                 nvidia,function = "sdmmc3";
  135                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
  136                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  137                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  138                         };
  139 
  140                         gmi_a17_pb0 {
  141                                 nvidia,pins = "gmi_a17_pb0";
  142                                 nvidia,function = "spi4";
  143                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  144                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  145                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  146                         };
  147 
  148                         gmi_a18_pb1 {
  149                                 nvidia,pins = "gmi_a18_pb1";
  150                                 nvidia,function = "spi4";
  151                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  152                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  153                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  154                         };
  155 
  156                         lcd_pwr0_pb2 {
  157                                 nvidia,pins = "lcd_pwr0_pb2";
  158                                 nvidia,function = "displaya";
  159                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  160                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  161                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  162                         };
  163 
  164                         lcd_pclk_pb3 {
  165                                 nvidia,pins = "lcd_pclk_pb3";
  166                                 nvidia,function = "displaya";
  167                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  168                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  169                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  170                         };
  171 
  172                         sdmmc3_dat3_pb4 {
  173                                 nvidia,pins = "sdmmc3_dat3_pb4";
  174                                 nvidia,function = "sdmmc3";
  175                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
  176                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  177                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  178                         };
  179 
  180                         sdmmc3_dat2_pb5 {
  181                                 nvidia,pins = "sdmmc3_dat2_pb5";
  182                                 nvidia,function = "sdmmc3";
  183                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
  184                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  185                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  186                         };
  187 
  188                         sdmmc3_dat1_pb6 {
  189                                 nvidia,pins = "sdmmc3_dat1_pb6";
  190                                 nvidia,function = "sdmmc3";
  191                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
  192                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  193                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  194                         };
  195 
  196                         sdmmc3_dat0_pb7 {
  197                                 nvidia,pins = "sdmmc3_dat0_pb7";
  198                                 nvidia,function = "sdmmc3";
  199                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
  200                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  201                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  202                         };
  203 
  204                         uart3_rts_n_pc0 {
  205                                 nvidia,pins = "uart3_rts_n_pc0";
  206                                 nvidia,function = "uartc";
  207                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  208                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  209                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  210                         };
  211 
  212                         lcd_pwr1_pc1 {
  213                                 nvidia,pins = "lcd_pwr1_pc1";
  214                                 nvidia,function = "displaya";
  215                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  216                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  217                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  218                         };
  219 
  220                         uart2_txd_pc2 {
  221                                 nvidia,pins = "uart2_txd_pc2";
  222                                 nvidia,function = "uartb";
  223                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  224                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  225                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  226                         };
  227 
  228                         uart2_rxd_pc3 {
  229                                 nvidia,pins = "uart2_rxd_pc3";
  230                                 nvidia,function = "uartb";
  231                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  232                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  233                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  234                         };
  235 
  236                         gen1_i2c_scl_pc4 {
  237                                 nvidia,pins = "gen1_i2c_scl_pc4";
  238                                 nvidia,function = "i2c1";
  239                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  240                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  241                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  242                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  243                         };
  244 
  245                         gen1_i2c_sda_pc5 {
  246                                 nvidia,pins = "gen1_i2c_sda_pc5";
  247                                 nvidia,function = "i2c1";
  248                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  249                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  250                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  251                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
  252                         };
  253 
  254                         lcd_pwr2_pc6 {
  255                                 nvidia,pins = "lcd_pwr2_pc6";
  256                                 nvidia,function = "displaya";
  257                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  258                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  259                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  260                         };
  261 
  262                         gmi_wp_n_pc7 {
  263                                 nvidia,pins = "gmi_wp_n_pc7";
  264                                 nvidia,function = "gmi";
  265                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  266                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  267                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  268                         };
  269 
  270                         sdmmc3_dat5_pd0 {
  271                                 nvidia,pins = "sdmmc3_dat5_pd0";
  272                                 nvidia,function = "sdmmc3";
  273                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
  274                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  275                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  276                         };
  277 
  278                         sdmmc3_dat4_pd1 {
  279                                 nvidia,pins = "sdmmc3_dat4_pd1";
  280                                 nvidia,function = "sdmmc3";
  281                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
  282                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  283                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  284                         };
  285 
  286                         lcd_dc1_pd2 {
  287                                 nvidia,pins = "lcd_dc1_pd2";
  288                                 nvidia,function = "displaya";
  289                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  290                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  291                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  292                         };
  293 
  294                         sdmmc3_dat6_pd3 {
  295                                 nvidia,pins = "sdmmc3_dat6_pd3";
  296                                 nvidia,function = "spi4";
  297                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  298                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  299                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  300                         };
  301 
  302                         sdmmc3_dat7_pd4 {
  303                                 nvidia,pins = "sdmmc3_dat7_pd4";
  304                                 nvidia,function = "spi4";
  305                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  306                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  307                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  308                         };
  309 
  310                         vi_d1_pd5 {
  311                                 nvidia,pins = "vi_d1_pd5";
  312                                 nvidia,function = "sdmmc2";
  313                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  314                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  315                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  316                         };
  317 
  318                         vi_vsync_pd6 {
  319                                 nvidia,pins = "vi_vsync_pd6";
  320                                 nvidia,function = "ddr";
  321                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  322                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  323                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  324                         };
  325 
  326                         vi_hsync_pd7 {
  327                                 nvidia,pins = "vi_hsync_pd7";
  328                                 nvidia,function = "ddr";
  329                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  330                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  331                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  332                         };
  333 
  334                         lcd_d0_pe0 {
  335                                 nvidia,pins = "lcd_d0_pe0";
  336                                 nvidia,function = "displaya";
  337                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  338                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  339                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  340                         };
  341 
  342                         lcd_d1_pe1 {
  343                                 nvidia,pins = "lcd_d1_pe1";
  344                                 nvidia,function = "displaya";
  345                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  346                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  347                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  348                         };
  349 
  350                         lcd_d2_pe2 {
  351                                 nvidia,pins = "lcd_d2_pe2";
  352                                 nvidia,function = "displaya";
  353                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  354                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  355                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  356                         };
  357 
  358                         lcd_d3_pe3 {
  359                                 nvidia,pins = "lcd_d3_pe3";
  360                                 nvidia,function = "displaya";
  361                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  362                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  363                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  364                         };
  365 
  366                         lcd_d4_pe4 {
  367                                 nvidia,pins = "lcd_d4_pe4";
  368                                 nvidia,function = "displaya";
  369                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  370                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  371                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  372                         };
  373 
  374                         lcd_d5_pe5 {
  375                                 nvidia,pins = "lcd_d5_pe5";
  376                                 nvidia,function = "displaya";
  377                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  378                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  379                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  380                         };
  381 
  382                         lcd_d6_pe6 {
  383                                 nvidia,pins = "lcd_d6_pe6";
  384                                 nvidia,function = "displaya";
  385                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  386                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  387                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  388                         };
  389 
  390                         lcd_d7_pe7 {
  391                                 nvidia,pins = "lcd_d7_pe7";
  392                                 nvidia,function = "displaya";
  393                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  394                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  395                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  396                         };
  397 
  398                         lcd_d8_pf0 {
  399                                 nvidia,pins = "lcd_d8_pf0";
  400                                 nvidia,function = "displaya";
  401                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  402                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  403                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  404                         };
  405 
  406                         lcd_d9_pf1 {
  407                                 nvidia,pins = "lcd_d9_pf1";
  408                                 nvidia,function = "displaya";
  409                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  410                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  411                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  412                         };
  413 
  414                         lcd_d10_pf2 {
  415                                 nvidia,pins = "lcd_d10_pf2";
  416                                 nvidia,function = "displaya";
  417                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  418                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  419                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  420                         };
  421 
  422                         lcd_d11_pf3 {
  423                                 nvidia,pins = "lcd_d11_pf3";
  424                                 nvidia,function = "displaya";
  425                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  426                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  427                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  428                         };
  429 
  430                         lcd_d12_pf4 {
  431                                 nvidia,pins = "lcd_d12_pf4";
  432                                 nvidia,function = "displaya";
  433                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  434                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  435                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  436                         };
  437 
  438                         lcd_d13_pf5 {
  439                                 nvidia,pins = "lcd_d13_pf5";
  440                                 nvidia,function = "displaya";
  441                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  442                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  443                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  444                         };
  445 
  446                         lcd_d14_pf6 {
  447                                 nvidia,pins = "lcd_d14_pf6";
  448                                 nvidia,function = "displaya";
  449                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  450                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  451                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  452                         };
  453 
  454                         lcd_d15_pf7 {
  455                                 nvidia,pins = "lcd_d15_pf7";
  456                                 nvidia,function = "displaya";
  457                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  458                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  459                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  460                         };
  461 
  462                         gmi_ad0_pg0 {
  463                                 nvidia,pins = "gmi_ad0_pg0";
  464                                 nvidia,function = "nand";
  465                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  466                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  467                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  468                         };
  469 
  470                         gmi_ad1_pg1 {
  471                                 nvidia,pins = "gmi_ad1_pg1";
  472                                 nvidia,function = "nand";
  473                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  474                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  475                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  476                         };
  477 
  478                         gmi_ad2_pg2 {
  479                                 nvidia,pins = "gmi_ad2_pg2";
  480                                 nvidia,function = "nand";
  481                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  482                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  483                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  484                         };
  485 
  486                         gmi_ad3_pg3 {
  487                                 nvidia,pins = "gmi_ad3_pg3";
  488                                 nvidia,function = "nand";
  489                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  490                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  491                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  492                         };
  493 
  494                         gmi_ad4_pg4 {
  495                                 nvidia,pins = "gmi_ad4_pg4";
  496                                 nvidia,function = "nand";
  497                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  498                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  499                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  500                         };
  501 
  502                         gmi_ad5_pg5 {
  503                                 nvidia,pins = "gmi_ad5_pg5";
  504                                 nvidia,function = "nand";
  505                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  506                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  507                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  508                         };
  509 
  510                         gmi_ad6_pg6 {
  511                                 nvidia,pins = "gmi_ad6_pg6";
  512                                 nvidia,function = "nand";
  513                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  514                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  515                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  516                         };
  517 
  518                         gmi_ad7_pg7 {
  519                                 nvidia,pins = "gmi_ad7_pg7";
  520                                 nvidia,function = "nand";
  521                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  522                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  523                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  524                         };
  525 
  526                         gmi_ad8_ph0 {
  527                                 nvidia,pins = "gmi_ad8_ph0";
  528                                 nvidia,function = "pwm0";
  529                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  530                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  531                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  532                         };
  533 
  534                         gmi_ad9_ph1 {
  535                                 nvidia,pins = "gmi_ad9_ph1";
  536                                 nvidia,function = "pwm1";
  537                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  538                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  539                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  540                         };
  541 
  542                         gmi_ad10_ph2 {
  543                                 nvidia,pins = "gmi_ad10_ph2";
  544                                 nvidia,function = "pwm2";
  545                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  546                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  547                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  548                         };
  549 
  550                         gmi_ad11_ph3 {
  551                                 nvidia,pins = "gmi_ad11_ph3";
  552                                 nvidia,function = "nand";
  553                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  554                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  555                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  556                         };
  557 
  558                         gmi_ad12_ph4 {
  559                                 nvidia,pins = "gmi_ad12_ph4";
  560                                 nvidia,function = "nand";
  561                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  562                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  563                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  564                         };
  565 
  566                         gmi_ad13_ph5 {
  567                                 nvidia,pins = "gmi_ad13_ph5";
  568                                 nvidia,function = "nand";
  569                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  570                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  571                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  572                         };
  573 
  574                         gmi_ad14_ph6 {
  575                                 nvidia,pins = "gmi_ad14_ph6";
  576                                 nvidia,function = "nand";
  577                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  578                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  579                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  580                         };
  581 
  582                         gmi_wr_n_pi0 {
  583                                 nvidia,pins = "gmi_wr_n_pi0";
  584                                 nvidia,function = "nand";
  585                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  586                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  587                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  588                         };
  589 
  590                         gmi_oe_n_pi1 {
  591                                 nvidia,pins = "gmi_oe_n_pi1";
  592                                 nvidia,function = "nand";
  593                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  594                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  595                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  596                         };
  597 
  598                         gmi_dqs_pi2 {
  599                                 nvidia,pins = "gmi_dqs_pi2";
  600                                 nvidia,function = "nand";
  601                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  602                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  603                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  604                         };
  605 
  606                         gmi_iordy_pi5 {
  607                                 nvidia,pins = "gmi_iordy_pi5";
  608                                 nvidia,function = "rsvd1";
  609                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  610                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  611                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  612                         };
  613 
  614                         gmi_cs7_n_pi6 {
  615                                 nvidia,pins = "gmi_cs7_n_pi6";
  616                                 nvidia,function = "nand";
  617                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  618                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  619                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  620                         };
  621 
  622                         gmi_wait_pi7 {
  623                                 nvidia,pins = "gmi_wait_pi7";
  624                                 nvidia,function = "nand";
  625                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  626                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  627                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  628                         };
  629 
  630                         lcd_de_pj1 {
  631                                 nvidia,pins = "lcd_de_pj1";
  632                                 nvidia,function = "displaya";
  633                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  634                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  635                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  636                         };
  637 
  638                         gmi_cs1_n_pj2 {
  639                                 nvidia,pins = "gmi_cs1_n_pj2";
  640                                 nvidia,function = "rsvd1";
  641                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  642                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  643                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  644                         };
  645 
  646                         lcd_hsync_pj3 {
  647                                 nvidia,pins = "lcd_hsync_pj3";
  648                                 nvidia,function = "displaya";
  649                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  650                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  651                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  652                         };
  653 
  654                         lcd_vsync_pj4 {
  655                                 nvidia,pins = "lcd_vsync_pj4";
  656                                 nvidia,function = "displaya";
  657                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  658                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  659                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  660                         };
  661 
  662                         uart2_cts_n_pj5 {
  663                                 nvidia,pins = "uart2_cts_n_pj5";
  664                                 nvidia,function = "uartb";
  665                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  666                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  667                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  668                         };
  669 
  670                         uart2_rts_n_pj6 {
  671                                 nvidia,pins = "uart2_rts_n_pj6";
  672                                 nvidia,function = "uartb";
  673                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  674                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  675                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  676                         };
  677 
  678                         gmi_a16_pj7 {
  679                                 nvidia,pins = "gmi_a16_pj7";
  680                                 nvidia,function = "spi4";
  681                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  682                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  683                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  684                         };
  685 
  686                         gmi_adv_n_pk0 {
  687                                 nvidia,pins = "gmi_adv_n_pk0";
  688                                 nvidia,function = "nand";
  689                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  690                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  691                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  692                         };
  693 
  694                         gmi_clk_pk1 {
  695                                 nvidia,pins = "gmi_clk_pk1";
  696                                 nvidia,function = "nand";
  697                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  698                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  699                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  700                         };
  701 
  702                         gmi_cs2_n_pk3 {
  703                                 nvidia,pins = "gmi_cs2_n_pk3";
  704                                 nvidia,function = "rsvd1";
  705                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  706                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  707                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  708                         };
  709 
  710                         gmi_cs3_n_pk4 {
  711                                 nvidia,pins = "gmi_cs3_n_pk4";
  712                                 nvidia,function = "nand";
  713                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  714                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  715                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  716                         };
  717 
  718                         spdif_out_pk5 {
  719                                 nvidia,pins = "spdif_out_pk5";
  720                                 nvidia,function = "spdif";
  721                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  722                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  723                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  724                         };
  725 
  726                         spdif_in_pk6 {
  727                                 nvidia,pins = "spdif_in_pk6";
  728                                 nvidia,function = "spdif";
  729                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  730                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  731                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  732                         };
  733 
  734                         gmi_a19_pk7 {
  735                                 nvidia,pins = "gmi_a19_pk7";
  736                                 nvidia,function = "spi4";
  737                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  738                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  739                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  740                         };
  741 
  742                         vi_d2_pl0 {
  743                                 nvidia,pins = "vi_d2_pl0";
  744                                 nvidia,function = "sdmmc2";
  745                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  746                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  747                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  748                         };
  749 
  750                         vi_d3_pl1 {
  751                                 nvidia,pins = "vi_d3_pl1";
  752                                 nvidia,function = "sdmmc2";
  753                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  754                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  755                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  756                         };
  757 
  758                         vi_d4_pl2 {
  759                                 nvidia,pins = "vi_d4_pl2";
  760                                 nvidia,function = "vi";
  761                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  762                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  763                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  764                         };
  765 
  766                         vi_d5_pl3 {
  767                                 nvidia,pins = "vi_d5_pl3";
  768                                 nvidia,function = "sdmmc2";
  769                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  770                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  771                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  772                         };
  773 
  774                         vi_d6_pl4 {
  775                                 nvidia,pins = "vi_d6_pl4";
  776                                 nvidia,function = "vi";
  777                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  778                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  779                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  780                         };
  781 
  782                         vi_d7_pl5 {
  783                                 nvidia,pins = "vi_d7_pl5";
  784                                 nvidia,function = "sdmmc2";
  785                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  786                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  787                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  788                         };
  789 
  790                         vi_d8_pl6 {
  791                                 nvidia,pins = "vi_d8_pl6";
  792                                 nvidia,function = "sdmmc2";
  793                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  794                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  795                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  796                         };
  797 
  798                         vi_d9_pl7 {
  799                                 nvidia,pins = "vi_d9_pl7";
  800                                 nvidia,function = "sdmmc2";
  801                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  802                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  803                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  804                         };
  805 
  806                         lcd_d16_pm0 {
  807                                 nvidia,pins = "lcd_d16_pm0";
  808                                 nvidia,function = "displaya";
  809                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  810                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  811                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  812                         };
  813 
  814                         lcd_d17_pm1 {
  815                                 nvidia,pins = "lcd_d17_pm1";
  816                                 nvidia,function = "displaya";
  817                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  818                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  819                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  820                         };
  821 
  822                         lcd_d18_pm2 {
  823                                 nvidia,pins = "lcd_d18_pm2";
  824                                 nvidia,function = "displaya";
  825                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  826                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  827                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  828                         };
  829 
  830                         lcd_d19_pm3 {
  831                                 nvidia,pins = "lcd_d19_pm3";
  832                                 nvidia,function = "displaya";
  833                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  834                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  835                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  836                         };
  837 
  838                         lcd_d20_pm4 {
  839                                 nvidia,pins = "lcd_d20_pm4";
  840                                 nvidia,function = "displaya";
  841                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  842                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  843                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  844                         };
  845 
  846                         lcd_d21_pm5 {
  847                                 nvidia,pins = "lcd_d21_pm5";
  848                                 nvidia,function = "displaya";
  849                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  850                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  851                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  852                         };
  853 
  854                         lcd_d22_pm6 {
  855                                 nvidia,pins = "lcd_d22_pm6";
  856                                 nvidia,function = "displaya";
  857                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  858                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  859                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  860                         };
  861 
  862                         lcd_d23_pm7 {
  863                                 nvidia,pins = "lcd_d23_pm7";
  864                                 nvidia,function = "displaya";
  865                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  866                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  867                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  868                         };
  869 
  870                         dap1_fs_pn0 {
  871                                 nvidia,pins = "dap1_fs_pn0";
  872                                 nvidia,function = "i2s0";
  873                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  874                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  875                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  876                         };
  877 
  878                         dap1_din_pn1 {
  879                                 nvidia,pins = "dap1_din_pn1";
  880                                 nvidia,function = "i2s0";
  881                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  882                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  883                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  884                         };
  885 
  886                         dap1_dout_pn2 {
  887                                 nvidia,pins = "dap1_dout_pn2";
  888                                 nvidia,function = "i2s0";
  889                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  890                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  891                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  892                         };
  893 
  894                         dap1_sclk_pn3 {
  895                                 nvidia,pins = "dap1_sclk_pn3";
  896                                 nvidia,function = "i2s0";
  897                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  898                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  899                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  900                         };
  901 
  902                         lcd_cs0_n_pn4 {
  903                                 nvidia,pins = "lcd_cs0_n_pn4";
  904                                 nvidia,function = "displaya";
  905                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  906                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  907                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  908                         };
  909 
  910                         lcd_sdout_pn5 {
  911                                 nvidia,pins = "lcd_sdout_pn5";
  912                                 nvidia,function = "displaya";
  913                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  914                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  915                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  916                         };
  917 
  918                         lcd_dc0_pn6 {
  919                                 nvidia,pins = "lcd_dc0_pn6";
  920                                 nvidia,function = "displaya";
  921                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  922                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  923                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  924                         };
  925 
  926                         hdmi_int_pn7 {
  927                                 nvidia,pins = "hdmi_int_pn7";
  928                                 nvidia,function = "hdmi";
  929                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  930                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  931                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  932                         };
  933 
  934                         ulpi_data7_po0 {
  935                                 nvidia,pins = "ulpi_data7_po0";
  936                                 nvidia,function = "uarta";
  937                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  938                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  939                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  940                         };
  941 
  942                         ulpi_data0_po1 {
  943                                 nvidia,pins = "ulpi_data0_po1";
  944                                 nvidia,function = "uarta";
  945                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  946                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  947                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  948                         };
  949 
  950                         ulpi_data1_po2 {
  951                                 nvidia,pins = "ulpi_data1_po2";
  952                                 nvidia,function = "uarta";
  953                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  954                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  955                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  956                         };
  957 
  958                         ulpi_data2_po3 {
  959                                 nvidia,pins = "ulpi_data2_po3";
  960                                 nvidia,function = "uarta";
  961                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  962                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  963                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  964                         };
  965 
  966                         ulpi_data3_po4 {
  967                                 nvidia,pins = "ulpi_data3_po4";
  968                                 nvidia,function = "uarta";
  969                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  970                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  971                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  972                         };
  973 
  974                         ulpi_data4_po5 {
  975                                 nvidia,pins = "ulpi_data4_po5";
  976                                 nvidia,function = "uarta";
  977                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  978                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  979                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  980                         };
  981 
  982                         ulpi_data5_po6 {
  983                                 nvidia,pins = "ulpi_data5_po6";
  984                                 nvidia,function = "uarta";
  985                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  986                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  987                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  988                         };
  989 
  990                         ulpi_data6_po7 {
  991                                 nvidia,pins = "ulpi_data6_po7";
  992                                 nvidia,function = "uarta";
  993                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  994                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  995                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  996                         };
  997 
  998                         dap3_fs_pp0 {
  999                                 nvidia,pins = "dap3_fs_pp0";
 1000                                 nvidia,function = "i2s2";
 1001                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1002                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1003                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1004                         };
 1005 
 1006                         dap3_din_pp1 {
 1007                                 nvidia,pins = "dap3_din_pp1";
 1008                                 nvidia,function = "i2s2";
 1009                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1010                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1011                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1012                         };
 1013 
 1014                         dap3_dout_pp2 {
 1015                                 nvidia,pins = "dap3_dout_pp2";
 1016                                 nvidia,function = "i2s2";
 1017                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1018                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1019                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1020                         };
 1021 
 1022                         dap3_sclk_pp3 {
 1023                                 nvidia,pins = "dap3_sclk_pp3";
 1024                                 nvidia,function = "i2s2";
 1025                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1026                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1027                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1028                         };
 1029 
 1030                         dap4_fs_pp4 {
 1031                                 nvidia,pins = "dap4_fs_pp4";
 1032                                 nvidia,function = "i2s3";
 1033                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1034                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1035                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1036                         };
 1037 
 1038                         dap4_din_pp5 {
 1039                                 nvidia,pins = "dap4_din_pp5";
 1040                                 nvidia,function = "i2s3";
 1041                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1042                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1043                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1044                         };
 1045 
 1046                         dap4_dout_pp6 {
 1047                                 nvidia,pins = "dap4_dout_pp6";
 1048                                 nvidia,function = "i2s3";
 1049                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1050                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1051                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1052                         };
 1053 
 1054                         dap4_sclk_pp7 {
 1055                                 nvidia,pins = "dap4_sclk_pp7";
 1056                                 nvidia,function = "i2s3";
 1057                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1058                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1059                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1060                         };
 1061 
 1062                         kb_col0_pq0 {
 1063                                 nvidia,pins = "kb_col0_pq0";
 1064                                 nvidia,function = "kbc";
 1065                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1066                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1067                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1068                         };
 1069 
 1070                         kb_col1_pq1 {
 1071                                 nvidia,pins = "kb_col1_pq1";
 1072                                 nvidia,function = "kbc";
 1073                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1074                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1075                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1076                         };
 1077 
 1078                         kb_col2_pq2 {
 1079                                 nvidia,pins = "kb_col2_pq2";
 1080                                 nvidia,function = "kbc";
 1081                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1082                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1083                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1084                         };
 1085 
 1086                         kb_col3_pq3 {
 1087                                 nvidia,pins = "kb_col3_pq3";
 1088                                 nvidia,function = "kbc";
 1089                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1090                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1091                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1092                         };
 1093 
 1094                         kb_col4_pq4 {
 1095                                 nvidia,pins = "kb_col4_pq4";
 1096                                 nvidia,function = "kbc";
 1097                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1098                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1099                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1100                         };
 1101 
 1102                         kb_col5_pq5 {
 1103                                 nvidia,pins = "kb_col5_pq5";
 1104                                 nvidia,function = "kbc";
 1105                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1106                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1107                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1108                         };
 1109 
 1110                         kb_col6_pq6 {
 1111                                 nvidia,pins = "kb_col6_pq6";
 1112                                 nvidia,function = "kbc";
 1113                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1114                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1115                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1116                         };
 1117 
 1118                         kb_col7_pq7 {
 1119                                 nvidia,pins = "kb_col7_pq7";
 1120                                 nvidia,function = "kbc";
 1121                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1122                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1123                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1124                         };
 1125 
 1126                         kb_row0_pr0 {
 1127                                 nvidia,pins = "kb_row0_pr0";
 1128                                 nvidia,function = "kbc";
 1129                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1130                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1131                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1132                         };
 1133 
 1134                         kb_row1_pr1 {
 1135                                 nvidia,pins = "kb_row1_pr1";
 1136                                 nvidia,function = "kbc";
 1137                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1138                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1139                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1140                         };
 1141 
 1142                         kb_row2_pr2 {
 1143                                 nvidia,pins = "kb_row2_pr2";
 1144                                 nvidia,function = "kbc";
 1145                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1146                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1147                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1148                         };
 1149 
 1150                         kb_row3_pr3 {
 1151                                 nvidia,pins = "kb_row3_pr3";
 1152                                 nvidia,function = "kbc";
 1153                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1154                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1155                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1156                         };
 1157 
 1158                         kb_row4_pr4 {
 1159                                 nvidia,pins = "kb_row4_pr4";
 1160                                 nvidia,function = "kbc";
 1161                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1162                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1163                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1164                         };
 1165 
 1166                         kb_row5_pr5 {
 1167                                 nvidia,pins = "kb_row5_pr5";
 1168                                 nvidia,function = "kbc";
 1169                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1170                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1171                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1172                         };
 1173 
 1174                         kb_row6_pr6 {
 1175                                 nvidia,pins = "kb_row6_pr6";
 1176                                 nvidia,function = "kbc";
 1177                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1178                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1179                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1180                         };
 1181 
 1182                         kb_row7_pr7 {
 1183                                 nvidia,pins = "kb_row7_pr7";
 1184                                 nvidia,function = "kbc";
 1185                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1186                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1187                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1188                         };
 1189 
 1190                         kb_row8_ps0 {
 1191                                 nvidia,pins = "kb_row8_ps0";
 1192                                 nvidia,function = "kbc";
 1193                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1194                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1195                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1196                         };
 1197 
 1198                         kb_row9_ps1 {
 1199                                 nvidia,pins = "kb_row9_ps1";
 1200                                 nvidia,function = "kbc";
 1201                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1202                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1203                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1204                         };
 1205 
 1206                         kb_row10_ps2 {
 1207                                 nvidia,pins = "kb_row10_ps2";
 1208                                 nvidia,function = "kbc";
 1209                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1210                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1211                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1212                         };
 1213 
 1214                         kb_row11_ps3 {
 1215                                 nvidia,pins = "kb_row11_ps3";
 1216                                 nvidia,function = "kbc";
 1217                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1218                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1219                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1220                         };
 1221 
 1222                         kb_row12_ps4 {
 1223                                 nvidia,pins = "kb_row12_ps4";
 1224                                 nvidia,function = "kbc";
 1225                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1226                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1227                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1228                         };
 1229 
 1230                         kb_row13_ps5 {
 1231                                 nvidia,pins = "kb_row13_ps5";
 1232                                 nvidia,function = "kbc";
 1233                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1234                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1235                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1236                         };
 1237 
 1238                         kb_row14_ps6 {
 1239                                 nvidia,pins = "kb_row14_ps6";
 1240                                 nvidia,function = "kbc";
 1241                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1242                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1243                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1244                         };
 1245 
 1246                         kb_row15_ps7 {
 1247                                 nvidia,pins = "kb_row15_ps7";
 1248                                 nvidia,function = "kbc";
 1249                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1250                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1251                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1252                         };
 1253 
 1254                         vi_pclk_pt0 {
 1255                                 nvidia,pins = "vi_pclk_pt0";
 1256                                 nvidia,function = "rsvd1";
 1257                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 1258                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1259                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1260                         };
 1261 
 1262                         vi_mclk_pt1 {
 1263                                 nvidia,pins = "vi_mclk_pt1";
 1264                                 nvidia,function = "vi";
 1265                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1266                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1267                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1268                         };
 1269 
 1270                         vi_d10_pt2 {
 1271                                 nvidia,pins = "vi_d10_pt2";
 1272                                 nvidia,function = "ddr";
 1273                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1274                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1275                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1276                         };
 1277 
 1278                         vi_d11_pt3 {
 1279                                 nvidia,pins = "vi_d11_pt3";
 1280                                 nvidia,function = "ddr";
 1281                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 1282                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1283                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1284                         };
 1285 
 1286                         vi_d0_pt4 {
 1287                                 nvidia,pins = "vi_d0_pt4";
 1288                                 nvidia,function = "ddr";
 1289                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1290                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1291                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1292                         };
 1293 
 1294                         gen2_i2c_scl_pt5 {
 1295                                 nvidia,pins = "gen2_i2c_scl_pt5";
 1296                                 nvidia,function = "i2c2";
 1297                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1298                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1299                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1300                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 1301                         };
 1302 
 1303                         gen2_i2c_sda_pt6 {
 1304                                 nvidia,pins = "gen2_i2c_sda_pt6";
 1305                                 nvidia,function = "i2c2";
 1306                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1307                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1308                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1309                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 1310                         };
 1311 
 1312                         sdmmc4_cmd_pt7 {
 1313                                 nvidia,pins = "sdmmc4_cmd_pt7";
 1314                                 nvidia,function = "sdmmc4";
 1315                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 1316                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1317                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1318                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 1319                         };
 1320 
 1321                         pu0 {
 1322                                 nvidia,pins = "pu0";
 1323                                 nvidia,function = "owr";
 1324                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1325                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1326                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1327                         };
 1328 
 1329                         pu1 {
 1330                                 nvidia,pins = "pu1";
 1331                                 nvidia,function = "rsvd1";
 1332                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1333                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1334                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1335                         };
 1336 
 1337                         pu2 {
 1338                                 nvidia,pins = "pu2";
 1339                                 nvidia,function = "rsvd1";
 1340                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1341                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1342                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1343                         };
 1344 
 1345                         pu3 {
 1346                                 nvidia,pins = "pu3";
 1347                                 nvidia,function = "pwm0";
 1348                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1349                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1350                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1351                         };
 1352 
 1353                         pu4 {
 1354                                 nvidia,pins = "pu4";
 1355                                 nvidia,function = "pwm1";
 1356                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1357                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1358                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1359                         };
 1360 
 1361                         pu5 {
 1362                                 nvidia,pins = "pu5";
 1363                                 nvidia,function = "rsvd4";
 1364                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1365                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1366                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1367                         };
 1368 
 1369                         pu6 {
 1370                                 nvidia,pins = "pu6";
 1371                                 nvidia,function = "pwm3";
 1372                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1373                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1374                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1375                         };
 1376 
 1377                         jtag_rtck_pu7 {
 1378                                 nvidia,pins = "jtag_rtck_pu7";
 1379                                 nvidia,function = "rtck";
 1380                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1381                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1382                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1383                         };
 1384 
 1385                         pv0 {
 1386                                 nvidia,pins = "pv0";
 1387                                 nvidia,function = "rsvd1";
 1388                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 1389                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1390                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1391                         };
 1392 
 1393                         pv1 {
 1394                                 nvidia,pins = "pv1";
 1395                                 nvidia,function = "rsvd1";
 1396                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1397                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1398                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1399                         };
 1400 
 1401                         pv2 {
 1402                                 nvidia,pins = "pv2";
 1403                                 nvidia,function = "owr";
 1404                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1405                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1406                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1407                         };
 1408 
 1409                         pv3 {
 1410                                 nvidia,pins = "pv3";
 1411                                 nvidia,function = "clk_12m_out";
 1412                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1413                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1414                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1415                         };
 1416 
 1417                         ddc_scl_pv4 {
 1418                                 nvidia,pins = "ddc_scl_pv4";
 1419                                 nvidia,function = "i2c4";
 1420                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1421                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1422                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1423                         };
 1424 
 1425                         ddc_sda_pv5 {
 1426                                 nvidia,pins = "ddc_sda_pv5";
 1427                                 nvidia,function = "i2c4";
 1428                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1429                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1430                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1431                         };
 1432 
 1433                         crt_hsync_pv6 {
 1434                                 nvidia,pins = "crt_hsync_pv6";
 1435                                 nvidia,function = "crt";
 1436                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1437                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1438                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1439                         };
 1440 
 1441                         crt_vsync_pv7 {
 1442                                 nvidia,pins = "crt_vsync_pv7";
 1443                                 nvidia,function = "crt";
 1444                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1445                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1446                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1447                         };
 1448 
 1449                         lcd_cs1_n_pw0 {
 1450                                 nvidia,pins = "lcd_cs1_n_pw0";
 1451                                 nvidia,function = "displaya";
 1452                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1453                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1454                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1455                         };
 1456 
 1457                         lcd_m1_pw1 {
 1458                                 nvidia,pins = "lcd_m1_pw1";
 1459                                 nvidia,function = "displaya";
 1460                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 1461                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1462                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1463                         };
 1464 
 1465                         spi2_cs1_n_pw2 {
 1466                                 nvidia,pins = "spi2_cs1_n_pw2";
 1467                                 nvidia,function = "spi2";
 1468                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1469                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1470                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1471                         };
 1472 
 1473                         clk1_out_pw4 {
 1474                                 nvidia,pins = "clk1_out_pw4";
 1475                                 nvidia,function = "extperiph1";
 1476                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1477                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1478                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1479                         };
 1480 
 1481                         clk2_out_pw5 {
 1482                                 nvidia,pins = "clk2_out_pw5";
 1483                                 nvidia,function = "extperiph2";
 1484                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1485                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1486                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1487                         };
 1488 
 1489                         uart3_txd_pw6 {
 1490                                 nvidia,pins = "uart3_txd_pw6";
 1491                                 nvidia,function = "uartc";
 1492                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1493                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1494                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1495                         };
 1496 
 1497                         uart3_rxd_pw7 {
 1498                                 nvidia,pins = "uart3_rxd_pw7";
 1499                                 nvidia,function = "uartc";
 1500                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1501                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1502                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1503                         };
 1504 
 1505                         spi2_sck_px2 {
 1506                                 nvidia,pins = "spi2_sck_px2";
 1507                                 nvidia,function = "gmi";
 1508                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1509                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1510                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1511                         };
 1512 
 1513                         spi1_mosi_px4 {
 1514                                 nvidia,pins = "spi1_mosi_px4";
 1515                                 nvidia,function = "spi1";
 1516                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1517                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1518                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1519                         };
 1520 
 1521                         spi1_sck_px5 {
 1522                                 nvidia,pins = "spi1_sck_px5";
 1523                                 nvidia,function = "spi1";
 1524                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1525                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1526                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1527                         };
 1528 
 1529                         spi1_cs0_n_px6 {
 1530                                 nvidia,pins = "spi1_cs0_n_px6";
 1531                                 nvidia,function = "spi1";
 1532                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1533                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1534                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1535                         };
 1536 
 1537                         spi1_miso_px7 {
 1538                                 nvidia,pins = "spi1_miso_px7";
 1539                                 nvidia,function = "spi1";
 1540                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1541                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1542                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1543                         };
 1544 
 1545                         ulpi_clk_py0 {
 1546                                 nvidia,pins = "ulpi_clk_py0";
 1547                                 nvidia,function = "uartd";
 1548                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1549                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1550                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1551                         };
 1552 
 1553                         ulpi_dir_py1 {
 1554                                 nvidia,pins = "ulpi_dir_py1";
 1555                                 nvidia,function = "uartd";
 1556                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1557                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1558                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1559                         };
 1560 
 1561                         ulpi_nxt_py2 {
 1562                                 nvidia,pins = "ulpi_nxt_py2";
 1563                                 nvidia,function = "uartd";
 1564                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1565                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1566                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1567                         };
 1568 
 1569                         ulpi_stp_py3 {
 1570                                 nvidia,pins = "ulpi_stp_py3";
 1571                                 nvidia,function = "uartd";
 1572                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1573                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1574                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1575                         };
 1576 
 1577                         sdmmc1_dat3_py4 {
 1578                                 nvidia,pins = "sdmmc1_dat3_py4";
 1579                                 nvidia,function = "sdmmc1";
 1580                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1581                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1582                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1583                         };
 1584 
 1585                         sdmmc1_dat2_py5 {
 1586                                 nvidia,pins = "sdmmc1_dat2_py5";
 1587                                 nvidia,function = "sdmmc1";
 1588                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1589                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1590                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1591                         };
 1592 
 1593                         sdmmc1_dat1_py6 {
 1594                                 nvidia,pins = "sdmmc1_dat1_py6";
 1595                                 nvidia,function = "sdmmc1";
 1596                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1597                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1598                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1599                         };
 1600 
 1601                         sdmmc1_dat0_py7 {
 1602                                 nvidia,pins = "sdmmc1_dat0_py7";
 1603                                 nvidia,function = "sdmmc1";
 1604                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1605                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1606                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1607                         };
 1608 
 1609                         sdmmc1_clk_pz0 {
 1610                                 nvidia,pins = "sdmmc1_clk_pz0";
 1611                                 nvidia,function = "sdmmc1";
 1612                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1613                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1614                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1615                         };
 1616 
 1617                         sdmmc1_cmd_pz1 {
 1618                                 nvidia,pins = "sdmmc1_cmd_pz1";
 1619                                 nvidia,function = "sdmmc1";
 1620                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1621                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1622                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1623                         };
 1624 
 1625                         lcd_sdin_pz2 {
 1626                                 nvidia,pins = "lcd_sdin_pz2";
 1627                                 nvidia,function = "displaya";
 1628                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1629                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1630                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1631                         };
 1632 
 1633                         lcd_wr_n_pz3 {
 1634                                 nvidia,pins = "lcd_wr_n_pz3";
 1635                                 nvidia,function = "displaya";
 1636                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1637                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1638                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1639                         };
 1640 
 1641                         lcd_sck_pz4 {
 1642                                 nvidia,pins = "lcd_sck_pz4";
 1643                                 nvidia,function = "displaya";
 1644                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1645                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1646                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1647                         };
 1648 
 1649                         sys_clk_req_pz5 {
 1650                                 nvidia,pins = "sys_clk_req_pz5";
 1651                                 nvidia,function = "sysclk";
 1652                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1653                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1654                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1655                         };
 1656 
 1657                         pwr_i2c_scl_pz6 {
 1658                                 nvidia,pins = "pwr_i2c_scl_pz6";
 1659                                 nvidia,function = "i2cpwr";
 1660                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1661                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1662                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1663                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 1664                         };
 1665 
 1666                         pwr_i2c_sda_pz7 {
 1667                                 nvidia,pins = "pwr_i2c_sda_pz7";
 1668                                 nvidia,function = "i2cpwr";
 1669                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1670                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1671                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1672                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 1673                         };
 1674 
 1675                         sdmmc4_dat0_paa0 {
 1676                                 nvidia,pins = "sdmmc4_dat0_paa0";
 1677                                 nvidia,function = "sdmmc4";
 1678                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 1679                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1680                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1681                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 1682                         };
 1683 
 1684                         sdmmc4_dat1_paa1 {
 1685                                 nvidia,pins = "sdmmc4_dat1_paa1";
 1686                                 nvidia,function = "sdmmc4";
 1687                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 1688                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1689                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1690                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 1691                         };
 1692 
 1693                         sdmmc4_dat2_paa2 {
 1694                                 nvidia,pins = "sdmmc4_dat2_paa2";
 1695                                 nvidia,function = "sdmmc4";
 1696                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 1697                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1698                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1699                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 1700                         };
 1701 
 1702                         sdmmc4_dat3_paa3 {
 1703                                 nvidia,pins = "sdmmc4_dat3_paa3";
 1704                                 nvidia,function = "sdmmc4";
 1705                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 1706                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1707                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1708                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 1709                         };
 1710 
 1711                         sdmmc4_dat4_paa4 {
 1712                                 nvidia,pins = "sdmmc4_dat4_paa4";
 1713                                 nvidia,function = "sdmmc4";
 1714                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 1715                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1716                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1717                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 1718                         };
 1719 
 1720                         sdmmc4_dat5_paa5 {
 1721                                 nvidia,pins = "sdmmc4_dat5_paa5";
 1722                                 nvidia,function = "sdmmc4";
 1723                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 1724                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1725                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1726                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 1727                         };
 1728 
 1729                         sdmmc4_dat6_paa6 {
 1730                                 nvidia,pins = "sdmmc4_dat6_paa6";
 1731                                 nvidia,function = "sdmmc4";
 1732                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 1733                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1734                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1735                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 1736                         };
 1737 
 1738                         sdmmc4_dat7_paa7 {
 1739                                 nvidia,pins = "sdmmc4_dat7_paa7";
 1740                                 nvidia,function = "sdmmc4";
 1741                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 1742                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1743                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1744                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 1745                         };
 1746 
 1747                         pbb0 {
 1748                                 nvidia,pins = "pbb0";
 1749                                 nvidia,function = "i2s4";
 1750                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1751                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1752                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1753                         };
 1754 
 1755                         cam_i2c_scl_pbb1 {
 1756                                 nvidia,pins = "cam_i2c_scl_pbb1";
 1757                                 nvidia,function = "i2c3";
 1758                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1759                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1760                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1761                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 1762                         };
 1763 
 1764                         cam_i2c_sda_pbb2 {
 1765                                 nvidia,pins = "cam_i2c_sda_pbb2";
 1766                                 nvidia,function = "i2c3";
 1767                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1768                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1769                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1770                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 1771                         };
 1772 
 1773                         pbb3 {
 1774                                 nvidia,pins = "pbb3";
 1775                                 nvidia,function = "vgp3";
 1776                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1777                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1778                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1779                         };
 1780 
 1781                         pbb4 {
 1782                                 nvidia,pins = "pbb4";
 1783                                 nvidia,function = "vgp4";
 1784                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1785                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1786                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1787                         };
 1788 
 1789                         pbb5 {
 1790                                 nvidia,pins = "pbb5";
 1791                                 nvidia,function = "vgp5";
 1792                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1793                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1794                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1795                         };
 1796 
 1797                         pbb6 {
 1798                                 nvidia,pins = "pbb6";
 1799                                 nvidia,function = "vgp6";
 1800                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1801                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1802                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1803                         };
 1804 
 1805                         pbb7 {
 1806                                 nvidia,pins = "pbb7";
 1807                                 nvidia,function = "i2s4";
 1808                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1809                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1810                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1811                         };
 1812 
 1813                         cam_mclk_pcc0 {
 1814                                 nvidia,pins = "cam_mclk_pcc0";
 1815                                 nvidia,function = "vi_alt3";
 1816                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1817                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1818                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1819                         };
 1820 
 1821                         pcc1 {
 1822                                 nvidia,pins = "pcc1";
 1823                                 nvidia,function = "i2s4";
 1824                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1825                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1826                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1827                         };
 1828 
 1829                         pcc2 {
 1830                                 nvidia,pins = "pcc2";
 1831                                 nvidia,function = "i2s4";
 1832                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1833                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1834                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1835                         };
 1836 
 1837                         sdmmc4_rst_n_pcc3 {
 1838                                 nvidia,pins = "sdmmc4_rst_n_pcc3";
 1839                                 nvidia,function = "sdmmc4";
 1840                                 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
 1841                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1842                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1843                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 1844                         };
 1845 
 1846                         sdmmc4_clk_pcc4 {
 1847                                 nvidia,pins = "sdmmc4_clk_pcc4";
 1848                                 nvidia,function = "sdmmc4";
 1849                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1850                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1851                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1852                                 nvidia,io-reset = <TEGRA_PIN_DISABLE>;
 1853                         };
 1854 
 1855                         clk2_req_pcc5 {
 1856                                 nvidia,pins = "clk2_req_pcc5";
 1857                                 nvidia,function = "dap";
 1858                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1859                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1860                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1861                         };
 1862 
 1863                         pex_l2_rst_n_pcc6 {
 1864                                 nvidia,pins = "pex_l2_rst_n_pcc6";
 1865                                 nvidia,function = "pcie";
 1866                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1867                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1868                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1869                         };
 1870 
 1871                         pex_l2_clkreq_n_pcc7 {
 1872                                 nvidia,pins = "pex_l2_clkreq_n_pcc7";
 1873                                 nvidia,function = "pcie";
 1874                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1875                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1876                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1877                         };
 1878 
 1879                         pex_l0_prsnt_n_pdd0 {
 1880                                 nvidia,pins = "pex_l0_prsnt_n_pdd0";
 1881                                 nvidia,function = "pcie";
 1882                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1883                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1884                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1885                         };
 1886 
 1887                         pex_l0_rst_n_pdd1 {
 1888                                 nvidia,pins = "pex_l0_rst_n_pdd1";
 1889                                 nvidia,function = "pcie";
 1890                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1891                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1892                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1893                         };
 1894 
 1895                         pex_l0_clkreq_n_pdd2 {
 1896                                 nvidia,pins = "pex_l0_clkreq_n_pdd2";
 1897                                 nvidia,function = "pcie";
 1898                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1899                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1900                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1901                         };
 1902 
 1903                         pex_wake_n_pdd3 {
 1904                                 nvidia,pins = "pex_wake_n_pdd3";
 1905                                 nvidia,function = "pcie";
 1906                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1907                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1908                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1909                         };
 1910 
 1911                         pex_l1_prsnt_n_pdd4 {
 1912                                 nvidia,pins = "pex_l1_prsnt_n_pdd4";
 1913                                 nvidia,function = "pcie";
 1914                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1915                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1916                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1917                         };
 1918 
 1919                         pex_l1_rst_n_pdd5 {
 1920                                 nvidia,pins = "pex_l1_rst_n_pdd5";
 1921                                 nvidia,function = "pcie";
 1922                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1923                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1924                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1925                         };
 1926 
 1927                         pex_l1_clkreq_n_pdd6 {
 1928                                 nvidia,pins = "pex_l1_clkreq_n_pdd6";
 1929                                 nvidia,function = "pcie";
 1930                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1931                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1932                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1933                         };
 1934 
 1935                         pex_l2_prsnt_n_pdd7 {
 1936                                 nvidia,pins = "pex_l2_prsnt_n_pdd7";
 1937                                 nvidia,function = "pcie";
 1938                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1939                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1940                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1941                         };
 1942 
 1943                         clk3_out_pee0 {
 1944                                 nvidia,pins = "clk3_out_pee0";
 1945                                 nvidia,function = "extperiph3";
 1946                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1947                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1948                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1949                         };
 1950 
 1951                         clk3_req_pee1 {
 1952                                 nvidia,pins = "clk3_req_pee1";
 1953                                 nvidia,function = "dev3";
 1954                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1955                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1956                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1957                         };
 1958 
 1959                         clk1_req_pee2 {
 1960                                 nvidia,pins = "clk1_req_pee2";
 1961                                 nvidia,function = "dap";
 1962                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1963                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1964                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1965                         };
 1966 
 1967                         hdmi_cec_pee3 {
 1968                                 nvidia,pins = "hdmi_cec_pee3";
 1969                                 nvidia,function = "cec";
 1970                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1971                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 1972                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 1973                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 1974                         };
 1975 
 1976                         owr {
 1977                                 nvidia,pins = "owr";
 1978                                 nvidia,function = "owr";
 1979                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 1980                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 1981                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 1982                         };
 1983 
 1984                         drive_groups {
 1985                                 nvidia,pins = "drive_gma",
 1986                                               "drive_gmb",
 1987                                               "drive_gmc",
 1988                                               "drive_gmd";
 1989                                 nvidia,pull-down-strength = <9>;
 1990                                 nvidia,pull-up-strength = <9>;
 1991                                 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
 1992                                 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
 1993                         };
 1994                 };
 1995         };
 1996 
 1997         uartc: serial@70006200 {
 1998                 compatible = "nvidia,tegra30-hsuart";
 1999                 /delete-property/ reg-shift;
 2000                 status = "okay";
 2001 
 2002                 nvidia,adjust-baud-rates = <0 9600 100>,
 2003                                            <9600 115200 200>,
 2004                                            <1000000 4000000 136>;
 2005 
 2006                 /* Azurewave AW-NH660 BCM4330B1 */
 2007                 bluetooth {
 2008                         compatible = "brcm,bcm4330-bt";
 2009 
 2010                         interrupt-parent = <&gpio>;
 2011                         interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
 2012                         interrupt-names = "host-wakeup";
 2013 
 2014                         max-speed = <4000000>;
 2015 
 2016                         clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
 2017                         clock-names = "txco";
 2018 
 2019                         vbat-supply  = <&sys_3v3_reg>;
 2020                         vddio-supply = <&vdd_1v8>;
 2021 
 2022                         shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
 2023                         device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
 2024                 };
 2025         };
 2026 
 2027         uartd: serial@70006300 {
 2028                 status = "okay";
 2029         };
 2030 
 2031         hdmi_ddc: i2c@7000c700 {
 2032                 status = "okay";
 2033                 clock-frequency = <100000>;
 2034         };
 2035 
 2036         i2c@7000d000 {
 2037                 status = "okay";
 2038                 clock-frequency = <400000>;
 2039 
 2040                 cpu_temp: nct1008@4c {
 2041                         compatible = "onnn,nct1008";
 2042                         reg = <0x4c>;
 2043                         vcc-supply = <&sys_3v3_reg>;
 2044 
 2045                         interrupt-parent = <&gpio>;
 2046                         interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
 2047 
 2048                         #thermal-sensor-cells = <1>;
 2049                 };
 2050 
 2051                 pmic: pmic@2d {
 2052                         compatible = "ti,tps65911";
 2053                         reg = <0x2d>;
 2054 
 2055                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 2056                         #interrupt-cells = <2>;
 2057                         interrupt-controller;
 2058                         wakeup-source;
 2059 
 2060                         ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>;
 2061                         ti,system-power-controller;
 2062                         ti,sleep-keep-ck32k;
 2063                         ti,sleep-enable;
 2064 
 2065                         #gpio-cells = <2>;
 2066                         gpio-controller;
 2067 
 2068                         vcc1-supply = <&vdd_5v0_reg>;
 2069                         vcc2-supply = <&vdd_5v0_reg>;
 2070                         vcc3-supply = <&vdd_1v8>;
 2071                         vcc4-supply = <&vdd_5v0_reg>;
 2072                         vcc5-supply = <&vdd_5v0_reg>;
 2073                         vcc6-supply = <&vdd2_reg>;
 2074                         vcc7-supply = <&vdd_5v0_reg>;
 2075                         vccio-supply = <&vdd_5v0_reg>;
 2076 
 2077                         regulators {
 2078                                 vdd1_reg: vdd1 {
 2079                                         regulator-name = "vddio_ddr_1v2";
 2080                                         regulator-min-microvolt = <1200000>;
 2081                                         regulator-max-microvolt = <1200000>;
 2082                                         regulator-always-on;
 2083                                 };
 2084 
 2085                                 vdd2_reg: vdd2 {
 2086                                         regulator-name = "vdd_1v5_gen";
 2087                                         regulator-min-microvolt = <1500000>;
 2088                                         regulator-max-microvolt = <1500000>;
 2089                                         regulator-always-on;
 2090                                 };
 2091 
 2092                                 vdd_cpu: vddctrl {
 2093                                         regulator-name = "vdd_cpu,vdd_sys";
 2094                                         regulator-min-microvolt = <800000>;
 2095                                         regulator-max-microvolt = <1270000>;
 2096                                         regulator-coupled-with = <&vdd_core>;
 2097                                         regulator-coupled-max-spread = <300000>;
 2098                                         regulator-max-step-microvolt = <100000>;
 2099                                         regulator-always-on;
 2100 
 2101                                         nvidia,tegra-cpu-regulator;
 2102                                 };
 2103 
 2104                                 vdd_1v8: vio {
 2105                                         regulator-name = "vdd_1v8_gen";
 2106                                         regulator-min-microvolt = <1800000>;
 2107                                         regulator-max-microvolt = <1800000>;
 2108                                         regulator-always-on;
 2109                                 };
 2110 
 2111                                 ldo1_reg: ldo1 {
 2112                                         regulator-name = "vdd_pexa,vdd_pexb";
 2113                                         regulator-min-microvolt = <1050000>;
 2114                                         regulator-max-microvolt = <1050000>;
 2115                                         regulator-always-on;
 2116                                 };
 2117 
 2118                                 ldo2_reg: ldo2 {
 2119                                         regulator-name = "vdd_sata,avdd_plle";
 2120                                         regulator-min-microvolt = <1050000>;
 2121                                         regulator-max-microvolt = <1050000>;
 2122                                         regulator-always-on;
 2123                                 };
 2124 
 2125                                 /* LDO3 is not connected to anything */
 2126 
 2127                                 ldo4_reg: ldo4 {
 2128                                         regulator-name = "vdd_rtc";
 2129                                         regulator-min-microvolt = <1200000>;
 2130                                         regulator-max-microvolt = <1200000>;
 2131                                         regulator-always-on;
 2132                                 };
 2133 
 2134                                 ldo5_reg: ldo5 {
 2135                                         regulator-name = "vddio_sdmmc,avdd_vdac";
 2136                                         regulator-min-microvolt = <1800000>;
 2137                                         regulator-max-microvolt = <3300000>;
 2138                                         regulator-always-on;
 2139                                 };
 2140 
 2141                                 ldo6_reg: ldo6 {
 2142                                         regulator-name = "avdd_dsi_csi,pwrdet_mipi";
 2143                                         regulator-min-microvolt = <1200000>;
 2144                                         regulator-max-microvolt = <1200000>;
 2145                                         regulator-always-on;
 2146                                 };
 2147 
 2148                                 ldo7_reg: ldo7 {
 2149                                         regulator-name = "vdd_pllm,x,u,a_p_c_s";
 2150                                         regulator-min-microvolt = <1200000>;
 2151                                         regulator-max-microvolt = <1200000>;
 2152                                         regulator-always-on;
 2153                                 };
 2154 
 2155                                 ldo8_reg: ldo8 {
 2156                                         regulator-name = "vdd_ddr_hs";
 2157                                         regulator-min-microvolt = <1000000>;
 2158                                         regulator-max-microvolt = <1000000>;
 2159                                         regulator-always-on;
 2160                                 };
 2161                         };
 2162                 };
 2163 
 2164                 vdd_core: tps62361@60 {
 2165                         compatible = "ti,tps62361";
 2166                         reg = <0x60>;
 2167 
 2168                         regulator-name = "vdd_core";
 2169                         regulator-min-microvolt = <950000>;
 2170                         regulator-max-microvolt = <1350000>;
 2171                         regulator-coupled-with = <&vdd_cpu>;
 2172                         regulator-coupled-max-spread = <300000>;
 2173                         regulator-max-step-microvolt = <100000>;
 2174                         regulator-boot-on;
 2175                         regulator-always-on;
 2176                         ti,vsel0-state-high;
 2177                         ti,vsel1-state-high;
 2178                         ti,enable-vout-discharge;
 2179 
 2180                         nvidia,tegra-core-regulator;
 2181                 };
 2182         };
 2183 
 2184         pmc@7000e400 {
 2185                 status = "okay";
 2186                 nvidia,invert-interrupt;
 2187                 nvidia,suspend-mode = <1>;
 2188                 nvidia,cpu-pwr-good-time = <2000>;
 2189                 nvidia,cpu-pwr-off-time = <200>;
 2190                 nvidia,core-pwr-good-time = <3845 3845>;
 2191                 nvidia,core-pwr-off-time = <458>;
 2192                 nvidia,core-power-req-active-high;
 2193                 nvidia,sys-clock-req-active-high;
 2194                 core-supply = <&vdd_core>;
 2195         };
 2196 
 2197         memory-controller@7000f000 {
 2198                 emc-timings-0 {
 2199                         nvidia,ram-code = <0>; /* Samsung RAM */
 2200 
 2201                         timing-25500000 {
 2202                                 clock-frequency = <25500000>;
 2203                                 nvidia,emem-configuration = <
 2204                                         0x00030003 /* MC_EMEM_ARB_CFG */
 2205                                         0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2206                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 2207                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 2208                                         0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 2209                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 2210                                         0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 2211                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 2212                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2213                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2214                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2215                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 2216                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 2217                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 2218                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 2219                                         0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 2220                                         0x75830303 /* MC_EMEM_ARB_MISC0 */
 2221                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2222                                 >;
 2223                         };
 2224 
 2225                         timing-51000000 {
 2226                                 clock-frequency = <51000000>;
 2227                                 nvidia,emem-configuration = <
 2228                                         0x00010003 /* MC_EMEM_ARB_CFG */
 2229                                         0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2230                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 2231                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 2232                                         0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 2233                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 2234                                         0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 2235                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 2236                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2237                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2238                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2239                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 2240                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 2241                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 2242                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 2243                                         0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 2244                                         0x74630303 /* MC_EMEM_ARB_MISC0 */
 2245                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2246                                 >;
 2247                         };
 2248 
 2249                         timing-102000000 {
 2250                                 clock-frequency = <102000000>;
 2251                                 nvidia,emem-configuration = <
 2252                                         0x00000003 /* MC_EMEM_ARB_CFG */
 2253                                         0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2254                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 2255                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 2256                                         0x00000003 /* MC_EMEM_ARB_TIMING_RC */
 2257                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 2258                                         0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
 2259                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 2260                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2261                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2262                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2263                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 2264                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 2265                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 2266                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 2267                                         0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
 2268                                         0x73c30504 /* MC_EMEM_ARB_MISC0 */
 2269                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2270                                 >;
 2271                         };
 2272 
 2273                         timing-204000000 {
 2274                                 clock-frequency = <204000000>;
 2275                                 nvidia,emem-configuration = <
 2276                                         0x00000006 /* MC_EMEM_ARB_CFG */
 2277                                         0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2278                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 2279                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 2280                                         0x00000005 /* MC_EMEM_ARB_TIMING_RC */
 2281                                         0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
 2282                                         0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
 2283                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 2284                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2285                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2286                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2287                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 2288                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 2289                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 2290                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 2291                                         0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
 2292                                         0x73840a06 /* MC_EMEM_ARB_MISC0 */
 2293                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2294                                 >;
 2295                         };
 2296 
 2297                         timing-400000000 {
 2298                                 clock-frequency = <400000000>;
 2299                                 nvidia,emem-configuration = <
 2300                                         0x0000000c /* MC_EMEM_ARB_CFG */
 2301                                         0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2302                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 2303                                         0x00000002 /* MC_EMEM_ARB_TIMING_RP */
 2304                                         0x00000009 /* MC_EMEM_ARB_TIMING_RC */
 2305                                         0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
 2306                                         0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
 2307                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 2308                                         0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2309                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2310                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2311                                         0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 2312                                         0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
 2313                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 2314                                         0x06030202 /* MC_EMEM_ARB_DA_TURNS */
 2315                                         0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
 2316                                         0x7086120a /* MC_EMEM_ARB_MISC0 */
 2317                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2318                                 >;
 2319                         };
 2320 
 2321                         timing-800000000 {
 2322                                 clock-frequency = <800000000>;
 2323                                 nvidia,emem-configuration = <
 2324                                         0x00000018 /* MC_EMEM_ARB_CFG */
 2325                                         0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2326                                         0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
 2327                                         0x00000005 /* MC_EMEM_ARB_TIMING_RP */
 2328                                         0x00000013 /* MC_EMEM_ARB_TIMING_RC */
 2329                                         0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
 2330                                         0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
 2331                                         0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
 2332                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2333                                         0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2334                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2335                                         0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 2336                                         0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
 2337                                         0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
 2338                                         0x08040202 /* MC_EMEM_ARB_DA_TURNS */
 2339                                         0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
 2340                                         0x712c2414 /* MC_EMEM_ARB_MISC0 */
 2341                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2342                                 >;
 2343                         };
 2344                 };
 2345 
 2346                 emc-timings-1 {
 2347                         nvidia,ram-code = <1>; /* Hynix M RAM */
 2348 
 2349                         timing-25500000 {
 2350                                 clock-frequency = <25500000>;
 2351                                 nvidia,emem-configuration = <
 2352                                         0x00030003 /* MC_EMEM_ARB_CFG */
 2353                                         0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2354                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 2355                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 2356                                         0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 2357                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 2358                                         0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 2359                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 2360                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2361                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2362                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2363                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 2364                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 2365                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 2366                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 2367                                         0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 2368                                         0x75830303 /* MC_EMEM_ARB_MISC0 */
 2369                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2370                                 >;
 2371                         };
 2372 
 2373                         timing-51000000 {
 2374                                 clock-frequency = <51000000>;
 2375                                 nvidia,emem-configuration = <
 2376                                         0x00010003 /* MC_EMEM_ARB_CFG */
 2377                                         0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2378                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 2379                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 2380                                         0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 2381                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 2382                                         0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 2383                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 2384                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2385                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2386                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2387                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 2388                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 2389                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 2390                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 2391                                         0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 2392                                         0x74630303 /* MC_EMEM_ARB_MISC0 */
 2393                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2394                                 >;
 2395                         };
 2396 
 2397                         timing-102000000 {
 2398                                 clock-frequency = <102000000>;
 2399                                 nvidia,emem-configuration = <
 2400                                         0x00000003 /* MC_EMEM_ARB_CFG */
 2401                                         0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2402                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 2403                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 2404                                         0x00000003 /* MC_EMEM_ARB_TIMING_RC */
 2405                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 2406                                         0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
 2407                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 2408                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2409                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2410                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2411                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 2412                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 2413                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 2414                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 2415                                         0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
 2416                                         0x73c30504 /* MC_EMEM_ARB_MISC0 */
 2417                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2418                                 >;
 2419                         };
 2420 
 2421                         timing-204000000 {
 2422                                 clock-frequency = <204000000>;
 2423                                 nvidia,emem-configuration = <
 2424                                         0x00000006 /* MC_EMEM_ARB_CFG */
 2425                                         0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2426                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 2427                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 2428                                         0x00000005 /* MC_EMEM_ARB_TIMING_RC */
 2429                                         0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
 2430                                         0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
 2431                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 2432                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2433                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2434                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2435                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 2436                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 2437                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 2438                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 2439                                         0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
 2440                                         0x73840a06 /* MC_EMEM_ARB_MISC0 */
 2441                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2442                                 >;
 2443                         };
 2444 
 2445                         timing-400000000 {
 2446                                 clock-frequency = <400000000>;
 2447                                 nvidia,emem-configuration = <
 2448                                         0x0000000c /* MC_EMEM_ARB_CFG */
 2449                                         0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2450                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 2451                                         0x00000002 /* MC_EMEM_ARB_TIMING_RP */
 2452                                         0x00000009 /* MC_EMEM_ARB_TIMING_RC */
 2453                                         0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
 2454                                         0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
 2455                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 2456                                         0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2457                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2458                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2459                                         0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 2460                                         0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
 2461                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 2462                                         0x06030202 /* MC_EMEM_ARB_DA_TURNS */
 2463                                         0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
 2464                                         0x7086120a /* MC_EMEM_ARB_MISC0 */
 2465                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2466                                 >;
 2467                         };
 2468 
 2469                         timing-800000000 {
 2470                                 clock-frequency = <800000000>;
 2471                                 nvidia,emem-configuration = <
 2472                                         0x00000018 /* MC_EMEM_ARB_CFG */
 2473                                         0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2474                                         0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
 2475                                         0x00000005 /* MC_EMEM_ARB_TIMING_RP */
 2476                                         0x00000013 /* MC_EMEM_ARB_TIMING_RC */
 2477                                         0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
 2478                                         0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
 2479                                         0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
 2480                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2481                                         0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2482                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2483                                         0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 2484                                         0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
 2485                                         0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
 2486                                         0x08040202 /* MC_EMEM_ARB_DA_TURNS */
 2487                                         0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
 2488                                         0x712c2414 /* MC_EMEM_ARB_MISC0 */
 2489                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2490                                 >;
 2491                         };
 2492                 };
 2493 
 2494                 emc-timings-2 {
 2495                         nvidia,ram-code = <2>; /* Hynix A RAM */
 2496 
 2497                         timing-25500000 {
 2498                                 clock-frequency = <25500000>;
 2499                                 nvidia,emem-configuration = <
 2500                                         0x00030003 /* MC_EMEM_ARB_CFG */
 2501                                         0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2502                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 2503                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 2504                                         0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 2505                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 2506                                         0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 2507                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 2508                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2509                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2510                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2511                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 2512                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 2513                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 2514                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 2515                                         0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 2516                                         0x75e30303 /* MC_EMEM_ARB_MISC0 */
 2517                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2518                                 >;
 2519                         };
 2520 
 2521                         timing-51000000 {
 2522                                 clock-frequency = <51000000>;
 2523                                 nvidia,emem-configuration = <
 2524                                         0x00010003 /* MC_EMEM_ARB_CFG */
 2525                                         0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2526                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 2527                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 2528                                         0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 2529                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 2530                                         0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
 2531                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 2532                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2533                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2534                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2535                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 2536                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 2537                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 2538                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 2539                                         0x000a0502 /* MC_EMEM_ARB_DA_COVERS */
 2540                                         0x74e30303 /* MC_EMEM_ARB_MISC0 */
 2541                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2542                                 >;
 2543                         };
 2544 
 2545                         timing-102000000 {
 2546                                 clock-frequency = <102000000>;
 2547                                 nvidia,emem-configuration = <
 2548                                         0x00000003 /* MC_EMEM_ARB_CFG */
 2549                                         0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2550                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 2551                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 2552                                         0x00000003 /* MC_EMEM_ARB_TIMING_RC */
 2553                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 2554                                         0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
 2555                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 2556                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2557                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2558                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2559                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 2560                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 2561                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 2562                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 2563                                         0x000a0503 /* MC_EMEM_ARB_DA_COVERS */
 2564                                         0x74430504 /* MC_EMEM_ARB_MISC0 */
 2565                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2566                                 >;
 2567                         };
 2568 
 2569                         timing-204000000 {
 2570                                 clock-frequency = <204000000>;
 2571                                 nvidia,emem-configuration = <
 2572                                         0x00000006 /* MC_EMEM_ARB_CFG */
 2573                                         0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2574                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 2575                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 2576                                         0x00000005 /* MC_EMEM_ARB_TIMING_RC */
 2577                                         0x00000002 /* MC_EMEM_ARB_TIMING_RAS */
 2578                                         0x00000004 /* MC_EMEM_ARB_TIMING_FAW */
 2579                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 2580                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2581                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2582                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2583                                         0x00000001 /* MC_EMEM_ARB_TIMING_W2W */
 2584                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2W */
 2585                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 2586                                         0x06020102 /* MC_EMEM_ARB_DA_TURNS */
 2587                                         0x000a0505 /* MC_EMEM_ARB_DA_COVERS */
 2588                                         0x74040a06 /* MC_EMEM_ARB_MISC0 */
 2589                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2590                                 >;
 2591                         };
 2592 
 2593                         timing-400000000 {
 2594                                 clock-frequency = <400000000>;
 2595                                 nvidia,emem-configuration = <
 2596                                         0x0000000c /* MC_EMEM_ARB_CFG */
 2597                                         0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2598                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 2599                                         0x00000002 /* MC_EMEM_ARB_TIMING_RP */
 2600                                         0x00000009 /* MC_EMEM_ARB_TIMING_RC */
 2601                                         0x00000005 /* MC_EMEM_ARB_TIMING_RAS */
 2602                                         0x00000007 /* MC_EMEM_ARB_TIMING_FAW */
 2603                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 2604                                         0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2605                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2606                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2607                                         0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 2608                                         0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
 2609                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 2610                                         0x06030202 /* MC_EMEM_ARB_DA_TURNS */
 2611                                         0x000d0709 /* MC_EMEM_ARB_DA_COVERS */
 2612                                         0x7086120a /* MC_EMEM_ARB_MISC0 */
 2613                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2614                                 >;
 2615                         };
 2616 
 2617                         timing-800000000 {
 2618                                 clock-frequency = <800000000>;
 2619                                 nvidia,emem-configuration = <
 2620                                         0x00000018 /* MC_EMEM_ARB_CFG */
 2621                                         0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */
 2622                                         0x00000004 /* MC_EMEM_ARB_TIMING_RCD */
 2623                                         0x00000005 /* MC_EMEM_ARB_TIMING_RP */
 2624                                         0x00000013 /* MC_EMEM_ARB_TIMING_RC */
 2625                                         0x0000000c /* MC_EMEM_ARB_TIMING_RAS */
 2626                                         0x0000000f /* MC_EMEM_ARB_TIMING_FAW */
 2627                                         0x00000002 /* MC_EMEM_ARB_TIMING_RRD */
 2628                                         0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 2629                                         0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */
 2630                                         0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
 2631                                         0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 2632                                         0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
 2633                                         0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
 2634                                         0x08040202 /* MC_EMEM_ARB_DA_TURNS */
 2635                                         0x00160d13 /* MC_EMEM_ARB_DA_COVERS */
 2636                                         0x712c2414 /* MC_EMEM_ARB_MISC0 */
 2637                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 2638                                 >;
 2639                         };
 2640                 };
 2641         };
 2642 
 2643         memory-controller@7000f400 {
 2644                 emc-timings-0 {
 2645                         nvidia,ram-code = <0>;  /* Samsung RAM */
 2646 
 2647                         timing-25500000 {
 2648                                 clock-frequency = <25500000>;
 2649                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 2650                                 nvidia,emc-mode-1 = <0x80100003>;
 2651                                 nvidia,emc-mode-2 = <0x80200008>;
 2652                                 nvidia,emc-mode-reset = <0x80001221>;
 2653                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 2654                                 nvidia,emc-cfg-periodic-qrst;
 2655                                 nvidia,emc-cfg-dyn-self-ref;
 2656                                 nvidia,emc-configuration = <
 2657                                         0x00000001 /* EMC_RC */
 2658                                         0x00000006 /* EMC_RFC */
 2659                                         0x00000000 /* EMC_RAS */
 2660                                         0x00000000 /* EMC_RP */
 2661                                         0x00000002 /* EMC_R2W */
 2662                                         0x0000000a /* EMC_W2R */
 2663                                         0x00000005 /* EMC_R2P */
 2664                                         0x0000000b /* EMC_W2P */
 2665                                         0x00000000 /* EMC_RD_RCD */
 2666                                         0x00000000 /* EMC_WR_RCD */
 2667                                         0x00000003 /* EMC_RRD */
 2668                                         0x00000001 /* EMC_REXT */
 2669                                         0x00000000 /* EMC_WEXT */
 2670                                         0x00000005 /* EMC_WDV */
 2671                                         0x00000005 /* EMC_QUSE */
 2672                                         0x00000004 /* EMC_QRST */
 2673                                         0x0000000a /* EMC_QSAFE */
 2674                                         0x0000000b /* EMC_RDV */
 2675                                         0x000000c0 /* EMC_REFRESH */
 2676                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 2677                                         0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
 2678                                         0x00000002 /* EMC_PDEX2WR */
 2679                                         0x00000002 /* EMC_PDEX2RD */
 2680                                         0x00000001 /* EMC_PCHG2PDEN */
 2681                                         0x00000000 /* EMC_ACT2PDEN */
 2682                                         0x00000007 /* EMC_AR2PDEN */
 2683                                         0x0000000f /* EMC_RW2PDEN */
 2684                                         0x00000007 /* EMC_TXSR */
 2685                                         0x00000007 /* EMC_TXSRDLL */
 2686                                         0x00000004 /* EMC_TCKE */
 2687                                         0x00000002 /* EMC_TFAW */
 2688                                         0x00000000 /* EMC_TRPAB */
 2689                                         0x00000004 /* EMC_TCLKSTABLE */
 2690                                         0x00000005 /* EMC_TCLKSTOP */
 2691                                         0x000000c7 /* EMC_TREFBW */
 2692                                         0x00000006 /* EMC_QUSE_EXTRA */
 2693                                         0x00000004 /* EMC_FBIO_CFG6 */
 2694                                         0x00000000 /* EMC_ODT_WRITE */
 2695                                         0x00000000 /* EMC_ODT_READ */
 2696                                         0x00004288 /* EMC_FBIO_CFG5 */
 2697                                         0x007800a4 /* EMC_CFG_DIG_DLL */
 2698                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 2699                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
 2700                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
 2701                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
 2702                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
 2703                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
 2704                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
 2705                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
 2706                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
 2707                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 2708                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 2709                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 2710                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 2711                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 2712                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 2713                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 2714                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 2715                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 2716                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 2717                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 2718                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 2719                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 2720                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 2721                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 2722                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 2723                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
 2724                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
 2725                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
 2726                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
 2727                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 2728                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
 2729                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
 2730                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 2731                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
 2732                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
 2733                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
 2734                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
 2735                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
 2736                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 2737                                         0x00000000 /* EMC_ZCAL_INTERVAL */
 2738                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
 2739                                         0x000c000c /* EMC_MRS_WAIT_CNT */
 2740                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 2741                                         0x00000000 /* EMC_CTT */
 2742                                         0x00000000 /* EMC_CTT_DURATION */
 2743                                         0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
 2744                                         0xe8000000 /* EMC_FBIO_SPARE */
 2745                                         0xff00ff00 /* EMC_CFG_RSV */
 2746                                 >;
 2747                         };
 2748 
 2749                         timing-51000000 {
 2750                                 clock-frequency = <51000000>;
 2751                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 2752                                 nvidia,emc-mode-1 = <0x80100003>;
 2753                                 nvidia,emc-mode-2 = <0x80200008>;
 2754                                 nvidia,emc-mode-reset = <0x80001221>;
 2755                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 2756                                 nvidia,emc-cfg-periodic-qrst;
 2757                                 nvidia,emc-cfg-dyn-self-ref;
 2758                                 nvidia,emc-configuration = <
 2759                                         0x00000002 /* EMC_RC */
 2760                                         0x0000000d /* EMC_RFC */
 2761                                         0x00000001 /* EMC_RAS */
 2762                                         0x00000000 /* EMC_RP */
 2763                                         0x00000002 /* EMC_R2W */
 2764                                         0x0000000a /* EMC_W2R */
 2765                                         0x00000005 /* EMC_R2P */
 2766                                         0x0000000b /* EMC_W2P */
 2767                                         0x00000000 /* EMC_RD_RCD */
 2768                                         0x00000000 /* EMC_WR_RCD */
 2769                                         0x00000003 /* EMC_RRD */
 2770                                         0x00000001 /* EMC_REXT */
 2771                                         0x00000000 /* EMC_WEXT */
 2772                                         0x00000005 /* EMC_WDV */
 2773                                         0x00000005 /* EMC_QUSE */
 2774                                         0x00000004 /* EMC_QRST */
 2775                                         0x0000000a /* EMC_QSAFE */
 2776                                         0x0000000b /* EMC_RDV */
 2777                                         0x00000181 /* EMC_REFRESH */
 2778                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 2779                                         0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
 2780                                         0x00000002 /* EMC_PDEX2WR */
 2781                                         0x00000002 /* EMC_PDEX2RD */
 2782                                         0x00000001 /* EMC_PCHG2PDEN */
 2783                                         0x00000000 /* EMC_ACT2PDEN */
 2784                                         0x00000007 /* EMC_AR2PDEN */
 2785                                         0x0000000f /* EMC_RW2PDEN */
 2786                                         0x0000000e /* EMC_TXSR */
 2787                                         0x0000000e /* EMC_TXSRDLL */
 2788                                         0x00000004 /* EMC_TCKE */
 2789                                         0x00000003 /* EMC_TFAW */
 2790                                         0x00000000 /* EMC_TRPAB */
 2791                                         0x00000004 /* EMC_TCLKSTABLE */
 2792                                         0x00000005 /* EMC_TCLKSTOP */
 2793                                         0x0000018e /* EMC_TREFBW */
 2794                                         0x00000006 /* EMC_QUSE_EXTRA */
 2795                                         0x00000004 /* EMC_FBIO_CFG6 */
 2796                                         0x00000000 /* EMC_ODT_WRITE */
 2797                                         0x00000000 /* EMC_ODT_READ */
 2798                                         0x00004288 /* EMC_FBIO_CFG5 */
 2799                                         0x007800a4 /* EMC_CFG_DIG_DLL */
 2800                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 2801                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
 2802                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
 2803                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
 2804                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
 2805                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
 2806                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
 2807                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
 2808                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
 2809                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 2810                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 2811                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 2812                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 2813                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 2814                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 2815                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 2816                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 2817                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 2818                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 2819                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 2820                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 2821                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 2822                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 2823                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 2824                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 2825                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
 2826                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
 2827                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
 2828                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
 2829                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 2830                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
 2831                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
 2832                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 2833                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
 2834                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
 2835                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
 2836                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
 2837                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
 2838                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 2839                                         0x00000000 /* EMC_ZCAL_INTERVAL */
 2840                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
 2841                                         0x000c000c /* EMC_MRS_WAIT_CNT */
 2842                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 2843                                         0x00000000 /* EMC_CTT */
 2844                                         0x00000000 /* EMC_CTT_DURATION */
 2845                                         0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
 2846                                         0xe8000000 /* EMC_FBIO_SPARE */
 2847                                         0xff00ff00 /* EMC_CFG_RSV */
 2848                                 >;
 2849                         };
 2850 
 2851                         timing-102000000 {
 2852                                 clock-frequency = <102000000>;
 2853                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 2854                                 nvidia,emc-mode-1 = <0x80100003>;
 2855                                 nvidia,emc-mode-2 = <0x80200008>;
 2856                                 nvidia,emc-mode-reset = <0x80001221>;
 2857                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 2858                                 nvidia,emc-cfg-periodic-qrst;
 2859                                 nvidia,emc-cfg-dyn-self-ref;
 2860                                 nvidia,emc-configuration = <
 2861                                         0x00000004 /* EMC_RC */
 2862                                         0x0000001a /* EMC_RFC */
 2863                                         0x00000003 /* EMC_RAS */
 2864                                         0x00000001 /* EMC_RP */
 2865                                         0x00000002 /* EMC_R2W */
 2866                                         0x0000000a /* EMC_W2R */
 2867                                         0x00000005 /* EMC_R2P */
 2868                                         0x0000000b /* EMC_W2P */
 2869                                         0x00000001 /* EMC_RD_RCD */
 2870                                         0x00000001 /* EMC_WR_RCD */
 2871                                         0x00000003 /* EMC_RRD */
 2872                                         0x00000001 /* EMC_REXT */
 2873                                         0x00000000 /* EMC_WEXT */
 2874                                         0x00000005 /* EMC_WDV */
 2875                                         0x00000005 /* EMC_QUSE */
 2876                                         0x00000004 /* EMC_QRST */
 2877                                         0x0000000a /* EMC_QSAFE */
 2878                                         0x0000000b /* EMC_RDV */
 2879                                         0x00000303 /* EMC_REFRESH */
 2880                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 2881                                         0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
 2882                                         0x00000002 /* EMC_PDEX2WR */
 2883                                         0x00000002 /* EMC_PDEX2RD */
 2884                                         0x00000001 /* EMC_PCHG2PDEN */
 2885                                         0x00000000 /* EMC_ACT2PDEN */
 2886                                         0x00000007 /* EMC_AR2PDEN */
 2887                                         0x0000000f /* EMC_RW2PDEN */
 2888                                         0x0000001c /* EMC_TXSR */
 2889                                         0x0000001c /* EMC_TXSRDLL */
 2890                                         0x00000004 /* EMC_TCKE */
 2891                                         0x00000005 /* EMC_TFAW */
 2892                                         0x00000000 /* EMC_TRPAB */
 2893                                         0x00000004 /* EMC_TCLKSTABLE */
 2894                                         0x00000005 /* EMC_TCLKSTOP */
 2895                                         0x0000031c /* EMC_TREFBW */
 2896                                         0x00000006 /* EMC_QUSE_EXTRA */
 2897                                         0x00000004 /* EMC_FBIO_CFG6 */
 2898                                         0x00000000 /* EMC_ODT_WRITE */
 2899                                         0x00000000 /* EMC_ODT_READ */
 2900                                         0x00004288 /* EMC_FBIO_CFG5 */
 2901                                         0x007800a4 /* EMC_CFG_DIG_DLL */
 2902                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 2903                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
 2904                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
 2905                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
 2906                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
 2907                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
 2908                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
 2909                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
 2910                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
 2911                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 2912                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 2913                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 2914                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 2915                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 2916                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 2917                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 2918                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 2919                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 2920                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 2921                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 2922                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 2923                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 2924                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 2925                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 2926                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 2927                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
 2928                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
 2929                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
 2930                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
 2931                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 2932                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
 2933                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
 2934                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 2935                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
 2936                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
 2937                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
 2938                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
 2939                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
 2940                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 2941                                         0x00000000 /* EMC_ZCAL_INTERVAL */
 2942                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
 2943                                         0x000c000c /* EMC_MRS_WAIT_CNT */
 2944                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 2945                                         0x00000000 /* EMC_CTT */
 2946                                         0x00000000 /* EMC_CTT_DURATION */
 2947                                         0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
 2948                                         0xe8000000 /* EMC_FBIO_SPARE */
 2949                                         0xff00ff00 /* EMC_CFG_RSV */
 2950                                 >;
 2951                         };
 2952 
 2953                         timing-204000000 {
 2954                                 clock-frequency = <204000000>;
 2955                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 2956                                 nvidia,emc-mode-1 = <0x80100003>;
 2957                                 nvidia,emc-mode-2 = <0x80200008>;
 2958                                 nvidia,emc-mode-reset = <0x80001221>;
 2959                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 2960                                 nvidia,emc-cfg-periodic-qrst;
 2961                                 nvidia,emc-cfg-dyn-self-ref;
 2962                                 nvidia,emc-configuration = <
 2963                                         0x00000009 /* EMC_RC */
 2964                                         0x00000035 /* EMC_RFC */
 2965                                         0x00000007 /* EMC_RAS */
 2966                                         0x00000002 /* EMC_RP */
 2967                                         0x00000002 /* EMC_R2W */
 2968                                         0x0000000a /* EMC_W2R */
 2969                                         0x00000005 /* EMC_R2P */
 2970                                         0x0000000b /* EMC_W2P */
 2971                                         0x00000002 /* EMC_RD_RCD */
 2972                                         0x00000002 /* EMC_WR_RCD */
 2973                                         0x00000003 /* EMC_RRD */
 2974                                         0x00000001 /* EMC_REXT */
 2975                                         0x00000000 /* EMC_WEXT */
 2976                                         0x00000005 /* EMC_WDV */
 2977                                         0x00000005 /* EMC_QUSE */
 2978                                         0x00000004 /* EMC_QRST */
 2979                                         0x0000000a /* EMC_QSAFE */
 2980                                         0x0000000b /* EMC_RDV */
 2981                                         0x00000607 /* EMC_REFRESH */
 2982                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 2983                                         0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
 2984                                         0x00000002 /* EMC_PDEX2WR */
 2985                                         0x00000002 /* EMC_PDEX2RD */
 2986                                         0x00000001 /* EMC_PCHG2PDEN */
 2987                                         0x00000000 /* EMC_ACT2PDEN */
 2988                                         0x00000007 /* EMC_AR2PDEN */
 2989                                         0x0000000f /* EMC_RW2PDEN */
 2990                                         0x00000038 /* EMC_TXSR */
 2991                                         0x00000038 /* EMC_TXSRDLL */
 2992                                         0x00000004 /* EMC_TCKE */
 2993                                         0x00000009 /* EMC_TFAW */
 2994                                         0x00000000 /* EMC_TRPAB */
 2995                                         0x00000004 /* EMC_TCLKSTABLE */
 2996                                         0x00000005 /* EMC_TCLKSTOP */
 2997                                         0x00000638 /* EMC_TREFBW */
 2998                                         0x00000006 /* EMC_QUSE_EXTRA */
 2999                                         0x00000006 /* EMC_FBIO_CFG6 */
 3000                                         0x00000000 /* EMC_ODT_WRITE */
 3001                                         0x00000000 /* EMC_ODT_READ */
 3002                                         0x00004288 /* EMC_FBIO_CFG5 */
 3003                                         0x004400a4 /* EMC_CFG_DIG_DLL */
 3004                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 3005                                         0x00080000 /* EMC_DLL_XFORM_DQS0 */
 3006                                         0x00080000 /* EMC_DLL_XFORM_DQS1 */
 3007                                         0x00080000 /* EMC_DLL_XFORM_DQS2 */
 3008                                         0x00080000 /* EMC_DLL_XFORM_DQS3 */
 3009                                         0x00080000 /* EMC_DLL_XFORM_DQS4 */
 3010                                         0x00080000 /* EMC_DLL_XFORM_DQS5 */
 3011                                         0x00080000 /* EMC_DLL_XFORM_DQS6 */
 3012                                         0x00080000 /* EMC_DLL_XFORM_DQS7 */
 3013                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 3014                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 3015                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 3016                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 3017                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 3018                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 3019                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 3020                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 3021                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 3022                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 3023                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 3024                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 3025                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 3026                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 3027                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 3028                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 3029                                         0x00080000 /* EMC_DLL_XFORM_DQ0 */
 3030                                         0x00080000 /* EMC_DLL_XFORM_DQ1 */
 3031                                         0x00080000 /* EMC_DLL_XFORM_DQ2 */
 3032                                         0x00080000 /* EMC_DLL_XFORM_DQ3 */
 3033                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 3034                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
 3035                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
 3036                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 3037                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
 3038                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
 3039                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
 3040                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
 3041                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
 3042                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 3043                                         0x00020000 /* EMC_ZCAL_INTERVAL */
 3044                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
 3045                                         0x000c000c /* EMC_MRS_WAIT_CNT */
 3046                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 3047                                         0x00000000 /* EMC_CTT */
 3048                                         0x00000000 /* EMC_CTT_DURATION */
 3049                                         0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
 3050                                         0xe8000000 /* EMC_FBIO_SPARE */
 3051                                         0xff00ff00 /* EMC_CFG_RSV */
 3052                                 >;
 3053                         };
 3054 
 3055                         timing-400000000 {
 3056                                 clock-frequency = <400000000>;
 3057                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 3058                                 nvidia,emc-mode-1 = <0x80100002>;
 3059                                 nvidia,emc-mode-2 = <0x80200000>;
 3060                                 nvidia,emc-mode-reset = <0x80000521>;
 3061                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 3062                                 nvidia,emc-configuration = <
 3063                                         0x00000012 /* EMC_RC */
 3064                                         0x00000066 /* EMC_RFC */
 3065                                         0x0000000c /* EMC_RAS */
 3066                                         0x00000004 /* EMC_RP */
 3067                                         0x00000003 /* EMC_R2W */
 3068                                         0x00000008 /* EMC_W2R */
 3069                                         0x00000002 /* EMC_R2P */
 3070                                         0x0000000a /* EMC_W2P */
 3071                                         0x00000004 /* EMC_RD_RCD */
 3072                                         0x00000004 /* EMC_WR_RCD */
 3073                                         0x00000002 /* EMC_RRD */
 3074                                         0x00000001 /* EMC_REXT */
 3075                                         0x00000000 /* EMC_WEXT */
 3076                                         0x00000004 /* EMC_WDV */
 3077                                         0x00000006 /* EMC_QUSE */
 3078                                         0x00000004 /* EMC_QRST */
 3079                                         0x0000000a /* EMC_QSAFE */
 3080                                         0x0000000c /* EMC_RDV */
 3081                                         0x00000bf0 /* EMC_REFRESH */
 3082                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 3083                                         0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
 3084                                         0x00000001 /* EMC_PDEX2WR */
 3085                                         0x00000008 /* EMC_PDEX2RD */
 3086                                         0x00000001 /* EMC_PCHG2PDEN */
 3087                                         0x00000000 /* EMC_ACT2PDEN */
 3088                                         0x00000008 /* EMC_AR2PDEN */
 3089                                         0x0000000f /* EMC_RW2PDEN */
 3090                                         0x0000006c /* EMC_TXSR */
 3091                                         0x00000200 /* EMC_TXSRDLL */
 3092                                         0x00000004 /* EMC_TCKE */
 3093                                         0x00000010 /* EMC_TFAW */
 3094                                         0x00000000 /* EMC_TRPAB */
 3095                                         0x00000004 /* EMC_TCLKSTABLE */
 3096                                         0x00000005 /* EMC_TCLKSTOP */
 3097                                         0x00000c30 /* EMC_TREFBW */
 3098                                         0x00000000 /* EMC_QUSE_EXTRA */
 3099                                         0x00000004 /* EMC_FBIO_CFG6 */
 3100                                         0x00000000 /* EMC_ODT_WRITE */
 3101                                         0x00000000 /* EMC_ODT_READ */
 3102                                         0x00007088 /* EMC_FBIO_CFG5 */
 3103                                         0x001d0084 /* EMC_CFG_DIG_DLL */
 3104                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 3105                                         0x0003c000 /* EMC_DLL_XFORM_DQS0 */
 3106                                         0x0003c000 /* EMC_DLL_XFORM_DQS1 */
 3107                                         0x0003c000 /* EMC_DLL_XFORM_DQS2 */
 3108                                         0x0003c000 /* EMC_DLL_XFORM_DQS3 */
 3109                                         0x0003c000 /* EMC_DLL_XFORM_DQS4 */
 3110                                         0x0003c000 /* EMC_DLL_XFORM_DQS5 */
 3111                                         0x0003c000 /* EMC_DLL_XFORM_DQS6 */
 3112                                         0x0003c000 /* EMC_DLL_XFORM_DQS7 */
 3113                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 3114                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 3115                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 3116                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 3117                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 3118                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 3119                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 3120                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 3121                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 3122                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 3123                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 3124                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 3125                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 3126                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 3127                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 3128                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 3129                                         0x00048000 /* EMC_DLL_XFORM_DQ0 */
 3130                                         0x00048000 /* EMC_DLL_XFORM_DQ1 */
 3131                                         0x00048000 /* EMC_DLL_XFORM_DQ2 */
 3132                                         0x00048000 /* EMC_DLL_XFORM_DQ3 */
 3133                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 3134                                         0x0800013d /* EMC_XM2DQSPADCTRL2 */
 3135                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
 3136                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 3137                                         0x01f1f508 /* EMC_XM2COMPPADCTRL */
 3138                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
 3139                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
 3140                                         0x080001e8 /* EMC_XM2QUSEPADCTRL */
 3141                                         0x08000021 /* EMC_XM2DQSPADCTRL3 */
 3142                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 3143                                         0x00020000 /* EMC_ZCAL_INTERVAL */
 3144                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
 3145                                         0x0158000c /* EMC_MRS_WAIT_CNT */
 3146                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 3147                                         0x00000000 /* EMC_CTT */
 3148                                         0x00000000 /* EMC_CTT_DURATION */
 3149                                         0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
 3150                                         0xe8000000 /* EMC_FBIO_SPARE */
 3151                                         0xff00ff89 /* EMC_CFG_RSV */
 3152                                 >;
 3153                         };
 3154 
 3155                         timing-800000000 {
 3156                                 clock-frequency = <800000000>;
 3157                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 3158                                 nvidia,emc-mode-1 = <0x80100002>;
 3159                                 nvidia,emc-mode-2 = <0x80200018>;
 3160                                 nvidia,emc-mode-reset = <0x80000d71>;
 3161                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 3162                                 nvidia,emc-cfg-periodic-qrst;
 3163                                 nvidia,emc-configuration = <
 3164                                         0x00000025 /* EMC_RC */
 3165                                         0x000000ce /* EMC_RFC */
 3166                                         0x0000001a /* EMC_RAS */
 3167                                         0x00000009 /* EMC_RP */
 3168                                         0x00000005 /* EMC_R2W */
 3169                                         0x0000000d /* EMC_W2R */
 3170                                         0x00000004 /* EMC_R2P */
 3171                                         0x00000013 /* EMC_W2P */
 3172                                         0x00000009 /* EMC_RD_RCD */
 3173                                         0x00000009 /* EMC_WR_RCD */
 3174                                         0x00000004 /* EMC_RRD */
 3175                                         0x00000001 /* EMC_REXT */
 3176                                         0x00000000 /* EMC_WEXT */
 3177                                         0x00000007 /* EMC_WDV */
 3178                                         0x0000000a /* EMC_QUSE */
 3179                                         0x00000009 /* EMC_QRST */
 3180                                         0x0000000b /* EMC_QSAFE */
 3181                                         0x00000011 /* EMC_RDV */
 3182                                         0x00001820 /* EMC_REFRESH */
 3183                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 3184                                         0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
 3185                                         0x00000003 /* EMC_PDEX2WR */
 3186                                         0x00000012 /* EMC_PDEX2RD */
 3187                                         0x00000001 /* EMC_PCHG2PDEN */
 3188                                         0x00000000 /* EMC_ACT2PDEN */
 3189                                         0x0000000f /* EMC_AR2PDEN */
 3190                                         0x00000018 /* EMC_RW2PDEN */
 3191                                         0x000000d8 /* EMC_TXSR */
 3192                                         0x00000200 /* EMC_TXSRDLL */
 3193                                         0x00000005 /* EMC_TCKE */
 3194                                         0x00000020 /* EMC_TFAW */
 3195                                         0x00000000 /* EMC_TRPAB */
 3196                                         0x00000007 /* EMC_TCLKSTABLE */
 3197                                         0x00000008 /* EMC_TCLKSTOP */
 3198                                         0x00001860 /* EMC_TREFBW */
 3199                                         0x0000000b /* EMC_QUSE_EXTRA */
 3200                                         0x00000006 /* EMC_FBIO_CFG6 */
 3201                                         0x00000000 /* EMC_ODT_WRITE */
 3202                                         0x00000000 /* EMC_ODT_READ */
 3203                                         0x00005088 /* EMC_FBIO_CFG5 */
 3204                                         0xf0070191 /* EMC_CFG_DIG_DLL */
 3205                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 3206                                         0x0000800a /* EMC_DLL_XFORM_DQS0 */
 3207                                         0x0000000a /* EMC_DLL_XFORM_DQS1 */
 3208                                         0x0000000a /* EMC_DLL_XFORM_DQS2 */
 3209                                         0x0000000a /* EMC_DLL_XFORM_DQS3 */
 3210                                         0x0000000a /* EMC_DLL_XFORM_DQS4 */
 3211                                         0x0000000a /* EMC_DLL_XFORM_DQS5 */
 3212                                         0x0000000a /* EMC_DLL_XFORM_DQS6 */
 3213                                         0x0000000a /* EMC_DLL_XFORM_DQS7 */
 3214                                         0x00018000 /* EMC_DLL_XFORM_QUSE0 */
 3215                                         0x00018000 /* EMC_DLL_XFORM_QUSE1 */
 3216                                         0x00018000 /* EMC_DLL_XFORM_QUSE2 */
 3217                                         0x00018000 /* EMC_DLL_XFORM_QUSE3 */
 3218                                         0x00018000 /* EMC_DLL_XFORM_QUSE4 */
 3219                                         0x00018000 /* EMC_DLL_XFORM_QUSE5 */
 3220                                         0x00018000 /* EMC_DLL_XFORM_QUSE6 */
 3221                                         0x00018000 /* EMC_DLL_XFORM_QUSE7 */
 3222                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 3223                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 3224                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 3225                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 3226                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 3227                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 3228                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 3229                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 3230                                         0x0000000a /* EMC_DLL_XFORM_DQ0 */
 3231                                         0x0000000a /* EMC_DLL_XFORM_DQ1 */
 3232                                         0x0000000a /* EMC_DLL_XFORM_DQ2 */
 3233                                         0x0000000a /* EMC_DLL_XFORM_DQ3 */
 3234                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 3235                                         0x0600013d /* EMC_XM2DQSPADCTRL2 */
 3236                                         0x22220000 /* EMC_XM2DQPADCTRL2 */
 3237                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 3238                                         0x01f1f501 /* EMC_XM2COMPPADCTRL */
 3239                                         0x07077404 /* EMC_XM2VTTGENPADCTRL */
 3240                                         0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
 3241                                         0x080001e8 /* EMC_XM2QUSEPADCTRL */
 3242                                         0x08000021 /* EMC_XM2DQSPADCTRL3 */
 3243                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 3244                                         0x00020000 /* EMC_ZCAL_INTERVAL */
 3245                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
 3246                                         0x00f0000c /* EMC_MRS_WAIT_CNT */
 3247                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 3248                                         0x00000000 /* EMC_CTT */
 3249                                         0x00000000 /* EMC_CTT_DURATION */
 3250                                         0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
 3251                                         0xe8000000 /* EMC_FBIO_SPARE */
 3252                                         0xff00ff49 /* EMC_CFG_RSV */
 3253                                 >;
 3254                         };
 3255                 };
 3256 
 3257                 emc-timings-1 {
 3258                         nvidia,ram-code = <1>;  /* Hynix M RAM */
 3259 
 3260                         timing-25500000 {
 3261                                 clock-frequency = <25500000>;
 3262                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 3263                                 nvidia,emc-mode-1 = <0x80100003>;
 3264                                 nvidia,emc-mode-2 = <0x80200008>;
 3265                                 nvidia,emc-mode-reset = <0x80001221>;
 3266                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 3267                                 nvidia,emc-cfg-periodic-qrst;
 3268                                 nvidia,emc-cfg-dyn-self-ref;
 3269                                 nvidia,emc-configuration = <
 3270                                         0x00000001 /* EMC_RC */
 3271                                         0x00000006 /* EMC_RFC */
 3272                                         0x00000000 /* EMC_RAS */
 3273                                         0x00000000 /* EMC_RP */
 3274                                         0x00000002 /* EMC_R2W */
 3275                                         0x0000000a /* EMC_W2R */
 3276                                         0x00000005 /* EMC_R2P */
 3277                                         0x0000000b /* EMC_W2P */
 3278                                         0x00000000 /* EMC_RD_RCD */
 3279                                         0x00000000 /* EMC_WR_RCD */
 3280                                         0x00000003 /* EMC_RRD */
 3281                                         0x00000001 /* EMC_REXT */
 3282                                         0x00000000 /* EMC_WEXT */
 3283                                         0x00000005 /* EMC_WDV */
 3284                                         0x00000005 /* EMC_QUSE */
 3285                                         0x00000004 /* EMC_QRST */
 3286                                         0x0000000a /* EMC_QSAFE */
 3287                                         0x0000000b /* EMC_RDV */
 3288                                         0x000000c0 /* EMC_REFRESH */
 3289                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 3290                                         0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
 3291                                         0x00000002 /* EMC_PDEX2WR */
 3292                                         0x00000002 /* EMC_PDEX2RD */
 3293                                         0x00000001 /* EMC_PCHG2PDEN */
 3294                                         0x00000000 /* EMC_ACT2PDEN */
 3295                                         0x00000007 /* EMC_AR2PDEN */
 3296                                         0x0000000f /* EMC_RW2PDEN */
 3297                                         0x00000007 /* EMC_TXSR */
 3298                                         0x00000007 /* EMC_TXSRDLL */
 3299                                         0x00000004 /* EMC_TCKE */
 3300                                         0x00000002 /* EMC_TFAW */
 3301                                         0x00000000 /* EMC_TRPAB */
 3302                                         0x00000004 /* EMC_TCLKSTABLE */
 3303                                         0x00000005 /* EMC_TCLKSTOP */
 3304                                         0x000000c7 /* EMC_TREFBW */
 3305                                         0x00000006 /* EMC_QUSE_EXTRA */
 3306                                         0x00000004 /* EMC_FBIO_CFG6 */
 3307                                         0x00000000 /* EMC_ODT_WRITE */
 3308                                         0x00000000 /* EMC_ODT_READ */
 3309                                         0x00004288 /* EMC_FBIO_CFG5 */
 3310                                         0x007800a4 /* EMC_CFG_DIG_DLL */
 3311                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 3312                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
 3313                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
 3314                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
 3315                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
 3316                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
 3317                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
 3318                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
 3319                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
 3320                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 3321                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 3322                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 3323                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 3324                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 3325                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 3326                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 3327                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 3328                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 3329                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 3330                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 3331                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 3332                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 3333                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 3334                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 3335                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 3336                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
 3337                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
 3338                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
 3339                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
 3340                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 3341                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
 3342                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
 3343                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 3344                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
 3345                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
 3346                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
 3347                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
 3348                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
 3349                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 3350                                         0x00000000 /* EMC_ZCAL_INTERVAL */
 3351                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
 3352                                         0x000c000c /* EMC_MRS_WAIT_CNT */
 3353                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 3354                                         0x00000000 /* EMC_CTT */
 3355                                         0x00000000 /* EMC_CTT_DURATION */
 3356                                         0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
 3357                                         0xe8000000 /* EMC_FBIO_SPARE */
 3358                                         0xff00ff00 /* EMC_CFG_RSV */
 3359                                 >;
 3360                         };
 3361 
 3362                         timing-51000000 {
 3363                                 clock-frequency = <51000000>;
 3364                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 3365                                 nvidia,emc-mode-1 = <0x80100003>;
 3366                                 nvidia,emc-mode-2 = <0x80200008>;
 3367                                 nvidia,emc-mode-reset = <0x80001221>;
 3368                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 3369                                 nvidia,emc-cfg-periodic-qrst;
 3370                                 nvidia,emc-cfg-dyn-self-ref;
 3371                                 nvidia,emc-configuration = <
 3372                                         0x00000002 /* EMC_RC */
 3373                                         0x0000000d /* EMC_RFC */
 3374                                         0x00000001 /* EMC_RAS */
 3375                                         0x00000000 /* EMC_RP */
 3376                                         0x00000002 /* EMC_R2W */
 3377                                         0x0000000a /* EMC_W2R */
 3378                                         0x00000005 /* EMC_R2P */
 3379                                         0x0000000b /* EMC_W2P */
 3380                                         0x00000000 /* EMC_RD_RCD */
 3381                                         0x00000000 /* EMC_WR_RCD */
 3382                                         0x00000003 /* EMC_RRD */
 3383                                         0x00000001 /* EMC_REXT */
 3384                                         0x00000000 /* EMC_WEXT */
 3385                                         0x00000005 /* EMC_WDV */
 3386                                         0x00000005 /* EMC_QUSE */
 3387                                         0x00000004 /* EMC_QRST */
 3388                                         0x0000000a /* EMC_QSAFE */
 3389                                         0x0000000b /* EMC_RDV */
 3390                                         0x00000181 /* EMC_REFRESH */
 3391                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 3392                                         0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
 3393                                         0x00000002 /* EMC_PDEX2WR */
 3394                                         0x00000002 /* EMC_PDEX2RD */
 3395                                         0x00000001 /* EMC_PCHG2PDEN */
 3396                                         0x00000000 /* EMC_ACT2PDEN */
 3397                                         0x00000007 /* EMC_AR2PDEN */
 3398                                         0x0000000f /* EMC_RW2PDEN */
 3399                                         0x0000000e /* EMC_TXSR */
 3400                                         0x0000000e /* EMC_TXSRDLL */
 3401                                         0x00000004 /* EMC_TCKE */
 3402                                         0x00000003 /* EMC_TFAW */
 3403                                         0x00000000 /* EMC_TRPAB */
 3404                                         0x00000004 /* EMC_TCLKSTABLE */
 3405                                         0x00000005 /* EMC_TCLKSTOP */
 3406                                         0x0000018e /* EMC_TREFBW */
 3407                                         0x00000006 /* EMC_QUSE_EXTRA */
 3408                                         0x00000004 /* EMC_FBIO_CFG6 */
 3409                                         0x00000000 /* EMC_ODT_WRITE */
 3410                                         0x00000000 /* EMC_ODT_READ */
 3411                                         0x00004288 /* EMC_FBIO_CFG5 */
 3412                                         0x007800a4 /* EMC_CFG_DIG_DLL */
 3413                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 3414                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
 3415                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
 3416                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
 3417                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
 3418                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
 3419                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
 3420                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
 3421                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
 3422                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 3423                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 3424                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 3425                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 3426                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 3427                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 3428                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 3429                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 3430                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 3431                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 3432                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 3433                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 3434                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 3435                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 3436                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 3437                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 3438                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
 3439                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
 3440                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
 3441                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
 3442                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 3443                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
 3444                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
 3445                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 3446                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
 3447                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
 3448                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
 3449                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
 3450                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
 3451                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 3452                                         0x00000000 /* EMC_ZCAL_INTERVAL */
 3453                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
 3454                                         0x000c000c /* EMC_MRS_WAIT_CNT */
 3455                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 3456                                         0x00000000 /* EMC_CTT */
 3457                                         0x00000000 /* EMC_CTT_DURATION */
 3458                                         0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
 3459                                         0xe8000000 /* EMC_FBIO_SPARE */
 3460                                         0xff00ff00 /* EMC_CFG_RSV */
 3461                                 >;
 3462                         };
 3463 
 3464                         timing-102000000 {
 3465                                 clock-frequency = <102000000>;
 3466                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 3467                                 nvidia,emc-mode-1 = <0x80100003>;
 3468                                 nvidia,emc-mode-2 = <0x80200008>;
 3469                                 nvidia,emc-mode-reset = <0x80001221>;
 3470                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 3471                                 nvidia,emc-cfg-periodic-qrst;
 3472                                 nvidia,emc-cfg-dyn-self-ref;
 3473                                 nvidia,emc-configuration = <
 3474                                         0x00000004 /* EMC_RC */
 3475                                         0x0000001a /* EMC_RFC */
 3476                                         0x00000003 /* EMC_RAS */
 3477                                         0x00000001 /* EMC_RP */
 3478                                         0x00000002 /* EMC_R2W */
 3479                                         0x0000000a /* EMC_W2R */
 3480                                         0x00000005 /* EMC_R2P */
 3481                                         0x0000000b /* EMC_W2P */
 3482                                         0x00000001 /* EMC_RD_RCD */
 3483                                         0x00000001 /* EMC_WR_RCD */
 3484                                         0x00000003 /* EMC_RRD */
 3485                                         0x00000001 /* EMC_REXT */
 3486                                         0x00000000 /* EMC_WEXT */
 3487                                         0x00000005 /* EMC_WDV */
 3488                                         0x00000005 /* EMC_QUSE */
 3489                                         0x00000004 /* EMC_QRST */
 3490                                         0x0000000a /* EMC_QSAFE */
 3491                                         0x0000000b /* EMC_RDV */
 3492                                         0x00000303 /* EMC_REFRESH */
 3493                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 3494                                         0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
 3495                                         0x00000002 /* EMC_PDEX2WR */
 3496                                         0x00000002 /* EMC_PDEX2RD */
 3497                                         0x00000001 /* EMC_PCHG2PDEN */
 3498                                         0x00000000 /* EMC_ACT2PDEN */
 3499                                         0x00000007 /* EMC_AR2PDEN */
 3500                                         0x0000000f /* EMC_RW2PDEN */
 3501                                         0x0000001c /* EMC_TXSR */
 3502                                         0x0000001c /* EMC_TXSRDLL */
 3503                                         0x00000004 /* EMC_TCKE */
 3504                                         0x00000005 /* EMC_TFAW */
 3505                                         0x00000000 /* EMC_TRPAB */
 3506                                         0x00000004 /* EMC_TCLKSTABLE */
 3507                                         0x00000005 /* EMC_TCLKSTOP */
 3508                                         0x0000031c /* EMC_TREFBW */
 3509                                         0x00000006 /* EMC_QUSE_EXTRA */
 3510                                         0x00000004 /* EMC_FBIO_CFG6 */
 3511                                         0x00000000 /* EMC_ODT_WRITE */
 3512                                         0x00000000 /* EMC_ODT_READ */
 3513                                         0x00004288 /* EMC_FBIO_CFG5 */
 3514                                         0x007800a4 /* EMC_CFG_DIG_DLL */
 3515                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 3516                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
 3517                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
 3518                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
 3519                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
 3520                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
 3521                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
 3522                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
 3523                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
 3524                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 3525                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 3526                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 3527                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 3528                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 3529                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 3530                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 3531                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 3532                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 3533                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 3534                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 3535                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 3536                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 3537                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 3538                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 3539                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 3540                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
 3541                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
 3542                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
 3543                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
 3544                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 3545                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
 3546                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
 3547                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 3548                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
 3549                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
 3550                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
 3551                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
 3552                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
 3553                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 3554                                         0x00000000 /* EMC_ZCAL_INTERVAL */
 3555                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
 3556                                         0x000c000c /* EMC_MRS_WAIT_CNT */
 3557                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 3558                                         0x00000000 /* EMC_CTT */
 3559                                         0x00000000 /* EMC_CTT_DURATION */
 3560                                         0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
 3561                                         0xe8000000 /* EMC_FBIO_SPARE */
 3562                                         0xff00ff00 /* EMC_CFG_RSV */
 3563                                 >;
 3564                         };
 3565 
 3566                         timing-204000000 {
 3567                                 clock-frequency = <204000000>;
 3568                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 3569                                 nvidia,emc-mode-1 = <0x80100003>;
 3570                                 nvidia,emc-mode-2 = <0x80200008>;
 3571                                 nvidia,emc-mode-reset = <0x80001221>;
 3572                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 3573                                 nvidia,emc-cfg-periodic-qrst;
 3574                                 nvidia,emc-cfg-dyn-self-ref;
 3575                                 nvidia,emc-configuration = <
 3576                                         0x00000009 /* EMC_RC */
 3577                                         0x00000035 /* EMC_RFC */
 3578                                         0x00000007 /* EMC_RAS */
 3579                                         0x00000002 /* EMC_RP */
 3580                                         0x00000002 /* EMC_R2W */
 3581                                         0x0000000a /* EMC_W2R */
 3582                                         0x00000005 /* EMC_R2P */
 3583                                         0x0000000b /* EMC_W2P */
 3584                                         0x00000002 /* EMC_RD_RCD */
 3585                                         0x00000002 /* EMC_WR_RCD */
 3586                                         0x00000003 /* EMC_RRD */
 3587                                         0x00000001 /* EMC_REXT */
 3588                                         0x00000000 /* EMC_WEXT */
 3589                                         0x00000005 /* EMC_WDV */
 3590                                         0x00000005 /* EMC_QUSE */
 3591                                         0x00000004 /* EMC_QRST */
 3592                                         0x0000000a /* EMC_QSAFE */
 3593                                         0x0000000b /* EMC_RDV */
 3594                                         0x00000607 /* EMC_REFRESH */
 3595                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 3596                                         0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
 3597                                         0x00000002 /* EMC_PDEX2WR */
 3598                                         0x00000002 /* EMC_PDEX2RD */
 3599                                         0x00000001 /* EMC_PCHG2PDEN */
 3600                                         0x00000000 /* EMC_ACT2PDEN */
 3601                                         0x00000007 /* EMC_AR2PDEN */
 3602                                         0x0000000f /* EMC_RW2PDEN */
 3603                                         0x00000038 /* EMC_TXSR */
 3604                                         0x00000038 /* EMC_TXSRDLL */
 3605                                         0x00000004 /* EMC_TCKE */
 3606                                         0x00000009 /* EMC_TFAW */
 3607                                         0x00000000 /* EMC_TRPAB */
 3608                                         0x00000004 /* EMC_TCLKSTABLE */
 3609                                         0x00000005 /* EMC_TCLKSTOP */
 3610                                         0x00000638 /* EMC_TREFBW */
 3611                                         0x00000006 /* EMC_QUSE_EXTRA */
 3612                                         0x00000006 /* EMC_FBIO_CFG6 */
 3613                                         0x00000000 /* EMC_ODT_WRITE */
 3614                                         0x00000000 /* EMC_ODT_READ */
 3615                                         0x00004288 /* EMC_FBIO_CFG5 */
 3616                                         0x004400a4 /* EMC_CFG_DIG_DLL */
 3617                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 3618                                         0x00080000 /* EMC_DLL_XFORM_DQS0 */
 3619                                         0x00080000 /* EMC_DLL_XFORM_DQS1 */
 3620                                         0x00080000 /* EMC_DLL_XFORM_DQS2 */
 3621                                         0x00080000 /* EMC_DLL_XFORM_DQS3 */
 3622                                         0x00080000 /* EMC_DLL_XFORM_DQS4 */
 3623                                         0x00080000 /* EMC_DLL_XFORM_DQS5 */
 3624                                         0x00080000 /* EMC_DLL_XFORM_DQS6 */
 3625                                         0x00080000 /* EMC_DLL_XFORM_DQS7 */
 3626                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 3627                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 3628                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 3629                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 3630                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 3631                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 3632                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 3633                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 3634                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 3635                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 3636                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 3637                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 3638                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 3639                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 3640                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 3641                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 3642                                         0x00080000 /* EMC_DLL_XFORM_DQ0 */
 3643                                         0x00080000 /* EMC_DLL_XFORM_DQ1 */
 3644                                         0x00080000 /* EMC_DLL_XFORM_DQ2 */
 3645                                         0x00080000 /* EMC_DLL_XFORM_DQ3 */
 3646                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 3647                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
 3648                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
 3649                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 3650                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
 3651                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
 3652                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
 3653                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
 3654                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
 3655                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 3656                                         0x00020000 /* EMC_ZCAL_INTERVAL */
 3657                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
 3658                                         0x000c000c /* EMC_MRS_WAIT_CNT */
 3659                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 3660                                         0x00000000 /* EMC_CTT */
 3661                                         0x00000000 /* EMC_CTT_DURATION */
 3662                                         0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
 3663                                         0xe8000000 /* EMC_FBIO_SPARE */
 3664                                         0xff00ff00 /* EMC_CFG_RSV */
 3665                                 >;
 3666                         };
 3667 
 3668                         timing-400000000 {
 3669                                 clock-frequency = <400000000>;
 3670                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 3671                                 nvidia,emc-mode-1 = <0x80100002>;
 3672                                 nvidia,emc-mode-2 = <0x80200000>;
 3673                                 nvidia,emc-mode-reset = <0x80000521>;
 3674                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 3675                                 nvidia,emc-configuration = <
 3676                                         0x00000012 /* EMC_RC */
 3677                                         0x00000066 /* EMC_RFC */
 3678                                         0x0000000c /* EMC_RAS */
 3679                                         0x00000004 /* EMC_RP */
 3680                                         0x00000003 /* EMC_R2W */
 3681                                         0x00000008 /* EMC_W2R */
 3682                                         0x00000002 /* EMC_R2P */
 3683                                         0x0000000a /* EMC_W2P */
 3684                                         0x00000004 /* EMC_RD_RCD */
 3685                                         0x00000004 /* EMC_WR_RCD */
 3686                                         0x00000002 /* EMC_RRD */
 3687                                         0x00000001 /* EMC_REXT */
 3688                                         0x00000000 /* EMC_WEXT */
 3689                                         0x00000004 /* EMC_WDV */
 3690                                         0x00000006 /* EMC_QUSE */
 3691                                         0x00000004 /* EMC_QRST */
 3692                                         0x0000000a /* EMC_QSAFE */
 3693                                         0x0000000c /* EMC_RDV */
 3694                                         0x00000bf0 /* EMC_REFRESH */
 3695                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 3696                                         0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
 3697                                         0x00000001 /* EMC_PDEX2WR */
 3698                                         0x00000008 /* EMC_PDEX2RD */
 3699                                         0x00000001 /* EMC_PCHG2PDEN */
 3700                                         0x00000000 /* EMC_ACT2PDEN */
 3701                                         0x00000008 /* EMC_AR2PDEN */
 3702                                         0x0000000f /* EMC_RW2PDEN */
 3703                                         0x0000006c /* EMC_TXSR */
 3704                                         0x00000200 /* EMC_TXSRDLL */
 3705                                         0x00000004 /* EMC_TCKE */
 3706                                         0x00000010 /* EMC_TFAW */
 3707                                         0x00000000 /* EMC_TRPAB */
 3708                                         0x00000004 /* EMC_TCLKSTABLE */
 3709                                         0x00000005 /* EMC_TCLKSTOP */
 3710                                         0x00000c30 /* EMC_TREFBW */
 3711                                         0x00000000 /* EMC_QUSE_EXTRA */
 3712                                         0x00000004 /* EMC_FBIO_CFG6 */
 3713                                         0x00000000 /* EMC_ODT_WRITE */
 3714                                         0x00000000 /* EMC_ODT_READ */
 3715                                         0x00007088 /* EMC_FBIO_CFG5 */
 3716                                         0x001d0084 /* EMC_CFG_DIG_DLL */
 3717                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 3718                                         0x0003c000 /* EMC_DLL_XFORM_DQS0 */
 3719                                         0x0003c000 /* EMC_DLL_XFORM_DQS1 */
 3720                                         0x0003c000 /* EMC_DLL_XFORM_DQS2 */
 3721                                         0x0003c000 /* EMC_DLL_XFORM_DQS3 */
 3722                                         0x0003c000 /* EMC_DLL_XFORM_DQS4 */
 3723                                         0x0003c000 /* EMC_DLL_XFORM_DQS5 */
 3724                                         0x0003c000 /* EMC_DLL_XFORM_DQS6 */
 3725                                         0x0003c000 /* EMC_DLL_XFORM_DQS7 */
 3726                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 3727                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 3728                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 3729                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 3730                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 3731                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 3732                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 3733                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 3734                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 3735                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 3736                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 3737                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 3738                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 3739                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 3740                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 3741                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 3742                                         0x00048000 /* EMC_DLL_XFORM_DQ0 */
 3743                                         0x00048000 /* EMC_DLL_XFORM_DQ1 */
 3744                                         0x00048000 /* EMC_DLL_XFORM_DQ2 */
 3745                                         0x00048000 /* EMC_DLL_XFORM_DQ3 */
 3746                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 3747                                         0x0800013d /* EMC_XM2DQSPADCTRL2 */
 3748                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
 3749                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 3750                                         0x01f1f508 /* EMC_XM2COMPPADCTRL */
 3751                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
 3752                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
 3753                                         0x080001e8 /* EMC_XM2QUSEPADCTRL */
 3754                                         0x08000021 /* EMC_XM2DQSPADCTRL3 */
 3755                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 3756                                         0x00020000 /* EMC_ZCAL_INTERVAL */
 3757                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
 3758                                         0x0158000c /* EMC_MRS_WAIT_CNT */
 3759                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 3760                                         0x00000000 /* EMC_CTT */
 3761                                         0x00000000 /* EMC_CTT_DURATION */
 3762                                         0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
 3763                                         0xe8000000 /* EMC_FBIO_SPARE */
 3764                                         0xff00ff89 /* EMC_CFG_RSV */
 3765                                 >;
 3766                         };
 3767 
 3768                         timing-800000000 {
 3769                                 clock-frequency = <800000000>;
 3770                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 3771                                 nvidia,emc-mode-1 = <0x80100002>;
 3772                                 nvidia,emc-mode-2 = <0x80200018>;
 3773                                 nvidia,emc-mode-reset = <0x80000d71>;
 3774                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 3775                                 nvidia,emc-cfg-periodic-qrst;
 3776                                 nvidia,emc-configuration = <
 3777                                         0x00000025 /* EMC_RC */
 3778                                         0x000000ce /* EMC_RFC */
 3779                                         0x0000001a /* EMC_RAS */
 3780                                         0x00000009 /* EMC_RP */
 3781                                         0x00000005 /* EMC_R2W */
 3782                                         0x0000000d /* EMC_W2R */
 3783                                         0x00000004 /* EMC_R2P */
 3784                                         0x00000013 /* EMC_W2P */
 3785                                         0x00000009 /* EMC_RD_RCD */
 3786                                         0x00000009 /* EMC_WR_RCD */
 3787                                         0x00000004 /* EMC_RRD */
 3788                                         0x00000001 /* EMC_REXT */
 3789                                         0x00000000 /* EMC_WEXT */
 3790                                         0x00000007 /* EMC_WDV */
 3791                                         0x0000000a /* EMC_QUSE */
 3792                                         0x00000009 /* EMC_QRST */
 3793                                         0x0000000b /* EMC_QSAFE */
 3794                                         0x00000011 /* EMC_RDV */
 3795                                         0x00001820 /* EMC_REFRESH */
 3796                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 3797                                         0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
 3798                                         0x00000003 /* EMC_PDEX2WR */
 3799                                         0x00000012 /* EMC_PDEX2RD */
 3800                                         0x00000001 /* EMC_PCHG2PDEN */
 3801                                         0x00000000 /* EMC_ACT2PDEN */
 3802                                         0x0000000f /* EMC_AR2PDEN */
 3803                                         0x00000018 /* EMC_RW2PDEN */
 3804                                         0x000000d8 /* EMC_TXSR */
 3805                                         0x00000200 /* EMC_TXSRDLL */
 3806                                         0x00000005 /* EMC_TCKE */
 3807                                         0x00000020 /* EMC_TFAW */
 3808                                         0x00000000 /* EMC_TRPAB */
 3809                                         0x00000007 /* EMC_TCLKSTABLE */
 3810                                         0x00000008 /* EMC_TCLKSTOP */
 3811                                         0x00001860 /* EMC_TREFBW */
 3812                                         0x0000000b /* EMC_QUSE_EXTRA */
 3813                                         0x00000006 /* EMC_FBIO_CFG6 */
 3814                                         0x00000000 /* EMC_ODT_WRITE */
 3815                                         0x00000000 /* EMC_ODT_READ */
 3816                                         0x00005088 /* EMC_FBIO_CFG5 */
 3817                                         0xf0070191 /* EMC_CFG_DIG_DLL */
 3818                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 3819                                         0x0000800a /* EMC_DLL_XFORM_DQS0 */
 3820                                         0x0000000a /* EMC_DLL_XFORM_DQS1 */
 3821                                         0x0000000a /* EMC_DLL_XFORM_DQS2 */
 3822                                         0x0000000a /* EMC_DLL_XFORM_DQS3 */
 3823                                         0x0000000a /* EMC_DLL_XFORM_DQS4 */
 3824                                         0x0000000a /* EMC_DLL_XFORM_DQS5 */
 3825                                         0x0000000a /* EMC_DLL_XFORM_DQS6 */
 3826                                         0x0000000a /* EMC_DLL_XFORM_DQS7 */
 3827                                         0x00018000 /* EMC_DLL_XFORM_QUSE0 */
 3828                                         0x00018000 /* EMC_DLL_XFORM_QUSE1 */
 3829                                         0x00018000 /* EMC_DLL_XFORM_QUSE2 */
 3830                                         0x00018000 /* EMC_DLL_XFORM_QUSE3 */
 3831                                         0x00018000 /* EMC_DLL_XFORM_QUSE4 */
 3832                                         0x00018000 /* EMC_DLL_XFORM_QUSE5 */
 3833                                         0x00018000 /* EMC_DLL_XFORM_QUSE6 */
 3834                                         0x00018000 /* EMC_DLL_XFORM_QUSE7 */
 3835                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 3836                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 3837                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 3838                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 3839                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 3840                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 3841                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 3842                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 3843                                         0x0000000a /* EMC_DLL_XFORM_DQ0 */
 3844                                         0x0000000a /* EMC_DLL_XFORM_DQ1 */
 3845                                         0x0000000a /* EMC_DLL_XFORM_DQ2 */
 3846                                         0x0000000a /* EMC_DLL_XFORM_DQ3 */
 3847                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 3848                                         0x0600013d /* EMC_XM2DQSPADCTRL2 */
 3849                                         0x22220000 /* EMC_XM2DQPADCTRL2 */
 3850                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 3851                                         0x01f1f501 /* EMC_XM2COMPPADCTRL */
 3852                                         0x07077404 /* EMC_XM2VTTGENPADCTRL */
 3853                                         0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
 3854                                         0x080001e8 /* EMC_XM2QUSEPADCTRL */
 3855                                         0x08000021 /* EMC_XM2DQSPADCTRL3 */
 3856                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 3857                                         0x00020000 /* EMC_ZCAL_INTERVAL */
 3858                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
 3859                                         0x00f0000c /* EMC_MRS_WAIT_CNT */
 3860                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 3861                                         0x00000000 /* EMC_CTT */
 3862                                         0x00000000 /* EMC_CTT_DURATION */
 3863                                         0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
 3864                                         0xe8000000 /* EMC_FBIO_SPARE */
 3865                                         0xff00ff49 /* EMC_CFG_RSV */
 3866                                 >;
 3867                         };
 3868                 };
 3869 
 3870                 emc-timings-2 {
 3871                         nvidia,ram-code = <2>;  /* Hynix A RAM */
 3872 
 3873                         timing-25500000 {
 3874                                 clock-frequency = <25500000>;
 3875                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 3876                                 nvidia,emc-mode-1 = <0x80100003>;
 3877                                 nvidia,emc-mode-2 = <0x80200008>;
 3878                                 nvidia,emc-mode-reset = <0x80001221>;
 3879                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 3880                                 nvidia,emc-cfg-periodic-qrst;
 3881                                 nvidia,emc-cfg-dyn-self-ref;
 3882                                 nvidia,emc-configuration = <
 3883                                         0x00000001 /* EMC_RC */
 3884                                         0x00000007 /* EMC_RFC */
 3885                                         0x00000000 /* EMC_RAS */
 3886                                         0x00000000 /* EMC_RP */
 3887                                         0x00000002 /* EMC_R2W */
 3888                                         0x0000000a /* EMC_W2R */
 3889                                         0x00000005 /* EMC_R2P */
 3890                                         0x0000000b /* EMC_W2P */
 3891                                         0x00000000 /* EMC_RD_RCD */
 3892                                         0x00000000 /* EMC_WR_RCD */
 3893                                         0x00000003 /* EMC_RRD */
 3894                                         0x00000001 /* EMC_REXT */
 3895                                         0x00000000 /* EMC_WEXT */
 3896                                         0x00000005 /* EMC_WDV */
 3897                                         0x00000005 /* EMC_QUSE */
 3898                                         0x00000004 /* EMC_QRST */
 3899                                         0x0000000a /* EMC_QSAFE */
 3900                                         0x0000000b /* EMC_RDV */
 3901                                         0x000000c0 /* EMC_REFRESH */
 3902                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 3903                                         0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */
 3904                                         0x00000002 /* EMC_PDEX2WR */
 3905                                         0x00000002 /* EMC_PDEX2RD */
 3906                                         0x00000001 /* EMC_PCHG2PDEN */
 3907                                         0x00000000 /* EMC_ACT2PDEN */
 3908                                         0x00000007 /* EMC_AR2PDEN */
 3909                                         0x0000000f /* EMC_RW2PDEN */
 3910                                         0x00000008 /* EMC_TXSR */
 3911                                         0x00000008 /* EMC_TXSRDLL */
 3912                                         0x00000004 /* EMC_TCKE */
 3913                                         0x00000002 /* EMC_TFAW */
 3914                                         0x00000000 /* EMC_TRPAB */
 3915                                         0x00000004 /* EMC_TCLKSTABLE */
 3916                                         0x00000005 /* EMC_TCLKSTOP */
 3917                                         0x000000c7 /* EMC_TREFBW */
 3918                                         0x00000006 /* EMC_QUSE_EXTRA */
 3919                                         0x00000004 /* EMC_FBIO_CFG6 */
 3920                                         0x00000000 /* EMC_ODT_WRITE */
 3921                                         0x00000000 /* EMC_ODT_READ */
 3922                                         0x00004288 /* EMC_FBIO_CFG5 */
 3923                                         0x007800a4 /* EMC_CFG_DIG_DLL */
 3924                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 3925                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
 3926                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
 3927                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
 3928                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
 3929                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
 3930                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
 3931                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
 3932                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
 3933                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 3934                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 3935                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 3936                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 3937                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 3938                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 3939                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 3940                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 3941                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 3942                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 3943                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 3944                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 3945                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 3946                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 3947                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 3948                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 3949                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
 3950                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
 3951                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
 3952                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
 3953                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 3954                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
 3955                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
 3956                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 3957                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
 3958                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
 3959                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
 3960                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
 3961                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
 3962                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 3963                                         0x00000000 /* EMC_ZCAL_INTERVAL */
 3964                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
 3965                                         0x000c000c /* EMC_MRS_WAIT_CNT */
 3966                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 3967                                         0x00000000 /* EMC_CTT */
 3968                                         0x00000000 /* EMC_CTT_DURATION */
 3969                                         0x80000287 /* EMC_DYN_SELF_REF_CONTROL */
 3970                                         0xe8000000 /* EMC_FBIO_SPARE */
 3971                                         0xff00ff00 /* EMC_CFG_RSV */
 3972                                 >;
 3973                         };
 3974 
 3975                         timing-51000000 {
 3976                                 clock-frequency = <51000000>;
 3977                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 3978                                 nvidia,emc-mode-1 = <0x80100003>;
 3979                                 nvidia,emc-mode-2 = <0x80200008>;
 3980                                 nvidia,emc-mode-reset = <0x80001221>;
 3981                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 3982                                 nvidia,emc-cfg-periodic-qrst;
 3983                                 nvidia,emc-cfg-dyn-self-ref;
 3984                                 nvidia,emc-configuration = <
 3985                                         0x00000002 /* EMC_RC */
 3986                                         0x0000000f /* EMC_RFC */
 3987                                         0x00000001 /* EMC_RAS */
 3988                                         0x00000000 /* EMC_RP */
 3989                                         0x00000002 /* EMC_R2W */
 3990                                         0x0000000a /* EMC_W2R */
 3991                                         0x00000005 /* EMC_R2P */
 3992                                         0x0000000b /* EMC_W2P */
 3993                                         0x00000000 /* EMC_RD_RCD */
 3994                                         0x00000000 /* EMC_WR_RCD */
 3995                                         0x00000003 /* EMC_RRD */
 3996                                         0x00000001 /* EMC_REXT */
 3997                                         0x00000000 /* EMC_WEXT */
 3998                                         0x00000005 /* EMC_WDV */
 3999                                         0x00000005 /* EMC_QUSE */
 4000                                         0x00000004 /* EMC_QRST */
 4001                                         0x0000000a /* EMC_QSAFE */
 4002                                         0x0000000b /* EMC_RDV */
 4003                                         0x00000181 /* EMC_REFRESH */
 4004                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 4005                                         0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */
 4006                                         0x00000002 /* EMC_PDEX2WR */
 4007                                         0x00000002 /* EMC_PDEX2RD */
 4008                                         0x00000001 /* EMC_PCHG2PDEN */
 4009                                         0x00000000 /* EMC_ACT2PDEN */
 4010                                         0x00000007 /* EMC_AR2PDEN */
 4011                                         0x0000000f /* EMC_RW2PDEN */
 4012                                         0x00000010 /* EMC_TXSR */
 4013                                         0x00000010 /* EMC_TXSRDLL */
 4014                                         0x00000004 /* EMC_TCKE */
 4015                                         0x00000003 /* EMC_TFAW */
 4016                                         0x00000000 /* EMC_TRPAB */
 4017                                         0x00000004 /* EMC_TCLKSTABLE */
 4018                                         0x00000005 /* EMC_TCLKSTOP */
 4019                                         0x0000018e /* EMC_TREFBW */
 4020                                         0x00000006 /* EMC_QUSE_EXTRA */
 4021                                         0x00000004 /* EMC_FBIO_CFG6 */
 4022                                         0x00000000 /* EMC_ODT_WRITE */
 4023                                         0x00000000 /* EMC_ODT_READ */
 4024                                         0x00004288 /* EMC_FBIO_CFG5 */
 4025                                         0x007800a4 /* EMC_CFG_DIG_DLL */
 4026                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 4027                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
 4028                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
 4029                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
 4030                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
 4031                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
 4032                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
 4033                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
 4034                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
 4035                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 4036                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 4037                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 4038                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 4039                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 4040                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 4041                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 4042                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 4043                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 4044                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 4045                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 4046                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 4047                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 4048                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 4049                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 4050                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 4051                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
 4052                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
 4053                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
 4054                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
 4055                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 4056                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
 4057                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
 4058                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 4059                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
 4060                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
 4061                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
 4062                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
 4063                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
 4064                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 4065                                         0x00000000 /* EMC_ZCAL_INTERVAL */
 4066                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
 4067                                         0x000c000c /* EMC_MRS_WAIT_CNT */
 4068                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 4069                                         0x00000000 /* EMC_CTT */
 4070                                         0x00000000 /* EMC_CTT_DURATION */
 4071                                         0x8000040b /* EMC_DYN_SELF_REF_CONTROL */
 4072                                         0xe8000000 /* EMC_FBIO_SPARE */
 4073                                         0xff00ff00 /* EMC_CFG_RSV */
 4074                                 >;
 4075                         };
 4076 
 4077                         timing-102000000 {
 4078                                 clock-frequency = <102000000>;
 4079                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 4080                                 nvidia,emc-mode-1 = <0x80100003>;
 4081                                 nvidia,emc-mode-2 = <0x80200008>;
 4082                                 nvidia,emc-mode-reset = <0x80001221>;
 4083                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 4084                                 nvidia,emc-cfg-periodic-qrst;
 4085                                 nvidia,emc-cfg-dyn-self-ref;
 4086                                 nvidia,emc-configuration = <
 4087                                         0x00000004 /* EMC_RC */
 4088                                         0x0000001e /* EMC_RFC */
 4089                                         0x00000003 /* EMC_RAS */
 4090                                         0x00000001 /* EMC_RP */
 4091                                         0x00000002 /* EMC_R2W */
 4092                                         0x0000000a /* EMC_W2R */
 4093                                         0x00000005 /* EMC_R2P */
 4094                                         0x0000000b /* EMC_W2P */
 4095                                         0x00000001 /* EMC_RD_RCD */
 4096                                         0x00000001 /* EMC_WR_RCD */
 4097                                         0x00000003 /* EMC_RRD */
 4098                                         0x00000001 /* EMC_REXT */
 4099                                         0x00000000 /* EMC_WEXT */
 4100                                         0x00000005 /* EMC_WDV */
 4101                                         0x00000005 /* EMC_QUSE */
 4102                                         0x00000004 /* EMC_QRST */
 4103                                         0x0000000a /* EMC_QSAFE */
 4104                                         0x0000000b /* EMC_RDV */
 4105                                         0x00000303 /* EMC_REFRESH */
 4106                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 4107                                         0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */
 4108                                         0x00000002 /* EMC_PDEX2WR */
 4109                                         0x00000002 /* EMC_PDEX2RD */
 4110                                         0x00000001 /* EMC_PCHG2PDEN */
 4111                                         0x00000000 /* EMC_ACT2PDEN */
 4112                                         0x00000007 /* EMC_AR2PDEN */
 4113                                         0x0000000f /* EMC_RW2PDEN */
 4114                                         0x00000020 /* EMC_TXSR */
 4115                                         0x00000020 /* EMC_TXSRDLL */
 4116                                         0x00000004 /* EMC_TCKE */
 4117                                         0x00000005 /* EMC_TFAW */
 4118                                         0x00000000 /* EMC_TRPAB */
 4119                                         0x00000004 /* EMC_TCLKSTABLE */
 4120                                         0x00000005 /* EMC_TCLKSTOP */
 4121                                         0x0000031c /* EMC_TREFBW */
 4122                                         0x00000006 /* EMC_QUSE_EXTRA */
 4123                                         0x00000004 /* EMC_FBIO_CFG6 */
 4124                                         0x00000000 /* EMC_ODT_WRITE */
 4125                                         0x00000000 /* EMC_ODT_READ */
 4126                                         0x00004288 /* EMC_FBIO_CFG5 */
 4127                                         0x007800a4 /* EMC_CFG_DIG_DLL */
 4128                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 4129                                         0x000fc000 /* EMC_DLL_XFORM_DQS0 */
 4130                                         0x000fc000 /* EMC_DLL_XFORM_DQS1 */
 4131                                         0x000fc000 /* EMC_DLL_XFORM_DQS2 */
 4132                                         0x000fc000 /* EMC_DLL_XFORM_DQS3 */
 4133                                         0x000fc000 /* EMC_DLL_XFORM_DQS4 */
 4134                                         0x000fc000 /* EMC_DLL_XFORM_DQS5 */
 4135                                         0x000fc000 /* EMC_DLL_XFORM_DQS6 */
 4136                                         0x000fc000 /* EMC_DLL_XFORM_DQS7 */
 4137                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 4138                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 4139                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 4140                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 4141                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 4142                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 4143                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 4144                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 4145                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 4146                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 4147                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 4148                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 4149                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 4150                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 4151                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 4152                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 4153                                         0x000fc000 /* EMC_DLL_XFORM_DQ0 */
 4154                                         0x000fc000 /* EMC_DLL_XFORM_DQ1 */
 4155                                         0x000fc000 /* EMC_DLL_XFORM_DQ2 */
 4156                                         0x000fc000 /* EMC_DLL_XFORM_DQ3 */
 4157                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 4158                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
 4159                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
 4160                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 4161                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
 4162                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
 4163                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
 4164                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
 4165                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
 4166                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 4167                                         0x00000000 /* EMC_ZCAL_INTERVAL */
 4168                                         0x00000040 /* EMC_ZCAL_WAIT_CNT */
 4169                                         0x000c000c /* EMC_MRS_WAIT_CNT */
 4170                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 4171                                         0x00000000 /* EMC_CTT */
 4172                                         0x00000000 /* EMC_CTT_DURATION */
 4173                                         0x80000713 /* EMC_DYN_SELF_REF_CONTROL */
 4174                                         0xe8000000 /* EMC_FBIO_SPARE */
 4175                                         0xff00ff00 /* EMC_CFG_RSV */
 4176                                 >;
 4177                         };
 4178 
 4179                         timing-204000000 {
 4180                                 clock-frequency = <204000000>;
 4181                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 4182                                 nvidia,emc-mode-1 = <0x80100003>;
 4183                                 nvidia,emc-mode-2 = <0x80200008>;
 4184                                 nvidia,emc-mode-reset = <0x80001221>;
 4185                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 4186                                 nvidia,emc-cfg-periodic-qrst;
 4187                                 nvidia,emc-cfg-dyn-self-ref;
 4188                                 nvidia,emc-configuration = <
 4189                                         0x00000009 /* EMC_RC */
 4190                                         0x0000003d /* EMC_RFC */
 4191                                         0x00000007 /* EMC_RAS */
 4192                                         0x00000002 /* EMC_RP */
 4193                                         0x00000002 /* EMC_R2W */
 4194                                         0x0000000a /* EMC_W2R */
 4195                                         0x00000005 /* EMC_R2P */
 4196                                         0x0000000b /* EMC_W2P */
 4197                                         0x00000002 /* EMC_RD_RCD */
 4198                                         0x00000002 /* EMC_WR_RCD */
 4199                                         0x00000003 /* EMC_RRD */
 4200                                         0x00000001 /* EMC_REXT */
 4201                                         0x00000000 /* EMC_WEXT */
 4202                                         0x00000005 /* EMC_WDV */
 4203                                         0x00000005 /* EMC_QUSE */
 4204                                         0x00000004 /* EMC_QRST */
 4205                                         0x0000000a /* EMC_QSAFE */
 4206                                         0x0000000b /* EMC_RDV */
 4207                                         0x00000607 /* EMC_REFRESH */
 4208                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 4209                                         0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */
 4210                                         0x00000002 /* EMC_PDEX2WR */
 4211                                         0x00000002 /* EMC_PDEX2RD */
 4212                                         0x00000001 /* EMC_PCHG2PDEN */
 4213                                         0x00000000 /* EMC_ACT2PDEN */
 4214                                         0x00000007 /* EMC_AR2PDEN */
 4215                                         0x0000000f /* EMC_RW2PDEN */
 4216                                         0x00000040 /* EMC_TXSR */
 4217                                         0x00000040 /* EMC_TXSRDLL */
 4218                                         0x00000004 /* EMC_TCKE */
 4219                                         0x00000009 /* EMC_TFAW */
 4220                                         0x00000000 /* EMC_TRPAB */
 4221                                         0x00000004 /* EMC_TCLKSTABLE */
 4222                                         0x00000005 /* EMC_TCLKSTOP */
 4223                                         0x00000638 /* EMC_TREFBW */
 4224                                         0x00000006 /* EMC_QUSE_EXTRA */
 4225                                         0x00000006 /* EMC_FBIO_CFG6 */
 4226                                         0x00000000 /* EMC_ODT_WRITE */
 4227                                         0x00000000 /* EMC_ODT_READ */
 4228                                         0x00004288 /* EMC_FBIO_CFG5 */
 4229                                         0x004400a4 /* EMC_CFG_DIG_DLL */
 4230                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 4231                                         0x00080000 /* EMC_DLL_XFORM_DQS0 */
 4232                                         0x00080000 /* EMC_DLL_XFORM_DQS1 */
 4233                                         0x00080000 /* EMC_DLL_XFORM_DQS2 */
 4234                                         0x00080000 /* EMC_DLL_XFORM_DQS3 */
 4235                                         0x00080000 /* EMC_DLL_XFORM_DQS4 */
 4236                                         0x00080000 /* EMC_DLL_XFORM_DQS5 */
 4237                                         0x00080000 /* EMC_DLL_XFORM_DQS6 */
 4238                                         0x00080000 /* EMC_DLL_XFORM_DQS7 */
 4239                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 4240                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 4241                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 4242                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 4243                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 4244                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 4245                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 4246                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 4247                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 4248                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 4249                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 4250                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 4251                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 4252                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 4253                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 4254                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 4255                                         0x00080000 /* EMC_DLL_XFORM_DQ0 */
 4256                                         0x00080000 /* EMC_DLL_XFORM_DQ1 */
 4257                                         0x00080000 /* EMC_DLL_XFORM_DQ2 */
 4258                                         0x00080000 /* EMC_DLL_XFORM_DQ3 */
 4259                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 4260                                         0x0800211c /* EMC_XM2DQSPADCTRL2 */
 4261                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
 4262                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 4263                                         0x01f1f108 /* EMC_XM2COMPPADCTRL */
 4264                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
 4265                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
 4266                                         0x08000168 /* EMC_XM2QUSEPADCTRL */
 4267                                         0x08000000 /* EMC_XM2DQSPADCTRL3 */
 4268                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 4269                                         0x00020000 /* EMC_ZCAL_INTERVAL */
 4270                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
 4271                                         0x000c000c /* EMC_MRS_WAIT_CNT */
 4272                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 4273                                         0x00000000 /* EMC_CTT */
 4274                                         0x00000000 /* EMC_CTT_DURATION */
 4275                                         0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */
 4276                                         0xe8000000 /* EMC_FBIO_SPARE */
 4277                                         0xff00ff00 /* EMC_CFG_RSV */
 4278                                 >;
 4279                         };
 4280 
 4281                         timing-400000000 {
 4282                                 clock-frequency = <400000000>;
 4283                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 4284                                 nvidia,emc-mode-1 = <0x80100002>;
 4285                                 nvidia,emc-mode-2 = <0x80200000>;
 4286                                 nvidia,emc-mode-reset = <0x80000521>;
 4287                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 4288                                 nvidia,emc-configuration = <
 4289                                         0x00000012 /* EMC_RC */
 4290                                         0x00000076 /* EMC_RFC */
 4291                                         0x0000000c /* EMC_RAS */
 4292                                         0x00000004 /* EMC_RP */
 4293                                         0x00000003 /* EMC_R2W */
 4294                                         0x00000008 /* EMC_W2R */
 4295                                         0x00000002 /* EMC_R2P */
 4296                                         0x0000000a /* EMC_W2P */
 4297                                         0x00000004 /* EMC_RD_RCD */
 4298                                         0x00000004 /* EMC_WR_RCD */
 4299                                         0x00000002 /* EMC_RRD */
 4300                                         0x00000001 /* EMC_REXT */
 4301                                         0x00000000 /* EMC_WEXT */
 4302                                         0x00000004 /* EMC_WDV */
 4303                                         0x00000006 /* EMC_QUSE */
 4304                                         0x00000004 /* EMC_QRST */
 4305                                         0x0000000a /* EMC_QSAFE */
 4306                                         0x0000000c /* EMC_RDV */
 4307                                         0x00000bf0 /* EMC_REFRESH */
 4308                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 4309                                         0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */
 4310                                         0x00000001 /* EMC_PDEX2WR */
 4311                                         0x00000008 /* EMC_PDEX2RD */
 4312                                         0x00000001 /* EMC_PCHG2PDEN */
 4313                                         0x00000000 /* EMC_ACT2PDEN */
 4314                                         0x00000008 /* EMC_AR2PDEN */
 4315                                         0x0000000f /* EMC_RW2PDEN */
 4316                                         0x0000007c /* EMC_TXSR */
 4317                                         0x00000200 /* EMC_TXSRDLL */
 4318                                         0x00000004 /* EMC_TCKE */
 4319                                         0x00000010 /* EMC_TFAW */
 4320                                         0x00000000 /* EMC_TRPAB */
 4321                                         0x00000004 /* EMC_TCLKSTABLE */
 4322                                         0x00000005 /* EMC_TCLKSTOP */
 4323                                         0x00000c30 /* EMC_TREFBW */
 4324                                         0x00000000 /* EMC_QUSE_EXTRA */
 4325                                         0x00000004 /* EMC_FBIO_CFG6 */
 4326                                         0x00000000 /* EMC_ODT_WRITE */
 4327                                         0x00000000 /* EMC_ODT_READ */
 4328                                         0x00007088 /* EMC_FBIO_CFG5 */
 4329                                         0x001d0084 /* EMC_CFG_DIG_DLL */
 4330                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 4331                                         0x00044000 /* EMC_DLL_XFORM_DQS0 */
 4332                                         0x00044000 /* EMC_DLL_XFORM_DQS1 */
 4333                                         0x00044000 /* EMC_DLL_XFORM_DQS2 */
 4334                                         0x00044000 /* EMC_DLL_XFORM_DQS3 */
 4335                                         0x00044000 /* EMC_DLL_XFORM_DQS4 */
 4336                                         0x00044000 /* EMC_DLL_XFORM_DQS5 */
 4337                                         0x00044000 /* EMC_DLL_XFORM_DQS6 */
 4338                                         0x00044000 /* EMC_DLL_XFORM_DQS7 */
 4339                                         0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 4340                                         0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 4341                                         0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 4342                                         0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 4343                                         0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 4344                                         0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 4345                                         0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 4346                                         0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 4347                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 4348                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 4349                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 4350                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 4351                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 4352                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 4353                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 4354                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 4355                                         0x00058000 /* EMC_DLL_XFORM_DQ0 */
 4356                                         0x00058000 /* EMC_DLL_XFORM_DQ1 */
 4357                                         0x00058000 /* EMC_DLL_XFORM_DQ2 */
 4358                                         0x00058000 /* EMC_DLL_XFORM_DQ3 */
 4359                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 4360                                         0x0800013d /* EMC_XM2DQSPADCTRL2 */
 4361                                         0x00000000 /* EMC_XM2DQPADCTRL2 */
 4362                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 4363                                         0x01f1f508 /* EMC_XM2COMPPADCTRL */
 4364                                         0x05057404 /* EMC_XM2VTTGENPADCTRL */
 4365                                         0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
 4366                                         0x080001e8 /* EMC_XM2QUSEPADCTRL */
 4367                                         0x08000021 /* EMC_XM2DQSPADCTRL3 */
 4368                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 4369                                         0x00020000 /* EMC_ZCAL_INTERVAL */
 4370                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
 4371                                         0x0148000c /* EMC_MRS_WAIT_CNT */
 4372                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 4373                                         0x00000000 /* EMC_CTT */
 4374                                         0x00000000 /* EMC_CTT_DURATION */
 4375                                         0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */
 4376                                         0xe8000000 /* EMC_FBIO_SPARE */
 4377                                         0xff00ff89 /* EMC_CFG_RSV */
 4378                                 >;
 4379                         };
 4380 
 4381                         timing-800000000 {
 4382                                 clock-frequency = <800000000>;
 4383                                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 4384                                 nvidia,emc-mode-1 = <0x80100002>;
 4385                                 nvidia,emc-mode-2 = <0x80200018>;
 4386                                 nvidia,emc-mode-reset = <0x80000d71>;
 4387                                 nvidia,emc-zcal-cnt-long = <0x00000040>;
 4388                                 nvidia,emc-cfg-periodic-qrst;
 4389                                 nvidia,emc-configuration = <
 4390                                         0x00000025 /* EMC_RC */
 4391                                         0x000000ee /* EMC_RFC */
 4392                                         0x0000001a /* EMC_RAS */
 4393                                         0x00000009 /* EMC_RP */
 4394                                         0x00000005 /* EMC_R2W */
 4395                                         0x0000000d /* EMC_W2R */
 4396                                         0x00000004 /* EMC_R2P */
 4397                                         0x00000013 /* EMC_W2P */
 4398                                         0x00000009 /* EMC_RD_RCD */
 4399                                         0x00000009 /* EMC_WR_RCD */
 4400                                         0x00000003 /* EMC_RRD */
 4401                                         0x00000001 /* EMC_REXT */
 4402                                         0x00000000 /* EMC_WEXT */
 4403                                         0x00000007 /* EMC_WDV */
 4404                                         0x0000000a /* EMC_QUSE */
 4405                                         0x00000009 /* EMC_QRST */
 4406                                         0x0000000b /* EMC_QSAFE */
 4407                                         0x00000011 /* EMC_RDV */
 4408                                         0x00001820 /* EMC_REFRESH */
 4409                                         0x00000000 /* EMC_BURST_REFRESH_NUM */
 4410                                         0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */
 4411                                         0x00000003 /* EMC_PDEX2WR */
 4412                                         0x00000012 /* EMC_PDEX2RD */
 4413                                         0x00000001 /* EMC_PCHG2PDEN */
 4414                                         0x00000000 /* EMC_ACT2PDEN */
 4415                                         0x0000000f /* EMC_AR2PDEN */
 4416                                         0x00000018 /* EMC_RW2PDEN */
 4417                                         0x000000f8 /* EMC_TXSR */
 4418                                         0x00000200 /* EMC_TXSRDLL */
 4419                                         0x00000005 /* EMC_TCKE */
 4420                                         0x00000020 /* EMC_TFAW */
 4421                                         0x00000000 /* EMC_TRPAB */
 4422                                         0x00000007 /* EMC_TCLKSTABLE */
 4423                                         0x00000008 /* EMC_TCLKSTOP */
 4424                                         0x00001860 /* EMC_TREFBW */
 4425                                         0x0000000b /* EMC_QUSE_EXTRA */
 4426                                         0x00000006 /* EMC_FBIO_CFG6 */
 4427                                         0x00000000 /* EMC_ODT_WRITE */
 4428                                         0x00000000 /* EMC_ODT_READ */
 4429                                         0x00005088 /* EMC_FBIO_CFG5 */
 4430                                         0xf0070191 /* EMC_CFG_DIG_DLL */
 4431                                         0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 4432                                         0x0000000c /* EMC_DLL_XFORM_DQS0 */
 4433                                         0x007fc00a /* EMC_DLL_XFORM_DQS1 */
 4434                                         0x00000008 /* EMC_DLL_XFORM_DQS2 */
 4435                                         0x0000000a /* EMC_DLL_XFORM_DQS3 */
 4436                                         0x0000000a /* EMC_DLL_XFORM_DQS4 */
 4437                                         0x0000000a /* EMC_DLL_XFORM_DQS5 */
 4438                                         0x0000000a /* EMC_DLL_XFORM_DQS6 */
 4439                                         0x0000000a /* EMC_DLL_XFORM_DQS7 */
 4440                                         0x00018000 /* EMC_DLL_XFORM_QUSE0 */
 4441                                         0x00018000 /* EMC_DLL_XFORM_QUSE1 */
 4442                                         0x00018000 /* EMC_DLL_XFORM_QUSE2 */
 4443                                         0x00018000 /* EMC_DLL_XFORM_QUSE3 */
 4444                                         0x00018000 /* EMC_DLL_XFORM_QUSE4 */
 4445                                         0x00018000 /* EMC_DLL_XFORM_QUSE5 */
 4446                                         0x00018000 /* EMC_DLL_XFORM_QUSE6 */
 4447                                         0x00018000 /* EMC_DLL_XFORM_QUSE7 */
 4448                                         0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 4449                                         0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 4450                                         0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 4451                                         0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 4452                                         0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 4453                                         0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 4454                                         0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 4455                                         0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 4456                                         0x0000000a /* EMC_DLL_XFORM_DQ0 */
 4457                                         0x0000000c /* EMC_DLL_XFORM_DQ1 */
 4458                                         0x0000000a /* EMC_DLL_XFORM_DQ2 */
 4459                                         0x0000000a /* EMC_DLL_XFORM_DQ3 */
 4460                                         0x000002a0 /* EMC_XM2CMDPADCTRL */
 4461                                         0x0600013d /* EMC_XM2DQSPADCTRL2 */
 4462                                         0x22220000 /* EMC_XM2DQPADCTRL2 */
 4463                                         0x77fff884 /* EMC_XM2CLKPADCTRL */
 4464                                         0x01f1f501 /* EMC_XM2COMPPADCTRL */
 4465                                         0x07077404 /* EMC_XM2VTTGENPADCTRL */
 4466                                         0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
 4467                                         0x080001e8 /* EMC_XM2QUSEPADCTRL */
 4468                                         0x0a000021 /* EMC_XM2DQSPADCTRL3 */
 4469                                         0x00000802 /* EMC_CTT_TERM_CTRL */
 4470                                         0x00020000 /* EMC_ZCAL_INTERVAL */
 4471                                         0x00000100 /* EMC_ZCAL_WAIT_CNT */
 4472                                         0x00d0000c /* EMC_MRS_WAIT_CNT */
 4473                                         0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
 4474                                         0x00000000 /* EMC_CTT */
 4475                                         0x00000000 /* EMC_CTT_DURATION */
 4476                                         0x8000308c /* EMC_DYN_SELF_REF_CONTROL */
 4477                                         0xe8000000 /* EMC_FBIO_SPARE */
 4478                                         0xff00ff49 /* EMC_CFG_RSV */
 4479                                 >;
 4480                         };
 4481                 };
 4482         };
 4483 
 4484         hda@70030000 {
 4485                 status = "okay";
 4486         };
 4487 
 4488         wifi_pwrseq: wifi_pwrseq {
 4489                 compatible = "mmc-pwrseq-simple";
 4490 
 4491                 clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
 4492                 clock-names = "ext_clock";
 4493 
 4494                 reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>;
 4495                 post-power-on-delay-ms = <300>;
 4496                 power-off-delay-us = <300>;
 4497         };
 4498 
 4499         sdmmc3: mmc@78000400 {
 4500                 status = "okay";
 4501 
 4502                 #address-cells = <1>;
 4503                 #size-cells = <0>;
 4504 
 4505                 assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 4506                 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
 4507                 assigned-clock-rates = <50000000>;
 4508 
 4509                 max-frequency = <50000000>;
 4510                 keep-power-in-suspend;
 4511 
 4512                 bus-width = <4>;
 4513                 non-removable;
 4514 
 4515                 mmc-pwrseq = <&wifi_pwrseq>;
 4516                 vmmc-supply = <&sdmmc_3v3_reg>;
 4517                 vqmmc-supply = <&vdd_1v8>;
 4518 
 4519                 /* Azurewave AW-NH660 BCM4330 */
 4520                 brcmf: wifi@1 {
 4521                         reg = <1>;
 4522                         compatible = "brcm,bcm4329-fmac";
 4523                         interrupt-parent = <&gpio>;
 4524                         interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
 4525                         interrupt-names = "host-wake";
 4526                 };
 4527         };
 4528 
 4529         sdmmc4: mmc@78000600 {
 4530                 status = "okay";
 4531 
 4532                 keep-power-in-suspend;
 4533                 bus-width = <8>;
 4534                 non-removable;
 4535                 vmmc-supply = <&sys_3v3_reg>;
 4536                 vqmmc-supply = <&vdd_1v8>;
 4537                 nvidia,default-tap = <0x0F>;
 4538                 max-frequency = <25500000>;
 4539         };
 4540 
 4541         usb@7d000000 {
 4542                 compatible = "nvidia,tegra30-udc";
 4543                 status = "okay";
 4544         };
 4545 
 4546         usb-phy@7d000000 {
 4547                 status = "okay";
 4548                 dr_mode = "peripheral";
 4549         };
 4550 
 4551         usb@7d004000 {
 4552                 status = "okay";
 4553                 #address-cells = <1>;
 4554                 #size-cells = <0>;
 4555 
 4556                 ethernet@2 { /* SMSC 10/100T Ethernet Controller */
 4557                         compatible = "usb424,9e00";
 4558                         reg = <2>;
 4559                         local-mac-address = [00 11 22 33 44 55];
 4560                 };
 4561         };
 4562 
 4563         usb-phy@7d004000 {
 4564                 vbus-supply = <&vdd_smsc>;
 4565                 status = "okay";
 4566         };
 4567 
 4568         usb@7d008000 {
 4569                 status = "okay";
 4570         };
 4571 
 4572         usb-phy@7d008000 {
 4573                 vbus-supply = <&usb3_vbus_reg>;
 4574                 status = "okay";
 4575         };
 4576 
 4577         /* PMIC has a built-in 32KHz oscillator which is used by PMC */
 4578         clk32k_in: clock {
 4579                 compatible = "fixed-clock";
 4580                 #clock-cells = <0>;
 4581                 clock-frequency = <32768>;
 4582                 clock-output-names = "pmic-oscillator";
 4583         };
 4584 
 4585         cpus {
 4586                 cpu0: cpu@0 {
 4587                         operating-points-v2 = <&cpu0_opp_table>;
 4588                         cpu-supply = <&vdd_cpu>;
 4589                         #cooling-cells = <2>;
 4590                 };
 4591 
 4592                 cpu1: cpu@1 {
 4593                         operating-points-v2 = <&cpu0_opp_table>;
 4594                         cpu-supply = <&vdd_cpu>;
 4595                         #cooling-cells = <2>;
 4596                 };
 4597 
 4598                 cpu2: cpu@2 {
 4599                         operating-points-v2 = <&cpu0_opp_table>;
 4600                         cpu-supply = <&vdd_cpu>;
 4601                         #cooling-cells = <2>;
 4602                 };
 4603 
 4604                 cpu3: cpu@3 {
 4605                         operating-points-v2 = <&cpu0_opp_table>;
 4606                         cpu-supply = <&vdd_cpu>;
 4607                         #cooling-cells = <2>;
 4608                 };
 4609         };
 4610 
 4611         firmware {
 4612                 trusted-foundations {
 4613                         compatible = "tlm,trusted-foundations";
 4614                         tlm,version-major = <0x0>;
 4615                         tlm,version-minor = <0x0>;
 4616                 };
 4617         };
 4618 
 4619         fan: gpio_fan {
 4620                 compatible = "gpio-fan";
 4621                 gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>;
 4622                 gpio-fan,speed-map = <0    0
 4623                                       4500 1>;
 4624                 #cooling-cells = <2>;
 4625         };
 4626 
 4627         thermal-zones {
 4628                 cpu_thermal: cpu-thermal {
 4629                         polling-delay = <5000>;
 4630                         polling-delay-passive = <5000>;
 4631 
 4632                         thermal-sensors = <&cpu_temp 1>;
 4633 
 4634                         trips {
 4635                                 cpu_alert0: cpu-alert0 {
 4636                                         temperature = <50000>;
 4637                                         hysteresis = <10000>;
 4638                                         type = "active";
 4639                                 };
 4640                                 cpu_alert1: cpu-alert1 {
 4641                                         temperature = <70000>;
 4642                                         hysteresis = <5000>;
 4643                                         type = "passive";
 4644                                 };
 4645                                 cpu_crit: cpu-crit {
 4646                                         temperature = <90000>;
 4647                                         hysteresis = <2000>;
 4648                                         type = "critical";
 4649                                 };
 4650                         };
 4651 
 4652                         cooling-maps {
 4653                                 map0 {
 4654                                         trip = <&cpu_alert0>;
 4655                                         cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 4656                                 };
 4657                                 map1 {
 4658                                         trip = <&cpu_alert1>;
 4659                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 4660                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 4661                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 4662                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 4663                                                          <&actmon THERMAL_NO_LIMIT
 4664                                                                   THERMAL_NO_LIMIT>;
 4665                                 };
 4666                         };
 4667                 };
 4668         };
 4669 
 4670         vdd_12v_in: vdd_12v_in {
 4671                 compatible = "regulator-fixed";
 4672                 regulator-name = "vdd_12v_in";
 4673                 regulator-min-microvolt = <12000000>;
 4674                 regulator-max-microvolt = <12000000>;
 4675                 regulator-always-on;
 4676         };
 4677 
 4678         sdmmc_3v3_reg: sdmmc_3v3_reg {
 4679                 compatible = "regulator-fixed";
 4680                 regulator-name = "sdmmc_3v3";
 4681                 regulator-min-microvolt = <3300000>;
 4682                 regulator-max-microvolt = <3300000>;
 4683                 enable-active-high;
 4684                 regulator-always-on;
 4685                 gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
 4686                 vin-supply = <&sys_3v3_reg>;
 4687         };
 4688 
 4689         vdd_fuse_3v3_reg: vdd_fuse_3v3_reg {
 4690                 compatible = "regulator-fixed";
 4691                 regulator-name = "vdd_fuse_3v3";
 4692                 regulator-min-microvolt = <3300000>;
 4693                 regulator-max-microvolt = <3300000>;
 4694                 enable-active-high;
 4695                 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
 4696                 vin-supply = <&sys_3v3_reg>;
 4697                 regulator-always-on;
 4698         };
 4699 
 4700         vdd_vid_reg: vdd_vid_reg {
 4701                 compatible = "regulator-fixed";
 4702                 regulator-name = "vddio_vid";
 4703                 regulator-min-microvolt = <5000000>;
 4704                 regulator-max-microvolt = <5000000>;
 4705                 enable-active-high;
 4706                 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
 4707                 vin-supply = <&vdd_5v0_reg>;
 4708                 regulator-boot-on;
 4709         };
 4710 
 4711         ddr_reg: ddr_reg {
 4712                 compatible = "regulator-fixed";
 4713                 regulator-name = "vdd_ddr";
 4714                 regulator-min-microvolt = <1500000>;
 4715                 regulator-max-microvolt = <1500000>;
 4716                 regulator-always-on;
 4717                 enable-active-high;
 4718                 gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
 4719                 regulator-boot-on;
 4720                 vin-supply = <&vdd_12v_in>;
 4721         };
 4722 
 4723         sys_3v3_reg: sys_3v3_reg {
 4724                 compatible = "regulator-fixed";
 4725                 regulator-name = "sys_3v3";
 4726                 regulator-min-microvolt = <3300000>;
 4727                 regulator-max-microvolt = <3300000>;
 4728                 enable-active-high;
 4729                 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 4730                 regulator-always-on;
 4731                 regulator-boot-on;
 4732                 vin-supply = <&vdd_12v_in>;
 4733         };
 4734 
 4735         vdd_5v0_reg: vdd_5v0_reg {
 4736                 compatible = "regulator-fixed";
 4737                 regulator-name = "vdd_5v0";
 4738                 regulator-min-microvolt = <5000000>;
 4739                 regulator-max-microvolt = <5000000>;
 4740                 enable-active-high;
 4741                 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
 4742                 regulator-always-on;
 4743                 regulator-boot-on;
 4744                 vin-supply = <&vdd_12v_in>;
 4745         };
 4746 
 4747         vdd_smsc: vdd_smsc {
 4748                 compatible = "regulator-fixed";
 4749                 regulator-name = "vdd_smsc";
 4750                 enable-active-high;
 4751                 gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>;
 4752         };
 4753 
 4754         usb3_vbus_reg: usb3_vbus_reg {
 4755                 compatible = "regulator-fixed";
 4756                 regulator-name = "usb3_vbus";
 4757                 regulator-min-microvolt = <5000000>;
 4758                 regulator-max-microvolt = <5000000>;
 4759                 enable-active-high;
 4760                 gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
 4761                 vin-supply = <&vdd_5v0_reg>;
 4762         };
 4763 
 4764         gpio-keys {
 4765                 compatible = "gpio-keys";
 4766 
 4767                 key-power {
 4768                         gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
 4769                         debounce-interval = <10>;
 4770                         linux,code = <KEY_POWER>;
 4771                         wakeup-event-action = <EV_ACT_ASSERTED>;
 4772                         wakeup-source;
 4773                 };
 4774         };
 4775 
 4776 
 4777         leds {
 4778                 compatible = "gpio-leds";
 4779 
 4780                 led-power {
 4781                         label = "power-led";
 4782                         gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
 4783                         default-state = "on";
 4784                         linux,default-trigger = "heartbeat";
 4785                         retain-state-suspended;
 4786                 };
 4787         };
 4788 };
 4789 
 4790 &emc_icc_dvfs_opp_table {
 4791         /delete-node/ opp-900000000-1350;
 4792 };
 4793 
 4794 &emc_bw_dfs_opp_table {
 4795         /delete-node/ opp-900000000;
 4796 };
Cache object: 29fada266a7a8d42777ce2e3c4b9f481
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.
FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm/tegra30-ouya.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/tegra30-ouya.dts
