Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/vf610-twr.dts
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1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 // 3 // Copyright 2013 Freescale Semiconductor, Inc. 4 5 /dts-v1/; 6 #include "vf610.dtsi" 7 8 / { 9 model = "VF610 Tower Board"; 10 compatible = "fsl,vf610-twr", "fsl,vf610"; 11 12 chosen { 13 bootargs = "console=ttyLP1,115200"; 14 }; 15 16 memory@80000000 { 17 device_type = "memory"; 18 reg = <0x80000000 0x8000000>; 19 }; 20 21 audio_ext: mclk_osc { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <24576000>; 25 }; 26 27 enet_ext: eth_osc { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <50000000>; 31 }; 32 33 regulators { 34 compatible = "simple-bus"; 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 reg_3p3v: regulator@0 { 39 compatible = "regulator-fixed"; 40 reg = <0>; 41 regulator-name = "3P3V"; 42 regulator-min-microvolt = <3300000>; 43 regulator-max-microvolt = <3300000>; 44 regulator-always-on; 45 }; 46 47 reg_vcc_3v3_mcu: regulator@1 { 48 compatible = "regulator-fixed"; 49 reg = <1>; 50 regulator-name = "vcc_3v3_mcu"; 51 regulator-min-microvolt = <3300000>; 52 regulator-max-microvolt = <3300000>; 53 }; 54 }; 55 56 sound { 57 compatible = "simple-audio-card"; 58 simple-audio-card,format = "i2s"; 59 simple-audio-card,widgets = 60 "Microphone", "Microphone Jack", 61 "Headphone", "Headphone Jack", 62 "Speaker", "Speaker Ext", 63 "Line", "Line In Jack"; 64 simple-audio-card,routing = 65 "MIC_IN", "Microphone Jack", 66 "Microphone Jack", "Mic Bias", 67 "LINE_IN", "Line In Jack", 68 "Headphone Jack", "HP_OUT", 69 "Speaker Ext", "LINE_OUT"; 70 71 simple-audio-card,cpu { 72 sound-dai = <&sai2>; 73 frame-master; 74 bitclock-master; 75 }; 76 77 simple-audio-card,codec { 78 sound-dai = <&codec>; 79 frame-master; 80 bitclock-master; 81 }; 82 }; 83 }; 84 85 &adc0 { 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_adc0_ad5>; 88 vref-supply = <®_vcc_3v3_mcu>; 89 status = "okay"; 90 }; 91 92 &clks { 93 clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>; 94 clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext"; 95 assigned-clocks = <&clks VF610_CLK_ENET_SEL>, 96 <&clks VF610_CLK_ENET_TS_SEL>; 97 assigned-clock-parents = <&clks VF610_CLK_ENET_EXT>, 98 <&clks VF610_CLK_ENET_EXT>; 99 }; 100 101 &dspi0 { 102 bus-num = <0>; 103 pinctrl-names = "default"; 104 pinctrl-0 = <&pinctrl_dspi0>; 105 status = "okay"; 106 107 sflash: at26df081a@0 { 108 #address-cells = <1>; 109 #size-cells = <1>; 110 compatible = "atmel,at26df081a"; 111 spi-max-frequency = <16000000>; 112 spi-cpol; 113 spi-cpha; 114 reg = <0>; 115 }; 116 }; 117 118 &edma0 { 119 status = "okay"; 120 }; 121 122 &esdhc1 { 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_esdhc1>; 125 bus-width = <4>; 126 cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; 127 status = "okay"; 128 }; 129 130 &fec0 { 131 phy-mode = "rmii"; 132 phy-handle = <ðphy0>; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pinctrl_fec0>; 135 status = "okay"; 136 137 mdio { 138 #address-cells = <1>; 139 #size-cells = <0>; 140 141 ethphy0: ethernet-phy@0 { 142 reg = <0>; 143 }; 144 145 ethphy1: ethernet-phy@1 { 146 reg = <1>; 147 }; 148 }; 149 }; 150 151 &fec1 { 152 phy-mode = "rmii"; 153 phy-handle = <ðphy1>; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_fec1>; 156 status = "okay"; 157 }; 158 159 &i2c0 { 160 clock-frequency = <100000>; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_i2c0>; 163 status = "okay"; 164 165 codec: sgtl5000@a { 166 #sound-dai-cells = <0>; 167 compatible = "fsl,sgtl5000"; 168 reg = <0x0a>; 169 VDDA-supply = <®_3p3v>; 170 VDDIO-supply = <®_3p3v>; 171 clocks = <&clks VF610_CLK_SAI2>; 172 }; 173 }; 174 175 &iomuxc { 176 vf610-twr { 177 pinctrl_adc0_ad5: adc0ad5grp { 178 fsl,pins = < 179 VF610_PAD_PTC30__ADC0_SE5 0xa1 180 >; 181 }; 182 183 pinctrl_dspi0: dspi0grp { 184 fsl,pins = < 185 VF610_PAD_PTB19__DSPI0_CS0 0x1182 186 VF610_PAD_PTB20__DSPI0_SIN 0x1181 187 VF610_PAD_PTB21__DSPI0_SOUT 0x1182 188 VF610_PAD_PTB22__DSPI0_SCK 0x1182 189 >; 190 }; 191 192 pinctrl_esdhc1: esdhc1grp { 193 fsl,pins = < 194 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef 195 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef 196 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef 197 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef 198 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef 199 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef 200 VF610_PAD_PTA7__GPIO_134 0x219d 201 >; 202 }; 203 204 pinctrl_fec0: fec0grp { 205 fsl,pins = < 206 VF610_PAD_PTA6__RMII_CLKIN 0x30d1 207 VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3 208 VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1 209 VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 210 VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 211 VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 212 VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 213 VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 214 VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 215 VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 216 >; 217 }; 218 219 pinctrl_fec1: fec1grp { 220 fsl,pins = < 221 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 222 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 223 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 224 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 225 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 226 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 227 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 228 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 229 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 230 >; 231 }; 232 233 pinctrl_i2c0: i2c0grp { 234 fsl,pins = < 235 VF610_PAD_PTB14__I2C0_SCL 0x30d3 236 VF610_PAD_PTB15__I2C0_SDA 0x30d3 237 >; 238 }; 239 240 pinctrl_nfc: nfcgrp { 241 fsl,pins = < 242 VF610_PAD_PTD31__NF_IO15 0x28df 243 VF610_PAD_PTD30__NF_IO14 0x28df 244 VF610_PAD_PTD29__NF_IO13 0x28df 245 VF610_PAD_PTD28__NF_IO12 0x28df 246 VF610_PAD_PTD27__NF_IO11 0x28df 247 VF610_PAD_PTD26__NF_IO10 0x28df 248 VF610_PAD_PTD25__NF_IO9 0x28df 249 VF610_PAD_PTD24__NF_IO8 0x28df 250 VF610_PAD_PTD23__NF_IO7 0x28df 251 VF610_PAD_PTD22__NF_IO6 0x28df 252 VF610_PAD_PTD21__NF_IO5 0x28df 253 VF610_PAD_PTD20__NF_IO4 0x28df 254 VF610_PAD_PTD19__NF_IO3 0x28df 255 VF610_PAD_PTD18__NF_IO2 0x28df 256 VF610_PAD_PTD17__NF_IO1 0x28df 257 VF610_PAD_PTD16__NF_IO0 0x28df 258 VF610_PAD_PTB24__NF_WE_B 0x28c2 259 VF610_PAD_PTB25__NF_CE0_B 0x28c2 260 VF610_PAD_PTB27__NF_RE_B 0x28c2 261 VF610_PAD_PTC26__NF_RB_B 0x283d 262 VF610_PAD_PTC27__NF_ALE 0x28c2 263 VF610_PAD_PTC28__NF_CLE 0x28c2 264 >; 265 }; 266 267 pinctrl_pwm0: pwm0grp { 268 fsl,pins = < 269 VF610_PAD_PTB0__FTM0_CH0 0x1582 270 VF610_PAD_PTB1__FTM0_CH1 0x1582 271 VF610_PAD_PTB2__FTM0_CH2 0x1582 272 VF610_PAD_PTB3__FTM0_CH3 0x1582 273 >; 274 }; 275 276 pinctrl_sai2: sai2grp { 277 fsl,pins = < 278 VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed 279 VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee 280 VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed 281 VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed 282 VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed 283 VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed 284 VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed 285 >; 286 }; 287 288 pinctrl_uart1: uart1grp { 289 fsl,pins = < 290 VF610_PAD_PTB4__UART1_TX 0x21a2 291 VF610_PAD_PTB5__UART1_RX 0x21a1 292 >; 293 }; 294 295 pinctrl_uart2: uart2grp { 296 fsl,pins = < 297 VF610_PAD_PTB6__UART2_TX 0x21a2 298 VF610_PAD_PTB7__UART2_RX 0x21a1 299 >; 300 }; 301 }; 302 }; 303 304 &nfc { 305 assigned-clocks = <&clks VF610_CLK_NFC>; 306 assigned-clock-rates = <33000000>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_nfc>; 309 status = "okay"; 310 311 nand@0 { 312 compatible = "fsl,vf610-nfc-nandcs"; 313 reg = <0>; 314 #address-cells = <1>; 315 #size-cells = <1>; 316 nand-bus-width = <16>; 317 nand-ecc-mode = "hw"; 318 nand-ecc-strength = <24>; 319 nand-ecc-step-size = <2048>; 320 nand-on-flash-bbt; 321 }; 322 }; 323 324 &pwm0 { 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pinctrl_pwm0>; 327 status = "okay"; 328 }; 329 330 &sai2 { 331 #sound-dai-cells = <0>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pinctrl_sai2>; 334 status = "okay"; 335 }; 336 337 &uart1 { 338 pinctrl-names = "default"; 339 pinctrl-0 = <&pinctrl_uart1>; 340 status = "okay"; 341 }; 342 343 &uart2 { 344 pinctrl-names = "default"; 345 pinctrl-0 = <&pinctrl_uart2>; 346 status = "okay"; 347 }; 348 349 &usbdev0 { 350 disable-over-current; 351 status = "okay"; 352 }; 353 354 &usbh1 { 355 disable-over-current; 356 status = "okay"; 357 }; 358 359 &usbmisc0 { 360 status = "okay"; 361 }; 362 363 &usbmisc1 { 364 status = "okay"; 365 }; 366 367 &usbphy0 { 368 status = "okay"; 369 }; 370 371 &usbphy1 { 372 status = "okay"; 373 };
Cache object: 81e649f4b440551903a3e3e348516b74
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