Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/vf610-zii-dev-rev-b.dts
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1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Copyright (C) 2015, 2016 Zodiac Inflight Innovations 4 */ 5 6 /dts-v1/; 7 #include "vf610-zii-dev.dtsi" 8 9 / { 10 model = "ZII VF610 Development Board, Rev B"; 11 compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610"; 12 13 mdio-mux { 14 compatible = "mdio-mux-gpio"; 15 pinctrl-0 = <&pinctrl_mdio_mux>; 16 pinctrl-names = "default"; 17 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH 18 &gpio0 9 GPIO_ACTIVE_HIGH 19 &gpio0 24 GPIO_ACTIVE_HIGH 20 &gpio0 25 GPIO_ACTIVE_HIGH>; 21 mdio-parent-bus = <&mdio1>; 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 mdio_mux_1: mdio@1 { 26 reg = <1>; 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 switch0: switch@0 { 31 compatible = "marvell,mv88e6085"; 32 pinctrl-0 = <&pinctrl_gpio_switch0>; 33 pinctrl-names = "default"; 34 reg = <0>; 35 dsa,member = <0 0>; 36 interrupt-parent = <&gpio0>; 37 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 38 interrupt-controller; 39 #interrupt-cells = <2>; 40 eeprom-length = <512>; 41 42 ports { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 port@0 { 47 reg = <0>; 48 label = "lan0"; 49 phy-handle = <&switch0phy0>; 50 }; 51 52 port@1 { 53 reg = <1>; 54 label = "lan1"; 55 phy-handle = <&switch0phy1>; 56 }; 57 58 port@2 { 59 reg = <2>; 60 label = "lan2"; 61 phy-handle = <&switch0phy2>; 62 }; 63 64 switch0port5: port@5 { 65 reg = <5>; 66 label = "dsa"; 67 phy-mode = "rgmii-txid"; 68 link = <&switch1port6 69 &switch2port9>; 70 fixed-link { 71 speed = <1000>; 72 full-duplex; 73 }; 74 }; 75 76 port@6 { 77 reg = <6>; 78 label = "cpu"; 79 ethernet = <&fec1>; 80 81 fixed-link { 82 speed = <100>; 83 full-duplex; 84 }; 85 }; 86 }; 87 mdio { 88 #address-cells = <1>; 89 #size-cells = <0>; 90 switch0phy0: switch0phy0@0 { 91 reg = <0>; 92 interrupt-parent = <&switch0>; 93 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 94 }; 95 switch0phy1: switch1phy0@1 { 96 reg = <1>; 97 interrupt-parent = <&switch0>; 98 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 99 }; 100 switch0phy2: switch1phy0@2 { 101 reg = <2>; 102 interrupt-parent = <&switch0>; 103 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 104 }; 105 }; 106 }; 107 }; 108 109 mdio_mux_2: mdio@2 { 110 reg = <2>; 111 #address-cells = <1>; 112 #size-cells = <0>; 113 114 switch1: switch@0 { 115 compatible = "marvell,mv88e6085"; 116 pinctrl-0 = <&pinctrl_gpio_switch1>; 117 pinctrl-names = "default"; 118 reg = <0>; 119 dsa,member = <0 1>; 120 interrupt-parent = <&gpio0>; 121 interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 122 interrupt-controller; 123 #interrupt-cells = <2>; 124 eeprom-length = <512>; 125 126 ports { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 130 port@0 { 131 reg = <0>; 132 label = "lan3"; 133 phy-handle = <&switch1phy0>; 134 }; 135 136 port@1 { 137 reg = <1>; 138 label = "lan4"; 139 phy-handle = <&switch1phy1>; 140 }; 141 142 port@2 { 143 reg = <2>; 144 label = "lan5"; 145 phy-handle = <&switch1phy2>; 146 }; 147 148 switch1port5: port@5 { 149 reg = <5>; 150 label = "dsa"; 151 link = <&switch2port9>; 152 phy-mode = "1000base-x"; 153 154 fixed-link { 155 speed = <1000>; 156 full-duplex; 157 }; 158 }; 159 160 switch1port6: port@6 { 161 reg = <6>; 162 label = "dsa"; 163 phy-mode = "rgmii-txid"; 164 link = <&switch0port5>; 165 fixed-link { 166 speed = <1000>; 167 full-duplex; 168 }; 169 }; 170 }; 171 mdio { 172 #address-cells = <1>; 173 #size-cells = <0>; 174 175 switch1phy0: switch1phy0@0 { 176 reg = <0>; 177 interrupt-parent = <&switch1>; 178 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 179 }; 180 181 switch1phy1: switch1phy0@1 { 182 reg = <1>; 183 interrupt-parent = <&switch1>; 184 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 185 }; 186 187 switch1phy2: switch1phy0@2 { 188 reg = <2>; 189 interrupt-parent = <&switch1>; 190 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 191 }; 192 }; 193 }; 194 }; 195 196 mdio_mux_4: mdio@4 { 197 #address-cells = <1>; 198 #size-cells = <0>; 199 reg = <4>; 200 201 switch2: switch@0 { 202 compatible = "marvell,mv88e6085"; 203 reg = <0>; 204 dsa,member = <0 2>; 205 206 ports { 207 #address-cells = <1>; 208 #size-cells = <0>; 209 210 port@0 { 211 reg = <0>; 212 label = "lan6"; 213 phy-handle = <&switch2phy0>; 214 phy-mode = "sgmii"; 215 }; 216 217 port@1 { 218 reg = <1>; 219 label = "lan7"; 220 phy-handle = <&switch2phy1>; 221 phy-mode = "sgmii"; 222 }; 223 224 port@2 { 225 reg = <2>; 226 label = "lan8"; 227 phy-handle = <&switch2phy2>; 228 }; 229 230 port@3 { 231 reg = <3>; 232 label = "optical3"; 233 234 fixed-link { 235 speed = <1000>; 236 full-duplex; 237 link-gpios = <&gpio6 2 238 GPIO_ACTIVE_HIGH>; 239 }; 240 }; 241 242 port@4 { 243 reg = <4>; 244 label = "optical4"; 245 246 fixed-link { 247 speed = <1000>; 248 full-duplex; 249 link-gpios = <&gpio6 3 250 GPIO_ACTIVE_HIGH>; 251 }; 252 }; 253 254 switch2port9: port@9 { 255 reg = <9>; 256 label = "dsa"; 257 phy-mode = "1000base-x"; 258 link = <&switch1port5 259 &switch0port5>; 260 261 fixed-link { 262 speed = <1000>; 263 full-duplex; 264 }; 265 }; 266 }; 267 mdio { 268 #address-cells = <1>; 269 #size-cells = <0>; 270 271 switch2phy0: phy@0 { 272 reg = <0>; 273 }; 274 switch2phy1: phy@1 { 275 reg = <1>; 276 }; 277 switch2phy2: phy@2 { 278 reg = <2>; 279 }; 280 }; 281 }; 282 }; 283 284 mdio_mux_8: mdio@8 { 285 reg = <8>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 }; 289 }; 290 291 spi0 { 292 compatible = "spi-gpio"; 293 pinctrl-0 = <&pinctrl_gpio_spi0>; 294 pinctrl-names = "default"; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>; 298 gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>; 299 gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>; 300 cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW 301 &gpio1 8 GPIO_ACTIVE_HIGH>; 302 num-chipselects = <2>; 303 304 flash@0 { 305 compatible = "m25p128", "jedec,spi-nor"; 306 #address-cells = <1>; 307 #size-cells = <1>; 308 reg = <0>; 309 spi-max-frequency = <1000000>; 310 }; 311 312 at93c46d@1 { 313 compatible = "atmel,at93c46d"; 314 pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>; 315 pinctrl-names = "default"; 316 reg = <1>; 317 spi-max-frequency = <500000>; 318 spi-cs-high; 319 data-size = <16>; 320 select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; 321 }; 322 }; 323 }; 324 325 &i2c0 { 326 gpio5: io-expander@20 { 327 compatible = "nxp,pca9554"; 328 reg = <0x20>; 329 gpio-controller; 330 #gpio-cells = <2>; 331 332 }; 333 334 gpio6: io-expander@22 { 335 compatible = "nxp,pca9554"; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_pca9554_22>; 338 reg = <0x22>; 339 gpio-controller; 340 #gpio-cells = <2>; 341 interrupt-controller; 342 interrupt-parent = <&gpio3>; 343 interrupts = <2 IRQ_TYPE_LEVEL_LOW>; 344 }; 345 }; 346 347 &i2c2 { 348 tca9548@70 { 349 compatible = "nxp,pca9548"; 350 pinctrl-0 = <&pinctrl_i2c_mux_reset>; 351 pinctrl-names = "default"; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 reg = <0x70>; 355 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 356 357 i2c@0 { 358 #address-cells = <1>; 359 #size-cells = <0>; 360 reg = <0>; 361 362 sfp1: eeprom@50 { 363 compatible = "atmel,24c02"; 364 reg = <0x50>; 365 }; 366 }; 367 368 i2c@1 { 369 #address-cells = <1>; 370 #size-cells = <0>; 371 reg = <1>; 372 373 sfp2: eeprom@50 { 374 compatible = "atmel,24c02"; 375 reg = <0x50>; 376 }; 377 }; 378 379 i2c@2 { 380 #address-cells = <1>; 381 #size-cells = <0>; 382 reg = <2>; 383 384 sfp3: eeprom@50 { 385 compatible = "atmel,24c02"; 386 reg = <0x50>; 387 }; 388 }; 389 390 i2c@3 { 391 #address-cells = <1>; 392 #size-cells = <0>; 393 reg = <3>; 394 395 sfp4: eeprom@50 { 396 compatible = "atmel,24c02"; 397 reg = <0x50>; 398 }; 399 }; 400 401 i2c@4 { 402 #address-cells = <1>; 403 #size-cells = <0>; 404 reg = <4>; 405 }; 406 }; 407 }; 408 409 &mdio1 { 410 clock-frequency = <5000000>; 411 }; 412 413 &iomuxc { 414 pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 { 415 fsl,pins = < 416 VF610_PAD_PTE27__GPIO_132 0x33e2 417 >; 418 }; 419 420 pinctrl_gpio_spi0: pinctrl-gpio-spi0 { 421 fsl,pins = < 422 VF610_PAD_PTB22__GPIO_44 0x33e2 423 VF610_PAD_PTB21__GPIO_43 0x33e2 424 VF610_PAD_PTB20__GPIO_42 0x33e1 425 VF610_PAD_PTB19__GPIO_41 0x33e2 426 VF610_PAD_PTB18__GPIO_40 0x33e2 427 >; 428 }; 429 430 pinctrl_mdio_mux: pinctrl-mdio-mux { 431 fsl,pins = < 432 VF610_PAD_PTA18__GPIO_8 0x31c2 433 VF610_PAD_PTA19__GPIO_9 0x31c2 434 VF610_PAD_PTB2__GPIO_24 0x31c2 435 VF610_PAD_PTB3__GPIO_25 0x31c2 436 >; 437 }; 438 439 pinctrl_pca9554_22: pinctrl-pca95540-22 { 440 fsl,pins = < 441 VF610_PAD_PTB28__GPIO_98 0x219d 442 >; 443 }; 444 };
Cache object: 75f1814e1a2b3fb034171a6f921e2514
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