Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/contrib/device-tree/src/arm/vf610-zii-scu4-aib.dts
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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 // 3 // Copyright (C) 2016-2018 Zodiac Inflight Innovations 4 5 /dts-v1/; 6 #include "vf610.dtsi" 7 8 / { 9 model = "ZII VF610 SCU4 AIB"; 10 compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610"; 11 12 chosen { 13 stdout-path = &uart0; 14 }; 15 16 memory@80000000 { 17 device_type = "memory"; 18 reg = <0x80000000 0x20000000>; 19 }; 20 21 gpio-leds { 22 compatible = "gpio-leds"; 23 pinctrl-0 = <&pinctrl_leds_debug>; 24 pinctrl-names = "default"; 25 26 debug { 27 label = "zii:green:debug1"; 28 gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; 29 linux,default-trigger = "heartbeat"; 30 }; 31 }; 32 33 mdio-mux { 34 compatible = "mdio-mux-gpio"; 35 pinctrl-0 = <&pinctrl_mdio_mux>; 36 pinctrl-names = "default"; 37 gpios = <&gpio4 4 GPIO_ACTIVE_HIGH 38 &gpio4 5 GPIO_ACTIVE_HIGH 39 &gpio3 30 GPIO_ACTIVE_HIGH 40 &gpio3 31 GPIO_ACTIVE_HIGH>; 41 mdio-parent-bus = <&mdio1>; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 45 mdio_mux_1: mdio@1 { 46 reg = <1>; 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 switch0: switch0@0 { 51 compatible = "marvell,mv88e6190"; 52 reg = <0>; 53 dsa,member = <0 0>; 54 eeprom-length = <65536>; 55 56 ports { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 port@0 { 61 reg = <0>; 62 label = "cpu"; 63 ethernet = <&fec1>; 64 65 fixed-link { 66 speed = <100>; 67 full-duplex; 68 }; 69 }; 70 71 port@1 { 72 reg = <1>; 73 label = "aib2main_1"; 74 }; 75 76 port@2 { 77 reg = <2>; 78 label = "aib2main_2"; 79 }; 80 81 port@3 { 82 reg = <3>; 83 label = "eth_cu_1000_5"; 84 }; 85 86 port@4 { 87 reg = <4>; 88 label = "eth_cu_1000_6"; 89 }; 90 91 port@5 { 92 reg = <5>; 93 label = "eth_cu_1000_4"; 94 }; 95 96 port@6 { 97 reg = <6>; 98 label = "eth_cu_1000_7"; 99 }; 100 101 port@7 { 102 reg = <7>; 103 label = "modem_pic"; 104 105 fixed-link { 106 speed = <100>; 107 full-duplex; 108 }; 109 }; 110 111 switch0port10: port@10 { 112 reg = <10>; 113 label = "dsa"; 114 phy-mode = "xgmii"; 115 link = <&switch1port10 116 &switch3port10 117 &switch2port10>; 118 }; 119 }; 120 }; 121 }; 122 123 mdio_mux_2: mdio@2 { 124 reg = <2>; 125 #address-cells = <1>; 126 #size-cells = <0>; 127 128 switch1: switch1@0 { 129 compatible = "marvell,mv88e6190"; 130 reg = <0>; 131 dsa,member = <0 1>; 132 eeprom-length = <65536>; 133 134 ports { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 port@1 { 139 reg = <1>; 140 label = "eth_cu_1000_3"; 141 }; 142 143 port@2 { 144 reg = <2>; 145 label = "eth_cu_100_2"; 146 }; 147 148 port@3 { 149 reg = <3>; 150 label = "eth_cu_100_3"; 151 }; 152 153 switch1port9: port@9 { 154 reg = <9>; 155 label = "dsa"; 156 phy-mode = "xgmii"; 157 link = <&switch3port10 158 &switch2port10>; 159 }; 160 161 switch1port10: port@10 { 162 reg = <10>; 163 label = "dsa"; 164 phy-mode = "xgmii"; 165 link = <&switch0port10>; 166 }; 167 }; 168 }; 169 }; 170 171 mdio_mux_4: mdio@4 { 172 reg = <4>; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 176 switch2: switch2@0 { 177 compatible = "marvell,mv88e6190"; 178 reg = <0>; 179 dsa,member = <0 2>; 180 eeprom-length = <65536>; 181 182 ports { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 186 port@2 { 187 reg = <2>; 188 label = "eth_fc_1000_2"; 189 phy-mode = "1000base-x"; 190 managed = "in-band-status"; 191 sfp = <&sff1>; 192 }; 193 194 port@3 { 195 reg = <3>; 196 label = "eth_fc_1000_3"; 197 phy-mode = "1000base-x"; 198 managed = "in-band-status"; 199 sfp = <&sff2>; 200 }; 201 202 port@4 { 203 reg = <4>; 204 label = "eth_fc_1000_4"; 205 phy-mode = "1000base-x"; 206 managed = "in-band-status"; 207 sfp = <&sff3>; 208 }; 209 210 port@5 { 211 reg = <5>; 212 label = "eth_fc_1000_5"; 213 phy-mode = "1000base-x"; 214 managed = "in-band-status"; 215 sfp = <&sff4>; 216 }; 217 218 port@6 { 219 reg = <6>; 220 label = "eth_fc_1000_6"; 221 phy-mode = "1000base-x"; 222 managed = "in-band-status"; 223 sfp = <&sff5>; 224 }; 225 226 port@7 { 227 reg = <7>; 228 label = "eth_fc_1000_7"; 229 phy-mode = "1000base-x"; 230 managed = "in-band-status"; 231 sfp = <&sff6>; 232 }; 233 234 port@9 { 235 reg = <9>; 236 label = "eth_fc_1000_1"; 237 phy-mode = "1000base-x"; 238 managed = "in-band-status"; 239 sfp = <&sff0>; 240 }; 241 242 switch2port10: port@10 { 243 reg = <10>; 244 label = "dsa"; 245 phy-mode = "2500base-x"; 246 link = <&switch3port9 247 &switch1port9 248 &switch0port10>; 249 }; 250 }; 251 }; 252 }; 253 254 mdio_mux_8: mdio@8 { 255 reg = <8>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 259 switch3: switch3@0 { 260 compatible = "marvell,mv88e6190"; 261 reg = <0>; 262 dsa,member = <0 3>; 263 eeprom-length = <65536>; 264 265 ports { 266 #address-cells = <1>; 267 #size-cells = <0>; 268 269 port@2 { 270 reg = <2>; 271 label = "eth_fc_1000_8"; 272 phy-mode = "1000base-x"; 273 managed = "in-band-status"; 274 sfp = <&sff7>; 275 }; 276 277 port@3 { 278 reg = <3>; 279 label = "eth_fc_1000_9"; 280 phy-mode = "1000base-x"; 281 managed = "in-band-status"; 282 sfp = <&sff8>; 283 }; 284 285 port@4 { 286 reg = <4>; 287 label = "eth_fc_1000_10"; 288 phy-mode = "1000base-x"; 289 managed = "in-band-status"; 290 sfp = <&sff9>; 291 }; 292 293 switch3port9: port@9 { 294 reg = <9>; 295 label = "dsa"; 296 phy-mode = "2500base-x"; 297 link = <&switch2port10>; 298 }; 299 300 switch3port10: port@10 { 301 reg = <10>; 302 label = "dsa"; 303 phy-mode = "xgmii"; 304 link = <&switch1port9 305 &switch0port10>; 306 }; 307 }; 308 }; 309 }; 310 }; 311 312 sff0: sff0 { 313 compatible = "sff,sff"; 314 i2c-bus = <&sff0_i2c>; 315 los-gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>; 316 tx-disable-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; 317 }; 318 319 sff1: sff1 { 320 compatible = "sff,sff"; 321 i2c-bus = <&sff1_i2c>; 322 los-gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>; 323 tx-disable-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 324 }; 325 326 sff2: sff2 { 327 compatible = "sff,sff"; 328 i2c-bus = <&sff2_i2c>; 329 los-gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>; 330 tx-disable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; 331 }; 332 333 sff3: sff3 { 334 compatible = "sff,sff"; 335 i2c-bus = <&sff3_i2c>; 336 los-gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>; 337 tx-disable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; 338 }; 339 340 sff4: sff4 { 341 compatible = "sff,sff"; 342 i2c-bus = <&sff4_i2c>; 343 los-gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>; 344 tx-disable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; 345 }; 346 347 sff5: sff5 { 348 compatible = "sff,sff"; 349 i2c-bus = <&sff5_i2c>; 350 los-gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>; 351 tx-disable-gpios = <&gpio7 5 GPIO_ACTIVE_HIGH>; 352 }; 353 354 sff6: sff6 { 355 compatible = "sff,sff"; 356 i2c-bus = <&sff6_i2c>; 357 los-gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>; 358 tx-disable-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; 359 }; 360 361 sff7: sff7 { 362 compatible = "sff,sff"; 363 i2c-bus = <&sff7_i2c>; 364 los-gpios = <&gpio9 7 GPIO_ACTIVE_HIGH>; 365 tx-disable-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; 366 }; 367 368 sff8: sff8 { 369 compatible = "sff,sff"; 370 i2c-bus = <&sff8_i2c>; 371 los-gpios = <&gpio9 8 GPIO_ACTIVE_HIGH>; 372 tx-disable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; 373 }; 374 375 sff9: sff9 { 376 compatible = "sff,sff"; 377 i2c-bus = <&sff9_i2c>; 378 los-gpios = <&gpio9 9 GPIO_ACTIVE_HIGH>; 379 tx-disable-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; 380 }; 381 382 reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { 383 compatible = "regulator-fixed"; 384 regulator-name = "vcc_3v3_mcu"; 385 regulator-min-microvolt = <3300000>; 386 regulator-max-microvolt = <3300000>; 387 }; 388 }; 389 390 &dspi0 { 391 pinctrl-0 = <&pinctrl_dspi0>; 392 pinctrl-names = "default"; 393 bus-num = <0>; 394 status = "okay"; 395 396 adc@5 { 397 compatible = "holt,hi8435"; 398 reg = <5>; 399 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; 400 spi-max-frequency = <1000000>; 401 }; 402 }; 403 404 &dspi1 { 405 bus-num = <1>; 406 pinctrl-names = "default"; 407 pinctrl-0 = <&pinctrl_dspi1>; 408 status = "okay"; 409 410 flash@0 { 411 #address-cells = <1>; 412 #size-cells = <1>; 413 compatible = "jedec,spi-nor"; 414 reg = <0>; 415 spi-max-frequency = <50000000>; 416 417 partition@0 { 418 label = "m25p128-0"; 419 reg = <0x0 0x01000000>; 420 }; 421 }; 422 423 flash@1 { 424 #address-cells = <1>; 425 #size-cells = <1>; 426 compatible = "jedec,spi-nor"; 427 reg = <1>; 428 spi-max-frequency = <50000000>; 429 430 partition@0 { 431 label = "m25p128-1"; 432 reg = <0x0 0x01000000>; 433 }; 434 }; 435 }; 436 437 &adc0 { 438 vref-supply = <®_vcc_3v3_mcu>; 439 status = "okay"; 440 }; 441 442 &adc1 { 443 vref-supply = <®_vcc_3v3_mcu>; 444 status = "okay"; 445 }; 446 447 &edma0 { 448 status = "okay"; 449 }; 450 451 &edma1 { 452 status = "okay"; 453 }; 454 455 &esdhc0 { 456 pinctrl-names = "default"; 457 pinctrl-0 = <&pinctrl_esdhc0>; 458 bus-width = <8>; 459 non-removable; 460 no-1-8-v; 461 no-sd; 462 no-sdio; 463 keep-power-in-suspend; 464 status = "okay"; 465 }; 466 467 &esdhc1 { 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pinctrl_esdhc1>; 470 bus-width = <4>; 471 no-sdio; 472 status = "okay"; 473 }; 474 475 &fec1 { 476 phy-mode = "rmii"; 477 pinctrl-names = "default"; 478 pinctrl-0 = <&pinctrl_fec1>; 479 status = "okay"; 480 481 fixed-link { 482 speed = <100>; 483 full-duplex; 484 }; 485 486 mdio1: mdio { 487 #address-cells = <1>; 488 #size-cells = <0>; 489 }; 490 }; 491 492 &i2c0 { 493 clock-frequency = <100000>; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&pinctrl_i2c0>; 496 status = "okay"; 497 498 gpio5: io-expander@20 { 499 compatible = "nxp,pca9554"; 500 reg = <0x20>; 501 gpio-controller; 502 #gpio-cells = <2>; 503 }; 504 505 gpio6: io-expander@22 { 506 compatible = "nxp,pca9554"; 507 reg = <0x22>; 508 gpio-controller; 509 #gpio-cells = <2>; 510 }; 511 512 temp-sensor@48 { 513 compatible = "national,lm75"; 514 reg = <0x48>; 515 }; 516 517 eeprom@50 { 518 compatible = "atmel,24c04"; 519 reg = <0x50>; 520 }; 521 522 eeprom@52 { 523 compatible = "atmel,24c04"; 524 reg = <0x52>; 525 }; 526 527 elapsed-time-recorder@6b { 528 compatible = "dallas,ds1682"; 529 reg = <0x6b>; 530 }; 531 }; 532 533 &i2c1 { 534 clock-frequency = <100000>; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&pinctrl_i2c1>; 537 status = "okay"; 538 539 watchdog@38 { 540 compatible = "zii,rave-wdt"; 541 reg = <0x38>; 542 }; 543 544 adc@4a { 545 compatible = "adi,adt7411"; 546 reg = <0x4a>; 547 }; 548 }; 549 550 &i2c2 { 551 clock-frequency = <100000>; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&pinctrl_i2c2>; 554 status = "okay"; 555 556 gpio9: io-expander@20 { 557 compatible = "semtech,sx1503q"; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&pinctrl_sx1503_20>; 560 #gpio-cells = <2>; 561 reg = <0x20>; 562 gpio-controller; 563 interrupt-parent = <&gpio1>; 564 interrupts = <31 IRQ_TYPE_EDGE_FALLING>; 565 }; 566 567 temp-sensor@4e { 568 compatible = "national,lm75"; 569 reg = <0x4e>; 570 }; 571 572 temp-sensor@4f { 573 compatible = "national,lm75"; 574 reg = <0x4f>; 575 }; 576 577 gpio7: io-expander@23 { 578 compatible = "nxp,pca9555"; 579 gpio-controller; 580 #gpio-cells = <2>; 581 reg = <0x23>; 582 }; 583 584 adc@4a { 585 compatible = "adi,adt7411"; 586 reg = <0x4a>; 587 }; 588 589 eeprom@54 { 590 compatible = "atmel,24c08"; 591 reg = <0x54>; 592 }; 593 594 i2c-mux@70 { 595 compatible = "nxp,pca9548"; 596 pinctrl-names = "default"; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 reg = <0x70>; 600 i2c-mux-idle-disconnect; 601 602 sff0_i2c: i2c@1 { 603 #address-cells = <1>; 604 #size-cells = <0>; 605 reg = <1>; 606 }; 607 608 sff1_i2c: i2c@2 { 609 #address-cells = <1>; 610 #size-cells = <0>; 611 reg = <2>; 612 }; 613 614 sff2_i2c: i2c@3 { 615 #address-cells = <1>; 616 #size-cells = <0>; 617 reg = <3>; 618 }; 619 620 sff3_i2c: i2c@4 { 621 #address-cells = <1>; 622 #size-cells = <0>; 623 reg = <4>; 624 }; 625 626 sff4_i2c: i2c@5 { 627 #address-cells = <1>; 628 #size-cells = <0>; 629 reg = <5>; 630 }; 631 }; 632 633 i2c-mux@71 { 634 compatible = "nxp,pca9548"; 635 pinctrl-names = "default"; 636 reg = <0x71>; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 i2c-mux-idle-disconnect; 640 641 sff5_i2c: i2c@1 { 642 #address-cells = <1>; 643 #size-cells = <0>; 644 reg = <1>; 645 }; 646 647 sff6_i2c: i2c@2 { 648 #address-cells = <1>; 649 #size-cells = <0>; 650 reg = <2>; 651 }; 652 653 sff7_i2c: i2c@3 { 654 #address-cells = <1>; 655 #size-cells = <0>; 656 reg = <3>; 657 }; 658 659 sff8_i2c: i2c@4 { 660 #address-cells = <1>; 661 #size-cells = <0>; 662 reg = <4>; 663 }; 664 665 sff9_i2c: i2c@5 { 666 #address-cells = <1>; 667 #size-cells = <0>; 668 reg = <5>; 669 }; 670 }; 671 }; 672 673 &snvsrtc { 674 status = "disabled"; 675 }; 676 677 &uart0 { 678 pinctrl-names = "default"; 679 pinctrl-0 = <&pinctrl_uart0>; 680 status = "okay"; 681 }; 682 683 &uart1 { 684 linux,rs485-enabled-at-boot-time; 685 pinctrl-names = "default"; 686 pinctrl-0 = <&pinctrl_uart1>; 687 status = "okay"; 688 }; 689 690 &uart2 { 691 linux,rs485-enabled-at-boot-time; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&pinctrl_uart2>; 694 status = "okay"; 695 }; 696 697 &iomuxc { 698 pinctrl_dspi0: dspi0grp { 699 fsl,pins = < 700 VF610_PAD_PTB19__DSPI0_CS0 0x1182 701 VF610_PAD_PTB18__DSPI0_CS1 0x1182 702 VF610_PAD_PTB13__DSPI0_CS4 0x1182 703 VF610_PAD_PTB12__DSPI0_CS5 0x1182 704 VF610_PAD_PTB20__DSPI0_SIN 0x1181 705 VF610_PAD_PTB21__DSPI0_SOUT 0x1182 706 VF610_PAD_PTB22__DSPI0_SCK 0x1182 707 >; 708 }; 709 710 pinctrl_dspi1: dspi1grp { 711 fsl,pins = < 712 VF610_PAD_PTD5__DSPI1_CS0 0x1182 713 VF610_PAD_PTD4__DSPI1_CS1 0x1182 714 VF610_PAD_PTC6__DSPI1_SIN 0x1181 715 VF610_PAD_PTC7__DSPI1_SOUT 0x1182 716 VF610_PAD_PTC8__DSPI1_SCK 0x1182 717 >; 718 }; 719 720 pinctrl_dspi2: dspi2gpio { 721 fsl,pins = < 722 VF610_PAD_PTD30__GPIO_64 0x33e2 723 VF610_PAD_PTD29__GPIO_65 0x33e1 724 VF610_PAD_PTD28__GPIO_66 0x33e2 725 VF610_PAD_PTD27__GPIO_67 0x33e2 726 VF610_PAD_PTD26__GPIO_68 0x31c2 727 >; 728 }; 729 730 pinctrl_esdhc0: esdhc0grp { 731 fsl,pins = < 732 VF610_PAD_PTC0__ESDHC0_CLK 0x31ef 733 VF610_PAD_PTC1__ESDHC0_CMD 0x31ef 734 VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef 735 VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef 736 VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef 737 VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef 738 VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef 739 VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef 740 VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef 741 VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef 742 >; 743 }; 744 745 pinctrl_esdhc1: esdhc1grp { 746 fsl,pins = < 747 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef 748 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef 749 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef 750 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef 751 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef 752 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef 753 >; 754 }; 755 756 pinctrl_fec1: fec1grp { 757 fsl,pins = < 758 VF610_PAD_PTA6__RMII_CLKIN 0x30d1 759 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 760 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 761 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 762 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 763 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 764 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 765 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 766 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 767 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 768 >; 769 }; 770 771 pinctrl_i2c0: i2c0grp { 772 fsl,pins = < 773 VF610_PAD_PTB14__I2C0_SCL 0x37ff 774 VF610_PAD_PTB15__I2C0_SDA 0x37ff 775 >; 776 }; 777 778 pinctrl_i2c1: i2c1grp { 779 fsl,pins = < 780 VF610_PAD_PTB16__I2C1_SCL 0x37ff 781 VF610_PAD_PTB17__I2C1_SDA 0x37ff 782 >; 783 }; 784 785 pinctrl_i2c2: i2c2grp { 786 fsl,pins = < 787 VF610_PAD_PTA22__I2C2_SCL 0x37ff 788 VF610_PAD_PTA23__I2C2_SDA 0x37ff 789 >; 790 }; 791 792 pinctrl_leds_debug: pinctrl-leds-debug { 793 fsl,pins = < 794 VF610_PAD_PTB26__GPIO_96 0x31c2 795 >; 796 }; 797 798 pinctrl_mdio_mux: pinctrl-mdio-mux { 799 fsl,pins = < 800 VF610_PAD_PTE27__GPIO_132 0x31c2 801 VF610_PAD_PTE28__GPIO_133 0x31c2 802 VF610_PAD_PTE21__GPIO_126 0x31c2 803 VF610_PAD_PTE22__GPIO_127 0x31c2 804 >; 805 }; 806 807 pinctrl_qspi0: qspi0grp { 808 fsl,pins = < 809 VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3 810 VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff 811 VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3 812 VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3 813 VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3 814 VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3 815 >; 816 }; 817 818 pinctrl_sx1503_20: pinctrl-sx1503-20 { 819 fsl,pins = < 820 VF610_PAD_PTD31__GPIO_63 0x219d 821 >; 822 }; 823 824 pinctrl_uart0: uart0grp { 825 fsl,pins = < 826 VF610_PAD_PTB10__UART0_TX 0x21a2 827 VF610_PAD_PTB11__UART0_RX 0x21a1 828 >; 829 }; 830 831 pinctrl_uart1: uart1grp { 832 fsl,pins = < 833 VF610_PAD_PTB23__UART1_TX 0x21a2 834 VF610_PAD_PTB24__UART1_RX 0x21a1 835 VF610_PAD_PTB25__UART1_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */ 836 >; 837 }; 838 839 pinctrl_uart2: uart2grp { 840 fsl,pins = < 841 VF610_PAD_PTD0__UART2_TX 0x21a2 842 VF610_PAD_PTD1__UART2_RX 0x21a1 843 VF610_PAD_PTD2__UART2_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */ 844 >; 845 }; 846 };
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