Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/wm8650.dtsi
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1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC 4 * 5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> 6 */ 7 8 / { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 compatible = "wm,wm8650"; 12 13 cpus { 14 #address-cells = <0>; 15 #size-cells = <0>; 16 17 cpu { 18 device_type = "cpu"; 19 compatible = "arm,arm926ej-s"; 20 }; 21 }; 22 23 memory { 24 device_type = "memory"; 25 reg = <0x0 0x0>; 26 }; 27 28 aliases { 29 serial0 = &uart0; 30 serial1 = &uart1; 31 }; 32 33 soc { 34 #address-cells = <1>; 35 #size-cells = <1>; 36 compatible = "simple-bus"; 37 ranges; 38 interrupt-parent = <&intc0>; 39 40 intc0: interrupt-controller@d8140000 { 41 compatible = "via,vt8500-intc"; 42 interrupt-controller; 43 reg = <0xd8140000 0x10000>; 44 #interrupt-cells = <1>; 45 }; 46 47 /* Secondary IC cascaded to intc0 */ 48 intc1: interrupt-controller@d8150000 { 49 compatible = "via,vt8500-intc"; 50 interrupt-controller; 51 #interrupt-cells = <1>; 52 reg = <0xD8150000 0x10000>; 53 interrupts = <56 57 58 59 60 61 62 63>; 54 }; 55 56 pinctrl: pinctrl@d8110000 { 57 compatible = "wm,wm8650-pinctrl"; 58 reg = <0xd8110000 0x10000>; 59 interrupt-controller; 60 #interrupt-cells = <2>; 61 gpio-controller; 62 #gpio-cells = <2>; 63 }; 64 65 pmc@d8130000 { 66 compatible = "via,vt8500-pmc"; 67 reg = <0xd8130000 0x1000>; 68 69 clocks { 70 #address-cells = <1>; 71 #size-cells = <0>; 72 73 ref25: ref25M { 74 #clock-cells = <0>; 75 compatible = "fixed-clock"; 76 clock-frequency = <25000000>; 77 }; 78 79 ref24: ref24M { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <24000000>; 83 }; 84 85 plla: plla { 86 #clock-cells = <0>; 87 compatible = "wm,wm8650-pll-clock"; 88 clocks = <&ref25>; 89 reg = <0x200>; 90 }; 91 92 pllb: pllb { 93 #clock-cells = <0>; 94 compatible = "wm,wm8650-pll-clock"; 95 clocks = <&ref25>; 96 reg = <0x204>; 97 }; 98 99 pllc: pllc { 100 #clock-cells = <0>; 101 compatible = "wm,wm8650-pll-clock"; 102 clocks = <&ref25>; 103 reg = <0x208>; 104 }; 105 106 plld: plld { 107 #clock-cells = <0>; 108 compatible = "wm,wm8650-pll-clock"; 109 clocks = <&ref25>; 110 reg = <0x20c>; 111 }; 112 113 plle: plle { 114 #clock-cells = <0>; 115 compatible = "wm,wm8650-pll-clock"; 116 clocks = <&ref25>; 117 reg = <0x210>; 118 }; 119 120 clkarm: arm { 121 #clock-cells = <0>; 122 compatible = "via,vt8500-device-clock"; 123 clocks = <&plla>; 124 divisor-reg = <0x300>; 125 }; 126 127 clkahb: ahb { 128 #clock-cells = <0>; 129 compatible = "via,vt8500-device-clock"; 130 clocks = <&pllb>; 131 divisor-reg = <0x304>; 132 }; 133 134 clkapb: apb { 135 #clock-cells = <0>; 136 compatible = "via,vt8500-device-clock"; 137 clocks = <&pllb>; 138 divisor-reg = <0x320>; 139 }; 140 141 clkddr: ddr { 142 #clock-cells = <0>; 143 compatible = "via,vt8500-device-clock"; 144 clocks = <&plld>; 145 divisor-reg = <0x310>; 146 }; 147 148 clkuart0: uart0 { 149 #clock-cells = <0>; 150 compatible = "via,vt8500-device-clock"; 151 clocks = <&ref24>; 152 enable-reg = <0x250>; 153 enable-bit = <1>; 154 }; 155 156 clkuart1: uart1 { 157 #clock-cells = <0>; 158 compatible = "via,vt8500-device-clock"; 159 clocks = <&ref24>; 160 enable-reg = <0x250>; 161 enable-bit = <2>; 162 }; 163 164 clksdhc: sdhc { 165 #clock-cells = <0>; 166 compatible = "via,vt8500-device-clock"; 167 clocks = <&pllb>; 168 divisor-reg = <0x328>; 169 divisor-mask = <0x3f>; 170 enable-reg = <0x254>; 171 enable-bit = <18>; 172 }; 173 }; 174 }; 175 176 timer@d8130100 { 177 compatible = "via,vt8500-timer"; 178 reg = <0xd8130100 0x28>; 179 interrupts = <36>; 180 }; 181 182 ehci@d8007900 { 183 compatible = "via,vt8500-ehci"; 184 reg = <0xd8007900 0x200>; 185 interrupts = <43>; 186 }; 187 188 uhci@d8007b00 { 189 compatible = "platform-uhci"; 190 reg = <0xd8007b00 0x200>; 191 interrupts = <43>; 192 }; 193 194 sdhc@d800a000 { 195 compatible = "wm,wm8505-sdhc"; 196 reg = <0xd800a000 0x400>; 197 interrupts = <20>, <21>; 198 clocks = <&clksdhc>; 199 bus-width = <4>; 200 sdon-inverted; 201 }; 202 203 fb: fb@d8050800 { 204 compatible = "wm,wm8505-fb"; 205 reg = <0xd8050800 0x200>; 206 }; 207 208 ge_rops@d8050400 { 209 compatible = "wm,prizm-ge-rops"; 210 reg = <0xd8050400 0x100>; 211 }; 212 213 uart0: serial@d8200000 { 214 compatible = "via,vt8500-uart"; 215 reg = <0xd8200000 0x1040>; 216 interrupts = <32>; 217 clocks = <&clkuart0>; 218 status = "disabled"; 219 }; 220 221 uart1: serial@d82b0000 { 222 compatible = "via,vt8500-uart"; 223 reg = <0xd82b0000 0x1040>; 224 interrupts = <33>; 225 clocks = <&clkuart1>; 226 status = "disabled"; 227 }; 228 229 rtc@d8100000 { 230 compatible = "via,vt8500-rtc"; 231 reg = <0xd8100000 0x10000>; 232 interrupts = <48>; 233 }; 234 235 ethernet@d8004000 { 236 compatible = "via,vt8500-rhine"; 237 reg = <0xd8004000 0x100>; 238 interrupts = <10>; 239 }; 240 }; 241 };
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