Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm/zynq-7000.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2011 - 2014 Xilinx 4 */ 5 6 / { 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "xlnx,zynq-7000"; 10 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 compatible = "arm,cortex-a9"; 17 device_type = "cpu"; 18 reg = <0>; 19 clocks = <&clkc 3>; 20 clock-latency = <1000>; 21 cpu0-supply = <®ulator_vccpint>; 22 operating-points = < 23 /* kHz uV */ 24 666667 1000000 25 333334 1000000 26 >; 27 }; 28 29 cpu1: cpu@1 { 30 compatible = "arm,cortex-a9"; 31 device_type = "cpu"; 32 reg = <1>; 33 clocks = <&clkc 3>; 34 }; 35 }; 36 37 fpga_full: fpga-full { 38 compatible = "fpga-region"; 39 fpga-mgr = <&devcfg>; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges; 43 }; 44 45 pmu@f8891000 { 46 compatible = "arm,cortex-a9-pmu"; 47 interrupts = <0 5 4>, <0 6 4>; 48 interrupt-parent = <&intc>; 49 reg = <0xf8891000 0x1000>, 50 <0xf8893000 0x1000>; 51 }; 52 53 regulator_vccpint: fixedregulator { 54 compatible = "regulator-fixed"; 55 regulator-name = "VCCPINT"; 56 regulator-min-microvolt = <1000000>; 57 regulator-max-microvolt = <1000000>; 58 regulator-boot-on; 59 regulator-always-on; 60 }; 61 62 replicator { 63 compatible = "arm,coresight-static-replicator"; 64 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 65 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 66 67 out-ports { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 /* replicator output ports */ 72 port@0 { 73 reg = <0>; 74 replicator_out_port0: endpoint { 75 remote-endpoint = <&tpiu_in_port>; 76 }; 77 }; 78 port@1 { 79 reg = <1>; 80 replicator_out_port1: endpoint { 81 remote-endpoint = <&etb_in_port>; 82 }; 83 }; 84 }; 85 in-ports { 86 /* replicator input port */ 87 port { 88 replicator_in_port0: endpoint { 89 remote-endpoint = <&funnel_out_port>; 90 }; 91 }; 92 }; 93 }; 94 95 amba: axi { 96 compatible = "simple-bus"; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 interrupt-parent = <&intc>; 100 ranges; 101 102 adc: adc@f8007100 { 103 compatible = "xlnx,zynq-xadc-1.00.a"; 104 reg = <0xf8007100 0x20>; 105 interrupts = <0 7 4>; 106 interrupt-parent = <&intc>; 107 clocks = <&clkc 12>; 108 }; 109 110 can0: can@e0008000 { 111 compatible = "xlnx,zynq-can-1.0"; 112 status = "disabled"; 113 clocks = <&clkc 19>, <&clkc 36>; 114 clock-names = "can_clk", "pclk"; 115 reg = <0xe0008000 0x1000>; 116 interrupts = <0 28 4>; 117 interrupt-parent = <&intc>; 118 tx-fifo-depth = <0x40>; 119 rx-fifo-depth = <0x40>; 120 }; 121 122 can1: can@e0009000 { 123 compatible = "xlnx,zynq-can-1.0"; 124 status = "disabled"; 125 clocks = <&clkc 20>, <&clkc 37>; 126 clock-names = "can_clk", "pclk"; 127 reg = <0xe0009000 0x1000>; 128 interrupts = <0 51 4>; 129 interrupt-parent = <&intc>; 130 tx-fifo-depth = <0x40>; 131 rx-fifo-depth = <0x40>; 132 }; 133 134 gpio0: gpio@e000a000 { 135 compatible = "xlnx,zynq-gpio-1.0"; 136 #gpio-cells = <2>; 137 clocks = <&clkc 42>; 138 gpio-controller; 139 interrupt-controller; 140 #interrupt-cells = <2>; 141 interrupt-parent = <&intc>; 142 interrupts = <0 20 4>; 143 reg = <0xe000a000 0x1000>; 144 }; 145 146 i2c0: i2c@e0004000 { 147 compatible = "cdns,i2c-r1p10"; 148 status = "disabled"; 149 clocks = <&clkc 38>; 150 interrupt-parent = <&intc>; 151 interrupts = <0 25 4>; 152 reg = <0xe0004000 0x1000>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 }; 156 157 i2c1: i2c@e0005000 { 158 compatible = "cdns,i2c-r1p10"; 159 status = "disabled"; 160 clocks = <&clkc 39>; 161 interrupt-parent = <&intc>; 162 interrupts = <0 48 4>; 163 reg = <0xe0005000 0x1000>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 }; 167 168 intc: interrupt-controller@f8f01000 { 169 compatible = "arm,cortex-a9-gic"; 170 #interrupt-cells = <3>; 171 interrupt-controller; 172 reg = <0xF8F01000 0x1000>, 173 <0xF8F00100 0x100>; 174 }; 175 176 L2: cache-controller@f8f02000 { 177 compatible = "arm,pl310-cache"; 178 reg = <0xF8F02000 0x1000>; 179 interrupts = <0 2 4>; 180 arm,data-latency = <3 2 2>; 181 arm,tag-latency = <2 2 2>; 182 cache-unified; 183 cache-level = <2>; 184 }; 185 186 mc: memory-controller@f8006000 { 187 compatible = "xlnx,zynq-ddrc-a05"; 188 reg = <0xf8006000 0x1000>; 189 }; 190 191 uart0: serial@e0000000 { 192 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 193 status = "disabled"; 194 clocks = <&clkc 23>, <&clkc 40>; 195 clock-names = "uart_clk", "pclk"; 196 reg = <0xE0000000 0x1000>; 197 interrupts = <0 27 4>; 198 }; 199 200 uart1: serial@e0001000 { 201 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 202 status = "disabled"; 203 clocks = <&clkc 24>, <&clkc 41>; 204 clock-names = "uart_clk", "pclk"; 205 reg = <0xE0001000 0x1000>; 206 interrupts = <0 50 4>; 207 }; 208 209 spi0: spi@e0006000 { 210 compatible = "xlnx,zynq-spi-r1p6"; 211 reg = <0xe0006000 0x1000>; 212 status = "disabled"; 213 interrupt-parent = <&intc>; 214 interrupts = <0 26 4>; 215 clocks = <&clkc 25>, <&clkc 34>; 216 clock-names = "ref_clk", "pclk"; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 }; 220 221 spi1: spi@e0007000 { 222 compatible = "xlnx,zynq-spi-r1p6"; 223 reg = <0xe0007000 0x1000>; 224 status = "disabled"; 225 interrupt-parent = <&intc>; 226 interrupts = <0 49 4>; 227 clocks = <&clkc 26>, <&clkc 35>; 228 clock-names = "ref_clk", "pclk"; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 }; 232 233 gem0: ethernet@e000b000 { 234 compatible = "cdns,zynq-gem", "cdns,gem"; 235 reg = <0xe000b000 0x1000>; 236 status = "disabled"; 237 interrupts = <0 22 4>; 238 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 239 clock-names = "pclk", "hclk", "tx_clk"; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 }; 243 244 gem1: ethernet@e000c000 { 245 compatible = "cdns,zynq-gem", "cdns,gem"; 246 reg = <0xe000c000 0x1000>; 247 status = "disabled"; 248 interrupts = <0 45 4>; 249 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 250 clock-names = "pclk", "hclk", "tx_clk"; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 }; 254 255 smcc: memory-controller@e000e000 { 256 compatible = "arm,pl353-smc-r2p1", "arm,primecell"; 257 reg = <0xe000e000 0x0001000>; 258 status = "disabled"; 259 clock-names = "memclk", "apb_pclk"; 260 clocks = <&clkc 11>, <&clkc 44>; 261 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ 262 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ 263 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ 264 #address-cells = <2>; 265 #size-cells = <1>; 266 267 nfc0: nand-controller@0,0 { 268 compatible = "arm,pl353-nand-r2p1"; 269 reg = <0 0 0x1000000>; 270 status = "disabled"; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 }; 274 }; 275 276 sdhci0: mmc@e0100000 { 277 compatible = "arasan,sdhci-8.9a"; 278 status = "disabled"; 279 clock-names = "clk_xin", "clk_ahb"; 280 clocks = <&clkc 21>, <&clkc 32>; 281 interrupt-parent = <&intc>; 282 interrupts = <0 24 4>; 283 reg = <0xe0100000 0x1000>; 284 }; 285 286 sdhci1: mmc@e0101000 { 287 compatible = "arasan,sdhci-8.9a"; 288 status = "disabled"; 289 clock-names = "clk_xin", "clk_ahb"; 290 clocks = <&clkc 22>, <&clkc 33>; 291 interrupt-parent = <&intc>; 292 interrupts = <0 47 4>; 293 reg = <0xe0101000 0x1000>; 294 }; 295 296 slcr: slcr@f8000000 { 297 #address-cells = <1>; 298 #size-cells = <1>; 299 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 300 reg = <0xF8000000 0x1000>; 301 ranges; 302 clkc: clkc@100 { 303 #clock-cells = <1>; 304 compatible = "xlnx,ps7-clkc"; 305 fclk-enable = <0>; 306 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 307 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 308 "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 309 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 310 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 311 "dma", "usb0_aper", "usb1_aper", "gem0_aper", 312 "gem1_aper", "sdio0_aper", "sdio1_aper", 313 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 314 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 315 "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 316 "dbg_trc", "dbg_apb"; 317 reg = <0x100 0x100>; 318 }; 319 320 rstc: rstc@200 { 321 compatible = "xlnx,zynq-reset"; 322 reg = <0x200 0x48>; 323 #reset-cells = <1>; 324 syscon = <&slcr>; 325 }; 326 327 pinctrl0: pinctrl@700 { 328 compatible = "xlnx,pinctrl-zynq"; 329 reg = <0x700 0x200>; 330 syscon = <&slcr>; 331 }; 332 }; 333 334 dmac_s: dmac@f8003000 { 335 compatible = "arm,pl330", "arm,primecell"; 336 reg = <0xf8003000 0x1000>; 337 interrupt-parent = <&intc>; 338 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", 339 "dma4", "dma5", "dma6", "dma7"; 340 interrupts = <0 13 4>, 341 <0 14 4>, <0 15 4>, 342 <0 16 4>, <0 17 4>, 343 <0 40 4>, <0 41 4>, 344 <0 42 4>, <0 43 4>; 345 #dma-cells = <1>; 346 clocks = <&clkc 27>; 347 clock-names = "apb_pclk"; 348 }; 349 350 devcfg: devcfg@f8007000 { 351 compatible = "xlnx,zynq-devcfg-1.0"; 352 reg = <0xf8007000 0x100>; 353 interrupt-parent = <&intc>; 354 interrupts = <0 8 4>; 355 clocks = <&clkc 12>; 356 clock-names = "ref_clk"; 357 syscon = <&slcr>; 358 }; 359 360 global_timer: timer@f8f00200 { 361 compatible = "arm,cortex-a9-global-timer"; 362 reg = <0xf8f00200 0x20>; 363 interrupts = <1 11 0x301>; 364 interrupt-parent = <&intc>; 365 clocks = <&clkc 4>; 366 }; 367 368 ttc0: timer@f8001000 { 369 interrupt-parent = <&intc>; 370 interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 371 compatible = "cdns,ttc"; 372 clocks = <&clkc 6>; 373 reg = <0xF8001000 0x1000>; 374 }; 375 376 ttc1: timer@f8002000 { 377 interrupt-parent = <&intc>; 378 interrupts = <0 37 4>, <0 38 4>, <0 39 4>; 379 compatible = "cdns,ttc"; 380 clocks = <&clkc 6>; 381 reg = <0xF8002000 0x1000>; 382 }; 383 384 scutimer: timer@f8f00600 { 385 interrupt-parent = <&intc>; 386 interrupts = <1 13 0x301>; 387 compatible = "arm,cortex-a9-twd-timer"; 388 reg = <0xf8f00600 0x20>; 389 clocks = <&clkc 4>; 390 }; 391 392 usb0: usb@e0002000 { 393 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 394 status = "disabled"; 395 clocks = <&clkc 28>; 396 interrupt-parent = <&intc>; 397 interrupts = <0 21 4>; 398 reg = <0xe0002000 0x1000>; 399 phy_type = "ulpi"; 400 }; 401 402 usb1: usb@e0003000 { 403 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 404 status = "disabled"; 405 clocks = <&clkc 29>; 406 interrupt-parent = <&intc>; 407 interrupts = <0 44 4>; 408 reg = <0xe0003000 0x1000>; 409 phy_type = "ulpi"; 410 }; 411 412 watchdog0: watchdog@f8005000 { 413 clocks = <&clkc 45>; 414 compatible = "cdns,wdt-r1p2"; 415 interrupt-parent = <&intc>; 416 interrupts = <0 9 1>; 417 reg = <0xf8005000 0x1000>; 418 timeout-sec = <10>; 419 }; 420 421 etb@f8801000 { 422 compatible = "arm,coresight-etb10", "arm,primecell"; 423 reg = <0xf8801000 0x1000>; 424 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 425 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 426 in-ports { 427 port { 428 etb_in_port: endpoint { 429 remote-endpoint = <&replicator_out_port1>; 430 }; 431 }; 432 }; 433 }; 434 435 tpiu@f8803000 { 436 compatible = "arm,coresight-tpiu", "arm,primecell"; 437 reg = <0xf8803000 0x1000>; 438 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 439 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 440 in-ports { 441 port { 442 tpiu_in_port: endpoint { 443 remote-endpoint = <&replicator_out_port0>; 444 }; 445 }; 446 }; 447 }; 448 449 funnel@f8804000 { 450 compatible = "arm,coresight-static-funnel", "arm,primecell"; 451 reg = <0xf8804000 0x1000>; 452 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 453 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 454 455 /* funnel output ports */ 456 out-ports { 457 port { 458 funnel_out_port: endpoint { 459 remote-endpoint = 460 <&replicator_in_port0>; 461 }; 462 }; 463 }; 464 465 in-ports { 466 #address-cells = <1>; 467 #size-cells = <0>; 468 469 /* funnel input ports */ 470 port@0 { 471 reg = <0>; 472 funnel0_in_port0: endpoint { 473 remote-endpoint = <&ptm0_out_port>; 474 }; 475 }; 476 477 port@1 { 478 reg = <1>; 479 funnel0_in_port1: endpoint { 480 remote-endpoint = <&ptm1_out_port>; 481 }; 482 }; 483 484 port@2 { 485 reg = <2>; 486 funnel0_in_port2: endpoint { 487 }; 488 }; 489 /* The other input ports are not connect to anything */ 490 }; 491 }; 492 493 ptm@f889c000 { 494 compatible = "arm,coresight-etm3x", "arm,primecell"; 495 reg = <0xf889c000 0x1000>; 496 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 497 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 498 cpu = <&cpu0>; 499 out-ports { 500 port { 501 ptm0_out_port: endpoint { 502 remote-endpoint = <&funnel0_in_port0>; 503 }; 504 }; 505 }; 506 }; 507 508 ptm@f889d000 { 509 compatible = "arm,coresight-etm3x", "arm,primecell"; 510 reg = <0xf889d000 0x1000>; 511 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 512 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 513 cpu = <&cpu1>; 514 out-ports { 515 port { 516 ptm1_out_port: endpoint { 517 remote-endpoint = <&funnel0_in_port1>; 518 }; 519 }; 520 }; 521 }; 522 }; 523 };
Cache object: 029e5366608deae0b86cc0ecae6707b3
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