sun50i-a64.dtsi

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    1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
    2 // Copyright (C) 2016 ARM Ltd.
    3 // based on the Allwinner H3 dtsi:
    4 //    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
    5 
    6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
    7 #include <dt-bindings/clock/sun6i-rtc.h>
    8 #include <dt-bindings/clock/sun8i-de2.h>
    9 #include <dt-bindings/clock/sun8i-r-ccu.h>
   10 #include <dt-bindings/interrupt-controller/arm-gic.h>
   11 #include <dt-bindings/reset/sun50i-a64-ccu.h>
   12 #include <dt-bindings/reset/sun8i-de2.h>
   13 #include <dt-bindings/reset/sun8i-r-ccu.h>
   14 #include <dt-bindings/thermal/thermal.h>
   15 
   16 / {
   17         interrupt-parent = <&gic>;
   18         #address-cells = <1>;
   19         #size-cells = <1>;
   20 
   21         chosen {
   22                 #address-cells = <1>;
   23                 #size-cells = <1>;
   24                 ranges;
   25 
   26                 simplefb_lcd: framebuffer-lcd {
   27                         compatible = "allwinner,simple-framebuffer",
   28                                      "simple-framebuffer";
   29                         allwinner,pipeline = "mixer0-lcd0";
   30                         clocks = <&ccu CLK_TCON0>,
   31                                  <&display_clocks CLK_MIXER0>;
   32                         status = "disabled";
   33                 };
   34 
   35                 simplefb_hdmi: framebuffer-hdmi {
   36                         compatible = "allwinner,simple-framebuffer",
   37                                      "simple-framebuffer";
   38                         allwinner,pipeline = "mixer1-lcd1-hdmi";
   39                         clocks = <&display_clocks CLK_MIXER1>,
   40                                  <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
   41                         status = "disabled";
   42                 };
   43         };
   44 
   45         cpus {
   46                 #address-cells = <1>;
   47                 #size-cells = <0>;
   48 
   49                 cpu0: cpu@0 {
   50                         compatible = "arm,cortex-a53";
   51                         device_type = "cpu";
   52                         reg = <0>;
   53                         enable-method = "psci";
   54                         next-level-cache = <&L2>;
   55                         clocks = <&ccu CLK_CPUX>;
   56                         clock-names = "cpu";
   57                         #cooling-cells = <2>;
   58                 };
   59 
   60                 cpu1: cpu@1 {
   61                         compatible = "arm,cortex-a53";
   62                         device_type = "cpu";
   63                         reg = <1>;
   64                         enable-method = "psci";
   65                         next-level-cache = <&L2>;
   66                         clocks = <&ccu CLK_CPUX>;
   67                         clock-names = "cpu";
   68                         #cooling-cells = <2>;
   69                 };
   70 
   71                 cpu2: cpu@2 {
   72                         compatible = "arm,cortex-a53";
   73                         device_type = "cpu";
   74                         reg = <2>;
   75                         enable-method = "psci";
   76                         next-level-cache = <&L2>;
   77                         clocks = <&ccu CLK_CPUX>;
   78                         clock-names = "cpu";
   79                         #cooling-cells = <2>;
   80                 };
   81 
   82                 cpu3: cpu@3 {
   83                         compatible = "arm,cortex-a53";
   84                         device_type = "cpu";
   85                         reg = <3>;
   86                         enable-method = "psci";
   87                         next-level-cache = <&L2>;
   88                         clocks = <&ccu CLK_CPUX>;
   89                         clock-names = "cpu";
   90                         #cooling-cells = <2>;
   91                 };
   92 
   93                 L2: l2-cache {
   94                         compatible = "cache";
   95                         cache-level = <2>;
   96                 };
   97         };
   98 
   99         de: display-engine {
  100                 compatible = "allwinner,sun50i-a64-display-engine";
  101                 allwinner,pipelines = <&mixer0>,
  102                                       <&mixer1>;
  103                 status = "disabled";
  104         };
  105 
  106         gpu_opp_table: opp-table-gpu {
  107                 compatible = "operating-points-v2";
  108 
  109                 opp-120000000 {
  110                         opp-hz = /bits/ 64 <120000000>;
  111                 };
  112 
  113                 opp-312000000 {
  114                         opp-hz = /bits/ 64 <312000000>;
  115                 };
  116 
  117                 opp-432000000 {
  118                         opp-hz = /bits/ 64 <432000000>;
  119                 };
  120         };
  121 
  122         osc24M: osc24M_clk {
  123                 #clock-cells = <0>;
  124                 compatible = "fixed-clock";
  125                 clock-frequency = <24000000>;
  126                 clock-output-names = "osc24M";
  127         };
  128 
  129         osc32k: osc32k_clk {
  130                 #clock-cells = <0>;
  131                 compatible = "fixed-clock";
  132                 clock-frequency = <32768>;
  133                 clock-output-names = "ext-osc32k";
  134         };
  135 
  136         pmu {
  137                 compatible = "arm,cortex-a53-pmu";
  138                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  139                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
  140                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
  141                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
  142                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  143         };
  144 
  145         psci {
  146                 compatible = "arm,psci-0.2";
  147                 method = "smc";
  148         };
  149 
  150         sound: sound {
  151                 #address-cells = <1>;
  152                 #size-cells = <0>;
  153                 compatible = "simple-audio-card";
  154                 simple-audio-card,name = "sun50i-a64-audio";
  155                 simple-audio-card,aux-devs = <&codec_analog>;
  156                 simple-audio-card,routing =
  157                                 "Left DAC", "DACL",
  158                                 "Right DAC", "DACR",
  159                                 "ADCL", "Left ADC",
  160                                 "ADCR", "Right ADC";
  161                 status = "disabled";
  162 
  163                 simple-audio-card,dai-link@0 {
  164                         format = "i2s";
  165                         frame-master = <&link0_cpu>;
  166                         bitclock-master = <&link0_cpu>;
  167                         mclk-fs = <128>;
  168 
  169                         link0_cpu: cpu {
  170                                 sound-dai = <&dai>;
  171                         };
  172 
  173                         link0_codec: codec {
  174                                 sound-dai = <&codec 0>;
  175                         };
  176                 };
  177         };
  178 
  179         timer {
  180                 compatible = "arm,armv8-timer";
  181                 allwinner,erratum-unknown1;
  182                 arm,no-tick-in-suspend;
  183                 interrupts = <GIC_PPI 13
  184                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  185                              <GIC_PPI 14
  186                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  187                              <GIC_PPI 11
  188                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  189                              <GIC_PPI 10
  190                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  191         };
  192 
  193         thermal-zones {
  194                 cpu_thermal: cpu0-thermal {
  195                         /* milliseconds */
  196                         polling-delay-passive = <0>;
  197                         polling-delay = <0>;
  198                         thermal-sensors = <&ths 0>;
  199 
  200                         cooling-maps {
  201                                 map0 {
  202                                         trip = <&cpu_alert0>;
  203                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  204                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  205                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  206                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  207                                 };
  208                                 map1 {
  209                                         trip = <&cpu_alert1>;
  210                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  211                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  212                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  213                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  214                                 };
  215                         };
  216 
  217                         trips {
  218                                 cpu_alert0: cpu_alert0 {
  219                                         /* milliCelsius */
  220                                         temperature = <75000>;
  221                                         hysteresis = <2000>;
  222                                         type = "passive";
  223                                 };
  224 
  225                                 cpu_alert1: cpu_alert1 {
  226                                         /* milliCelsius */
  227                                         temperature = <90000>;
  228                                         hysteresis = <2000>;
  229                                         type = "hot";
  230                                 };
  231 
  232                                 cpu_crit: cpu_crit {
  233                                         /* milliCelsius */
  234                                         temperature = <110000>;
  235                                         hysteresis = <2000>;
  236                                         type = "critical";
  237                                 };
  238                         };
  239                 };
  240 
  241                 gpu0_thermal: gpu0-thermal {
  242                         /* milliseconds */
  243                         polling-delay-passive = <0>;
  244                         polling-delay = <0>;
  245                         thermal-sensors = <&ths 1>;
  246                 };
  247 
  248                 gpu1_thermal: gpu1-thermal {
  249                         /* milliseconds */
  250                         polling-delay-passive = <0>;
  251                         polling-delay = <0>;
  252                         thermal-sensors = <&ths 2>;
  253                 };
  254         };
  255 
  256         soc {
  257                 compatible = "simple-bus";
  258                 #address-cells = <1>;
  259                 #size-cells = <1>;
  260                 ranges;
  261 
  262                 bus@1000000 {
  263                         compatible = "allwinner,sun50i-a64-de2";
  264                         reg = <0x1000000 0x400000>;
  265                         allwinner,sram = <&de2_sram 1>;
  266                         #address-cells = <1>;
  267                         #size-cells = <1>;
  268                         ranges = <0 0x1000000 0x400000>;
  269 
  270                         display_clocks: clock@0 {
  271                                 compatible = "allwinner,sun50i-a64-de2-clk";
  272                                 reg = <0x0 0x10000>;
  273                                 clocks = <&ccu CLK_BUS_DE>,
  274                                          <&ccu CLK_DE>;
  275                                 clock-names = "bus",
  276                                               "mod";
  277                                 resets = <&ccu RST_BUS_DE>;
  278                                 #clock-cells = <1>;
  279                                 #reset-cells = <1>;
  280                         };
  281 
  282                         rotate: rotate@20000 {
  283                                 compatible = "allwinner,sun50i-a64-de2-rotate",
  284                                              "allwinner,sun8i-a83t-de2-rotate";
  285                                 reg = <0x20000 0x10000>;
  286                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  287                                 clocks = <&display_clocks CLK_BUS_ROT>,
  288                                          <&display_clocks CLK_ROT>;
  289                                 clock-names = "bus",
  290                                               "mod";
  291                                 resets = <&display_clocks RST_ROT>;
  292                         };
  293 
  294                         mixer0: mixer@100000 {
  295                                 compatible = "allwinner,sun50i-a64-de2-mixer-0";
  296                                 reg = <0x100000 0x100000>;
  297                                 clocks = <&display_clocks CLK_BUS_MIXER0>,
  298                                          <&display_clocks CLK_MIXER0>;
  299                                 clock-names = "bus",
  300                                               "mod";
  301                                 resets = <&display_clocks RST_MIXER0>;
  302 
  303                                 ports {
  304                                         #address-cells = <1>;
  305                                         #size-cells = <0>;
  306 
  307                                         mixer0_out: port@1 {
  308                                                 #address-cells = <1>;
  309                                                 #size-cells = <0>;
  310                                                 reg = <1>;
  311 
  312                                                 mixer0_out_tcon0: endpoint@0 {
  313                                                         reg = <0>;
  314                                                         remote-endpoint = <&tcon0_in_mixer0>;
  315                                                 };
  316 
  317                                                 mixer0_out_tcon1: endpoint@1 {
  318                                                         reg = <1>;
  319                                                         remote-endpoint = <&tcon1_in_mixer0>;
  320                                                 };
  321                                         };
  322                                 };
  323                         };
  324 
  325                         mixer1: mixer@200000 {
  326                                 compatible = "allwinner,sun50i-a64-de2-mixer-1";
  327                                 reg = <0x200000 0x100000>;
  328                                 clocks = <&display_clocks CLK_BUS_MIXER1>,
  329                                          <&display_clocks CLK_MIXER1>;
  330                                 clock-names = "bus",
  331                                               "mod";
  332                                 resets = <&display_clocks RST_MIXER1>;
  333 
  334                                 ports {
  335                                         #address-cells = <1>;
  336                                         #size-cells = <0>;
  337 
  338                                         mixer1_out: port@1 {
  339                                                 #address-cells = <1>;
  340                                                 #size-cells = <0>;
  341                                                 reg = <1>;
  342 
  343                                                 mixer1_out_tcon0: endpoint@0 {
  344                                                         reg = <0>;
  345                                                         remote-endpoint = <&tcon0_in_mixer1>;
  346                                                 };
  347 
  348                                                 mixer1_out_tcon1: endpoint@1 {
  349                                                         reg = <1>;
  350                                                         remote-endpoint = <&tcon1_in_mixer1>;
  351                                                 };
  352                                         };
  353                                 };
  354                         };
  355                 };
  356 
  357                 syscon: syscon@1c00000 {
  358                         compatible = "allwinner,sun50i-a64-system-control";
  359                         reg = <0x01c00000 0x1000>;
  360                         #address-cells = <1>;
  361                         #size-cells = <1>;
  362                         ranges;
  363 
  364                         sram_c: sram@18000 {
  365                                 compatible = "mmio-sram";
  366                                 reg = <0x00018000 0x28000>;
  367                                 #address-cells = <1>;
  368                                 #size-cells = <1>;
  369                                 ranges = <0 0x00018000 0x28000>;
  370 
  371                                 de2_sram: sram-section@0 {
  372                                         compatible = "allwinner,sun50i-a64-sram-c";
  373                                         reg = <0x0000 0x28000>;
  374                                 };
  375                         };
  376 
  377                         sram_c1: sram@1d00000 {
  378                                 compatible = "mmio-sram";
  379                                 reg = <0x01d00000 0x40000>;
  380                                 #address-cells = <1>;
  381                                 #size-cells = <1>;
  382                                 ranges = <0 0x01d00000 0x40000>;
  383 
  384                                 ve_sram: sram-section@0 {
  385                                         compatible = "allwinner,sun50i-a64-sram-c1",
  386                                                      "allwinner,sun4i-a10-sram-c1";
  387                                         reg = <0x000000 0x40000>;
  388                                 };
  389                         };
  390                 };
  391 
  392                 dma: dma-controller@1c02000 {
  393                         compatible = "allwinner,sun50i-a64-dma";
  394                         reg = <0x01c02000 0x1000>;
  395                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
  396                         clocks = <&ccu CLK_BUS_DMA>;
  397                         dma-channels = <8>;
  398                         dma-requests = <27>;
  399                         resets = <&ccu RST_BUS_DMA>;
  400                         #dma-cells = <1>;
  401                 };
  402 
  403                 tcon0: lcd-controller@1c0c000 {
  404                         compatible = "allwinner,sun50i-a64-tcon-lcd",
  405                                      "allwinner,sun8i-a83t-tcon-lcd";
  406                         reg = <0x01c0c000 0x1000>;
  407                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  408                         clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
  409                         clock-names = "ahb", "tcon-ch0";
  410                         clock-output-names = "tcon-pixel-clock";
  411                         #clock-cells = <0>;
  412                         resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
  413                         reset-names = "lcd", "lvds";
  414 
  415                         ports {
  416                                 #address-cells = <1>;
  417                                 #size-cells = <0>;
  418 
  419                                 tcon0_in: port@0 {
  420                                         #address-cells = <1>;
  421                                         #size-cells = <0>;
  422                                         reg = <0>;
  423 
  424                                         tcon0_in_mixer0: endpoint@0 {
  425                                                 reg = <0>;
  426                                                 remote-endpoint = <&mixer0_out_tcon0>;
  427                                         };
  428 
  429                                         tcon0_in_mixer1: endpoint@1 {
  430                                                 reg = <1>;
  431                                                 remote-endpoint = <&mixer1_out_tcon0>;
  432                                         };
  433                                 };
  434 
  435                                 tcon0_out: port@1 {
  436                                         #address-cells = <1>;
  437                                         #size-cells = <0>;
  438                                         reg = <1>;
  439 
  440                                         tcon0_out_dsi: endpoint@1 {
  441                                                 reg = <1>;
  442                                                 remote-endpoint = <&dsi_in_tcon0>;
  443                                                 allwinner,tcon-channel = <1>;
  444                                         };
  445                                 };
  446                         };
  447                 };
  448 
  449                 tcon1: lcd-controller@1c0d000 {
  450                         compatible = "allwinner,sun50i-a64-tcon-tv",
  451                                      "allwinner,sun8i-a83t-tcon-tv";
  452                         reg = <0x01c0d000 0x1000>;
  453                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
  454                         clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
  455                         clock-names = "ahb", "tcon-ch1";
  456                         resets = <&ccu RST_BUS_TCON1>;
  457                         reset-names = "lcd";
  458 
  459                         ports {
  460                                 #address-cells = <1>;
  461                                 #size-cells = <0>;
  462 
  463                                 tcon1_in: port@0 {
  464                                         #address-cells = <1>;
  465                                         #size-cells = <0>;
  466                                         reg = <0>;
  467 
  468                                         tcon1_in_mixer0: endpoint@0 {
  469                                                 reg = <0>;
  470                                                 remote-endpoint = <&mixer0_out_tcon1>;
  471                                         };
  472 
  473                                         tcon1_in_mixer1: endpoint@1 {
  474                                                 reg = <1>;
  475                                                 remote-endpoint = <&mixer1_out_tcon1>;
  476                                         };
  477                                 };
  478 
  479                                 tcon1_out: port@1 {
  480                                         #address-cells = <1>;
  481                                         #size-cells = <0>;
  482                                         reg = <1>;
  483 
  484                                         tcon1_out_hdmi: endpoint@1 {
  485                                                 reg = <1>;
  486                                                 remote-endpoint = <&hdmi_in_tcon1>;
  487                                         };
  488                                 };
  489                         };
  490                 };
  491 
  492                 video-codec@1c0e000 {
  493                         compatible = "allwinner,sun50i-a64-video-engine";
  494                         reg = <0x01c0e000 0x1000>;
  495                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
  496                                  <&ccu CLK_DRAM_VE>;
  497                         clock-names = "ahb", "mod", "ram";
  498                         resets = <&ccu RST_BUS_VE>;
  499                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
  500                         allwinner,sram = <&ve_sram 1>;
  501                 };
  502 
  503                 mmc0: mmc@1c0f000 {
  504                         compatible = "allwinner,sun50i-a64-mmc";
  505                         reg = <0x01c0f000 0x1000>;
  506                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
  507                         clock-names = "ahb", "mmc";
  508                         resets = <&ccu RST_BUS_MMC0>;
  509                         reset-names = "ahb";
  510                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  511                         max-frequency = <150000000>;
  512                         status = "disabled";
  513                         #address-cells = <1>;
  514                         #size-cells = <0>;
  515                 };
  516 
  517                 mmc1: mmc@1c10000 {
  518                         compatible = "allwinner,sun50i-a64-mmc";
  519                         reg = <0x01c10000 0x1000>;
  520                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
  521                         clock-names = "ahb", "mmc";
  522                         resets = <&ccu RST_BUS_MMC1>;
  523                         reset-names = "ahb";
  524                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  525                         max-frequency = <150000000>;
  526                         status = "disabled";
  527                         #address-cells = <1>;
  528                         #size-cells = <0>;
  529                 };
  530 
  531                 mmc2: mmc@1c11000 {
  532                         compatible = "allwinner,sun50i-a64-emmc";
  533                         reg = <0x01c11000 0x1000>;
  534                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
  535                         clock-names = "ahb", "mmc";
  536                         resets = <&ccu RST_BUS_MMC2>;
  537                         reset-names = "ahb";
  538                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  539                         max-frequency = <150000000>;
  540                         status = "disabled";
  541                         #address-cells = <1>;
  542                         #size-cells = <0>;
  543                 };
  544 
  545                 sid: eeprom@1c14000 {
  546                         compatible = "allwinner,sun50i-a64-sid";
  547                         reg = <0x1c14000 0x400>;
  548                         #address-cells = <1>;
  549                         #size-cells = <1>;
  550 
  551                         ths_calibration: thermal-sensor-calibration@34 {
  552                                 reg = <0x34 0x8>;
  553                         };
  554                 };
  555 
  556                 crypto: crypto@1c15000 {
  557                         compatible = "allwinner,sun50i-a64-crypto";
  558                         reg = <0x01c15000 0x1000>;
  559                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
  560                         clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
  561                         clock-names = "bus", "mod";
  562                         resets = <&ccu RST_BUS_CE>;
  563                 };
  564 
  565                 msgbox: mailbox@1c17000 {
  566                         compatible = "allwinner,sun50i-a64-msgbox",
  567                                      "allwinner,sun6i-a31-msgbox";
  568                         reg = <0x01c17000 0x1000>;
  569                         clocks = <&ccu CLK_BUS_MSGBOX>;
  570                         resets = <&ccu RST_BUS_MSGBOX>;
  571                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
  572                         #mbox-cells = <1>;
  573                 };
  574 
  575                 usb_otg: usb@1c19000 {
  576                         compatible = "allwinner,sun8i-a33-musb";
  577                         reg = <0x01c19000 0x0400>;
  578                         clocks = <&ccu CLK_BUS_OTG>;
  579                         resets = <&ccu RST_BUS_OTG>;
  580                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  581                         interrupt-names = "mc";
  582                         phys = <&usbphy 0>;
  583                         phy-names = "usb";
  584                         extcon = <&usbphy 0>;
  585                         dr_mode = "otg";
  586                         status = "disabled";
  587                 };
  588 
  589                 usbphy: phy@1c19400 {
  590                         compatible = "allwinner,sun50i-a64-usb-phy";
  591                         reg = <0x01c19400 0x14>,
  592                               <0x01c1a800 0x4>,
  593                               <0x01c1b800 0x4>;
  594                         reg-names = "phy_ctrl",
  595                                     "pmu0",
  596                                     "pmu1";
  597                         clocks = <&ccu CLK_USB_PHY0>,
  598                                  <&ccu CLK_USB_PHY1>;
  599                         clock-names = "usb0_phy",
  600                                       "usb1_phy";
  601                         resets = <&ccu RST_USB_PHY0>,
  602                                  <&ccu RST_USB_PHY1>;
  603                         reset-names = "usb0_reset",
  604                                       "usb1_reset";
  605                         status = "disabled";
  606                         #phy-cells = <1>;
  607                 };
  608 
  609                 ehci0: usb@1c1a000 {
  610                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
  611                         reg = <0x01c1a000 0x100>;
  612                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  613                         clocks = <&ccu CLK_BUS_OHCI0>,
  614                                  <&ccu CLK_BUS_EHCI0>,
  615                                  <&ccu CLK_USB_OHCI0>;
  616                         resets = <&ccu RST_BUS_OHCI0>,
  617                                  <&ccu RST_BUS_EHCI0>;
  618                         phys = <&usbphy 0>;
  619                         phy-names = "usb";
  620                         status = "disabled";
  621                 };
  622 
  623                 ohci0: usb@1c1a400 {
  624                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
  625                         reg = <0x01c1a400 0x100>;
  626                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  627                         clocks = <&ccu CLK_BUS_OHCI0>,
  628                                  <&ccu CLK_USB_OHCI0>;
  629                         resets = <&ccu RST_BUS_OHCI0>;
  630                         phys = <&usbphy 0>;
  631                         phy-names = "usb";
  632                         status = "disabled";
  633                 };
  634 
  635                 ehci1: usb@1c1b000 {
  636                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
  637                         reg = <0x01c1b000 0x100>;
  638                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  639                         clocks = <&ccu CLK_BUS_OHCI1>,
  640                                  <&ccu CLK_BUS_EHCI1>,
  641                                  <&ccu CLK_USB_OHCI1>;
  642                         resets = <&ccu RST_BUS_OHCI1>,
  643                                  <&ccu RST_BUS_EHCI1>;
  644                         phys = <&usbphy 1>;
  645                         phy-names = "usb";
  646                         status = "disabled";
  647                 };
  648 
  649                 ohci1: usb@1c1b400 {
  650                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
  651                         reg = <0x01c1b400 0x100>;
  652                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  653                         clocks = <&ccu CLK_BUS_OHCI1>,
  654                                  <&ccu CLK_USB_OHCI1>;
  655                         resets = <&ccu RST_BUS_OHCI1>;
  656                         phys = <&usbphy 1>;
  657                         phy-names = "usb";
  658                         status = "disabled";
  659                 };
  660 
  661                 ccu: clock@1c20000 {
  662                         compatible = "allwinner,sun50i-a64-ccu";
  663                         reg = <0x01c20000 0x400>;
  664                         clocks = <&osc24M>, <&rtc CLK_OSC32K>;
  665                         clock-names = "hosc", "losc";
  666                         #clock-cells = <1>;
  667                         #reset-cells = <1>;
  668                 };
  669 
  670                 pio: pinctrl@1c20800 {
  671                         compatible = "allwinner,sun50i-a64-pinctrl";
  672                         reg = <0x01c20800 0x400>;
  673                         interrupt-parent = <&r_intc>;
  674                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  675                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
  676                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
  677                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
  678                                  <&rtc CLK_OSC32K>;
  679                         clock-names = "apb", "hosc", "losc";
  680                         gpio-controller;
  681                         #gpio-cells = <3>;
  682                         interrupt-controller;
  683                         #interrupt-cells = <3>;
  684 
  685                         /omit-if-no-ref/
  686                         aif2_pins: aif2-pins {
  687                                 pins = "PB4", "PB5", "PB6", "PB7";
  688                                 function = "aif2";
  689                         };
  690 
  691                         /omit-if-no-ref/
  692                         aif3_pins: aif3-pins {
  693                                 pins = "PG10", "PG11", "PG12", "PG13";
  694                                 function = "aif3";
  695                         };
  696 
  697                         csi_pins: csi-pins {
  698                                 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
  699                                        "PE7", "PE8", "PE9", "PE10", "PE11";
  700                                 function = "csi";
  701                         };
  702 
  703                         /omit-if-no-ref/
  704                         csi_mclk_pin: csi-mclk-pin {
  705                                 pins = "PE1";
  706                                 function = "csi";
  707                         };
  708 
  709                         i2c0_pins: i2c0-pins {
  710                                 pins = "PH0", "PH1";
  711                                 function = "i2c0";
  712                         };
  713 
  714                         i2c1_pins: i2c1-pins {
  715                                 pins = "PH2", "PH3";
  716                                 function = "i2c1";
  717                         };
  718 
  719                         i2c2_pins: i2c2-pins {
  720                                 pins = "PE14", "PE15";
  721                                 function = "i2c2";
  722                         };
  723 
  724                         /omit-if-no-ref/
  725                         lcd_rgb666_pins: lcd-rgb666-pins {
  726                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
  727                                        "PD5", "PD6", "PD7", "PD8", "PD9",
  728                                        "PD10", "PD11", "PD12", "PD13",
  729                                        "PD14", "PD15", "PD16", "PD17",
  730                                        "PD18", "PD19", "PD20", "PD21";
  731                                 function = "lcd0";
  732                         };
  733 
  734                         mmc0_pins: mmc0-pins {
  735                                 pins = "PF0", "PF1", "PF2", "PF3",
  736                                        "PF4", "PF5";
  737                                 function = "mmc0";
  738                                 drive-strength = <30>;
  739                                 bias-pull-up;
  740                         };
  741 
  742                         mmc1_pins: mmc1-pins {
  743                                 pins = "PG0", "PG1", "PG2", "PG3",
  744                                        "PG4", "PG5";
  745                                 function = "mmc1";
  746                                 drive-strength = <30>;
  747                                 bias-pull-up;
  748                         };
  749 
  750                         mmc2_pins: mmc2-pins {
  751                                 pins = "PC5", "PC6", "PC8", "PC9",
  752                                        "PC10","PC11", "PC12", "PC13",
  753                                        "PC14", "PC15", "PC16";
  754                                 function = "mmc2";
  755                                 drive-strength = <30>;
  756                                 bias-pull-up;
  757                         };
  758 
  759                         mmc2_ds_pin: mmc2-ds-pin {
  760                                 pins = "PC1";
  761                                 function = "mmc2";
  762                                 drive-strength = <30>;
  763                                 bias-pull-up;
  764                         };
  765 
  766                         pwm_pin: pwm-pin {
  767                                 pins = "PD22";
  768                                 function = "pwm";
  769                         };
  770 
  771                         rmii_pins: rmii-pins {
  772                                 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
  773                                        "PD18", "PD19", "PD20", "PD22", "PD23";
  774                                 function = "emac";
  775                                 drive-strength = <40>;
  776                         };
  777 
  778                         rgmii_pins: rgmii-pins {
  779                                 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
  780                                        "PD13", "PD15", "PD16", "PD17", "PD18",
  781                                        "PD19", "PD20", "PD21", "PD22", "PD23";
  782                                 function = "emac";
  783                                 drive-strength = <40>;
  784                         };
  785 
  786                         spdif_tx_pin: spdif-tx-pin {
  787                                 pins = "PH8";
  788                                 function = "spdif";
  789                         };
  790 
  791                         spi0_pins: spi0-pins {
  792                                 pins = "PC0", "PC1", "PC2", "PC3";
  793                                 function = "spi0";
  794                         };
  795 
  796                         spi1_pins: spi1-pins {
  797                                 pins = "PD0", "PD1", "PD2", "PD3";
  798                                 function = "spi1";
  799                         };
  800 
  801                         uart0_pb_pins: uart0-pb-pins {
  802                                 pins = "PB8", "PB9";
  803                                 function = "uart0";
  804                         };
  805 
  806                         uart1_pins: uart1-pins {
  807                                 pins = "PG6", "PG7";
  808                                 function = "uart1";
  809                         };
  810 
  811                         uart1_rts_cts_pins: uart1-rts-cts-pins {
  812                                 pins = "PG8", "PG9";
  813                                 function = "uart1";
  814                         };
  815 
  816                         uart2_pins: uart2-pins {
  817                                 pins = "PB0", "PB1";
  818                                 function = "uart2";
  819                         };
  820 
  821                         uart3_pins: uart3-pins {
  822                                 pins = "PD0", "PD1";
  823                                 function = "uart3";
  824                         };
  825 
  826                         uart4_pins: uart4-pins {
  827                                 pins = "PD2", "PD3";
  828                                 function = "uart4";
  829                         };
  830 
  831                         uart4_rts_cts_pins: uart4-rts-cts-pins {
  832                                 pins = "PD4", "PD5";
  833                                 function = "uart4";
  834                         };
  835                 };
  836 
  837                 timer@1c20c00 {
  838                         compatible = "allwinner,sun50i-a64-timer",
  839                                      "allwinner,sun8i-a23-timer";
  840                         reg = <0x01c20c00 0xa0>;
  841                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  842                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  843                         clocks = <&osc24M>;
  844                 };
  845 
  846                 wdt0: watchdog@1c20ca0 {
  847                         compatible = "allwinner,sun50i-a64-wdt",
  848                                      "allwinner,sun6i-a31-wdt";
  849                         reg = <0x01c20ca0 0x20>;
  850                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  851                         clocks = <&osc24M>;
  852                 };
  853 
  854                 spdif: spdif@1c21000 {
  855                         #sound-dai-cells = <0>;
  856                         compatible = "allwinner,sun50i-a64-spdif",
  857                                      "allwinner,sun8i-h3-spdif";
  858                         reg = <0x01c21000 0x400>;
  859                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  860                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
  861                         resets = <&ccu RST_BUS_SPDIF>;
  862                         clock-names = "apb", "spdif";
  863                         dmas = <&dma 2>;
  864                         dma-names = "tx";
  865                         pinctrl-names = "default";
  866                         pinctrl-0 = <&spdif_tx_pin>;
  867                         status = "disabled";
  868                 };
  869 
  870                 lradc: lradc@1c21800 {
  871                         compatible = "allwinner,sun50i-a64-lradc",
  872                                      "allwinner,sun8i-a83t-r-lradc";
  873                         reg = <0x01c21800 0x400>;
  874                         interrupt-parent = <&r_intc>;
  875                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  876                         status = "disabled";
  877                 };
  878 
  879                 i2s0: i2s@1c22000 {
  880                         #sound-dai-cells = <0>;
  881                         compatible = "allwinner,sun50i-a64-i2s",
  882                                      "allwinner,sun8i-h3-i2s";
  883                         reg = <0x01c22000 0x400>;
  884                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  885                         clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
  886                         clock-names = "apb", "mod";
  887                         resets = <&ccu RST_BUS_I2S0>;
  888                         dma-names = "rx", "tx";
  889                         dmas = <&dma 3>, <&dma 3>;
  890                         status = "disabled";
  891                 };
  892 
  893                 i2s1: i2s@1c22400 {
  894                         #sound-dai-cells = <0>;
  895                         compatible = "allwinner,sun50i-a64-i2s",
  896                                      "allwinner,sun8i-h3-i2s";
  897                         reg = <0x01c22400 0x400>;
  898                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  899                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
  900                         clock-names = "apb", "mod";
  901                         resets = <&ccu RST_BUS_I2S1>;
  902                         dma-names = "rx", "tx";
  903                         dmas = <&dma 4>, <&dma 4>;
  904                         status = "disabled";
  905                 };
  906 
  907                 i2s2: i2s@1c22800 {
  908                         #sound-dai-cells = <0>;
  909                         compatible = "allwinner,sun50i-a64-i2s",
  910                                      "allwinner,sun8i-h3-i2s";
  911                         reg = <0x01c22800 0x400>;
  912                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
  913                         clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
  914                         clock-names = "apb", "mod";
  915                         resets = <&ccu RST_BUS_I2S2>;
  916                         dma-names = "rx", "tx";
  917                         dmas = <&dma 27>, <&dma 27>;
  918                         status = "disabled";
  919                 };
  920 
  921                 dai: dai@1c22c00 {
  922                         #sound-dai-cells = <0>;
  923                         compatible = "allwinner,sun50i-a64-codec-i2s";
  924                         reg = <0x01c22c00 0x200>;
  925                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  926                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
  927                         clock-names = "apb", "mod";
  928                         resets = <&ccu RST_BUS_CODEC>;
  929                         dmas = <&dma 15>, <&dma 15>;
  930                         dma-names = "rx", "tx";
  931                         status = "disabled";
  932                 };
  933 
  934                 codec: codec@1c22e00 {
  935                         #sound-dai-cells = <1>;
  936                         compatible = "allwinner,sun50i-a64-codec",
  937                                      "allwinner,sun8i-a33-codec";
  938                         reg = <0x01c22e00 0x600>;
  939                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  940                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
  941                         clock-names = "bus", "mod";
  942                         status = "disabled";
  943                 };
  944 
  945                 ths: thermal-sensor@1c25000 {
  946                         compatible = "allwinner,sun50i-a64-ths";
  947                         reg = <0x01c25000 0x100>;
  948                         clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
  949                         clock-names = "bus", "mod";
  950                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  951                         resets = <&ccu RST_BUS_THS>;
  952                         nvmem-cells = <&ths_calibration>;
  953                         nvmem-cell-names = "calibration";
  954                         #thermal-sensor-cells = <1>;
  955                 };
  956 
  957                 uart0: serial@1c28000 {
  958                         compatible = "snps,dw-apb-uart";
  959                         reg = <0x01c28000 0x400>;
  960                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  961                         reg-shift = <2>;
  962                         reg-io-width = <4>;
  963                         clocks = <&ccu CLK_BUS_UART0>;
  964                         resets = <&ccu RST_BUS_UART0>;
  965                         status = "disabled";
  966                 };
  967 
  968                 uart1: serial@1c28400 {
  969                         compatible = "snps,dw-apb-uart";
  970                         reg = <0x01c28400 0x400>;
  971                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  972                         reg-shift = <2>;
  973                         reg-io-width = <4>;
  974                         clocks = <&ccu CLK_BUS_UART1>;
  975                         resets = <&ccu RST_BUS_UART1>;
  976                         status = "disabled";
  977                 };
  978 
  979                 uart2: serial@1c28800 {
  980                         compatible = "snps,dw-apb-uart";
  981                         reg = <0x01c28800 0x400>;
  982                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  983                         reg-shift = <2>;
  984                         reg-io-width = <4>;
  985                         clocks = <&ccu CLK_BUS_UART2>;
  986                         resets = <&ccu RST_BUS_UART2>;
  987                         status = "disabled";
  988                 };
  989 
  990                 uart3: serial@1c28c00 {
  991                         compatible = "snps,dw-apb-uart";
  992                         reg = <0x01c28c00 0x400>;
  993                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  994                         reg-shift = <2>;
  995                         reg-io-width = <4>;
  996                         clocks = <&ccu CLK_BUS_UART3>;
  997                         resets = <&ccu RST_BUS_UART3>;
  998                         status = "disabled";
  999                 };
 1000 
 1001                 uart4: serial@1c29000 {
 1002                         compatible = "snps,dw-apb-uart";
 1003                         reg = <0x01c29000 0x400>;
 1004                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 1005                         reg-shift = <2>;
 1006                         reg-io-width = <4>;
 1007                         clocks = <&ccu CLK_BUS_UART4>;
 1008                         resets = <&ccu RST_BUS_UART4>;
 1009                         status = "disabled";
 1010                 };
 1011 
 1012                 i2c0: i2c@1c2ac00 {
 1013                         compatible = "allwinner,sun6i-a31-i2c";
 1014                         reg = <0x01c2ac00 0x400>;
 1015                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 1016                         clocks = <&ccu CLK_BUS_I2C0>;
 1017                         resets = <&ccu RST_BUS_I2C0>;
 1018                         pinctrl-names = "default";
 1019                         pinctrl-0 = <&i2c0_pins>;
 1020                         status = "disabled";
 1021                         #address-cells = <1>;
 1022                         #size-cells = <0>;
 1023                 };
 1024 
 1025                 i2c1: i2c@1c2b000 {
 1026                         compatible = "allwinner,sun6i-a31-i2c";
 1027                         reg = <0x01c2b000 0x400>;
 1028                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 1029                         clocks = <&ccu CLK_BUS_I2C1>;
 1030                         resets = <&ccu RST_BUS_I2C1>;
 1031                         pinctrl-names = "default";
 1032                         pinctrl-0 = <&i2c1_pins>;
 1033                         status = "disabled";
 1034                         #address-cells = <1>;
 1035                         #size-cells = <0>;
 1036                 };
 1037 
 1038                 i2c2: i2c@1c2b400 {
 1039                         compatible = "allwinner,sun6i-a31-i2c";
 1040                         reg = <0x01c2b400 0x400>;
 1041                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 1042                         clocks = <&ccu CLK_BUS_I2C2>;
 1043                         resets = <&ccu RST_BUS_I2C2>;
 1044                         pinctrl-names = "default";
 1045                         pinctrl-0 = <&i2c2_pins>;
 1046                         status = "disabled";
 1047                         #address-cells = <1>;
 1048                         #size-cells = <0>;
 1049                 };
 1050 
 1051                 spi0: spi@1c68000 {
 1052                         compatible = "allwinner,sun8i-h3-spi";
 1053                         reg = <0x01c68000 0x1000>;
 1054                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 1055                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 1056                         clock-names = "ahb", "mod";
 1057                         dmas = <&dma 23>, <&dma 23>;
 1058                         dma-names = "rx", "tx";
 1059                         pinctrl-names = "default";
 1060                         pinctrl-0 = <&spi0_pins>;
 1061                         resets = <&ccu RST_BUS_SPI0>;
 1062                         status = "disabled";
 1063                         num-cs = <1>;
 1064                         #address-cells = <1>;
 1065                         #size-cells = <0>;
 1066                 };
 1067 
 1068                 spi1: spi@1c69000 {
 1069                         compatible = "allwinner,sun8i-h3-spi";
 1070                         reg = <0x01c69000 0x1000>;
 1071                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 1072                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
 1073                         clock-names = "ahb", "mod";
 1074                         dmas = <&dma 24>, <&dma 24>;
 1075                         dma-names = "rx", "tx";
 1076                         pinctrl-names = "default";
 1077                         pinctrl-0 = <&spi1_pins>;
 1078                         resets = <&ccu RST_BUS_SPI1>;
 1079                         status = "disabled";
 1080                         num-cs = <1>;
 1081                         #address-cells = <1>;
 1082                         #size-cells = <0>;
 1083                 };
 1084 
 1085                 emac: ethernet@1c30000 {
 1086                         compatible = "allwinner,sun50i-a64-emac";
 1087                         syscon = <&syscon>;
 1088                         reg = <0x01c30000 0x10000>;
 1089                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 1090                         interrupt-names = "macirq";
 1091                         resets = <&ccu RST_BUS_EMAC>;
 1092                         reset-names = "stmmaceth";
 1093                         clocks = <&ccu CLK_BUS_EMAC>;
 1094                         clock-names = "stmmaceth";
 1095                         status = "disabled";
 1096 
 1097                         mdio: mdio {
 1098                                 compatible = "snps,dwmac-mdio";
 1099                                 #address-cells = <1>;
 1100                                 #size-cells = <0>;
 1101                         };
 1102                 };
 1103 
 1104                 mali: gpu@1c40000 {
 1105                         compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
 1106                         reg = <0x01c40000 0x10000>;
 1107                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 1108                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 1109                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 1110                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 1111                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 1112                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 1113                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 1114                         interrupt-names = "gp",
 1115                                           "gpmmu",
 1116                                           "pp0",
 1117                                           "ppmmu0",
 1118                                           "pp1",
 1119                                           "ppmmu1",
 1120                                           "pmu";
 1121                         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 1122                         clock-names = "bus", "core";
 1123                         resets = <&ccu RST_BUS_GPU>;
 1124                         operating-points-v2 = <&gpu_opp_table>;
 1125                 };
 1126 
 1127                 gic: interrupt-controller@1c81000 {
 1128                         compatible = "arm,gic-400";
 1129                         reg = <0x01c81000 0x1000>,
 1130                               <0x01c82000 0x2000>,
 1131                               <0x01c84000 0x2000>,
 1132                               <0x01c86000 0x2000>;
 1133                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 1134                         interrupt-controller;
 1135                         #interrupt-cells = <3>;
 1136                 };
 1137 
 1138                 pwm: pwm@1c21400 {
 1139                         compatible = "allwinner,sun50i-a64-pwm",
 1140                                      "allwinner,sun5i-a13-pwm";
 1141                         reg = <0x01c21400 0x400>;
 1142                         clocks = <&osc24M>;
 1143                         pinctrl-names = "default";
 1144                         pinctrl-0 = <&pwm_pin>;
 1145                         #pwm-cells = <3>;
 1146                         status = "disabled";
 1147                 };
 1148 
 1149                 mbus: dram-controller@1c62000 {
 1150                         compatible = "allwinner,sun50i-a64-mbus";
 1151                         reg = <0x01c62000 0x1000>,
 1152                               <0x01c63000 0x1000>;
 1153                         reg-names = "mbus", "dram";
 1154                         clocks = <&ccu CLK_MBUS>,
 1155                                  <&ccu CLK_DRAM>,
 1156                                  <&ccu CLK_BUS_DRAM>;
 1157                         clock-names = "mbus", "dram", "bus";
 1158                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 1159                         #address-cells = <1>;
 1160                         #size-cells = <1>;
 1161                         dma-ranges = <0x00000000 0x40000000 0xc0000000>;
 1162                         #interconnect-cells = <1>;
 1163                 };
 1164 
 1165                 csi: csi@1cb0000 {
 1166                         compatible = "allwinner,sun50i-a64-csi";
 1167                         reg = <0x01cb0000 0x1000>;
 1168                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 1169                         clocks = <&ccu CLK_BUS_CSI>,
 1170                                  <&ccu CLK_CSI_SCLK>,
 1171                                  <&ccu CLK_DRAM_CSI>;
 1172                         clock-names = "bus", "mod", "ram";
 1173                         resets = <&ccu RST_BUS_CSI>;
 1174                         pinctrl-names = "default";
 1175                         pinctrl-0 = <&csi_pins>;
 1176                         status = "disabled";
 1177                 };
 1178 
 1179                 dsi: dsi@1ca0000 {
 1180                         compatible = "allwinner,sun50i-a64-mipi-dsi";
 1181                         reg = <0x01ca0000 0x1000>;
 1182                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 1183                         clocks = <&ccu CLK_BUS_MIPI_DSI>;
 1184                         resets = <&ccu RST_BUS_MIPI_DSI>;
 1185                         phys = <&dphy>;
 1186                         phy-names = "dphy";
 1187                         status = "disabled";
 1188                         #address-cells = <1>;
 1189                         #size-cells = <0>;
 1190 
 1191                         port {
 1192                                 dsi_in_tcon0: endpoint {
 1193                                         remote-endpoint = <&tcon0_out_dsi>;
 1194                                 };
 1195                         };
 1196                 };
 1197 
 1198                 dphy: d-phy@1ca1000 {
 1199                         compatible = "allwinner,sun50i-a64-mipi-dphy",
 1200                                      "allwinner,sun6i-a31-mipi-dphy";
 1201                         reg = <0x01ca1000 0x1000>;
 1202                         clocks = <&ccu CLK_BUS_MIPI_DSI>,
 1203                                  <&ccu CLK_DSI_DPHY>;
 1204                         clock-names = "bus", "mod";
 1205                         resets = <&ccu RST_BUS_MIPI_DSI>;
 1206                         status = "disabled";
 1207                         #phy-cells = <0>;
 1208                 };
 1209 
 1210                 deinterlace: deinterlace@1e00000 {
 1211                         compatible = "allwinner,sun50i-a64-deinterlace",
 1212                                      "allwinner,sun8i-h3-deinterlace";
 1213                         reg = <0x01e00000 0x20000>;
 1214                         clocks = <&ccu CLK_BUS_DEINTERLACE>,
 1215                                  <&ccu CLK_DEINTERLACE>,
 1216                                  <&ccu CLK_DRAM_DEINTERLACE>;
 1217                         clock-names = "bus", "mod", "ram";
 1218                         resets = <&ccu RST_BUS_DEINTERLACE>;
 1219                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 1220                         interconnects = <&mbus 9>;
 1221                         interconnect-names = "dma-mem";
 1222                 };
 1223 
 1224                 hdmi: hdmi@1ee0000 {
 1225                         compatible = "allwinner,sun50i-a64-dw-hdmi",
 1226                                      "allwinner,sun8i-a83t-dw-hdmi";
 1227                         reg = <0x01ee0000 0x10000>;
 1228                         reg-io-width = <1>;
 1229                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 1230                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
 1231                                  <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
 1232                         clock-names = "iahb", "isfr", "tmds", "cec";
 1233                         resets = <&ccu RST_BUS_HDMI1>;
 1234                         reset-names = "ctrl";
 1235                         phys = <&hdmi_phy>;
 1236                         phy-names = "phy";
 1237                         status = "disabled";
 1238 
 1239                         ports {
 1240                                 #address-cells = <1>;
 1241                                 #size-cells = <0>;
 1242 
 1243                                 hdmi_in: port@0 {
 1244                                         reg = <0>;
 1245 
 1246                                         hdmi_in_tcon1: endpoint {
 1247                                                 remote-endpoint = <&tcon1_out_hdmi>;
 1248                                         };
 1249                                 };
 1250 
 1251                                 hdmi_out: port@1 {
 1252                                         reg = <1>;
 1253                                 };
 1254                         };
 1255                 };
 1256 
 1257                 hdmi_phy: hdmi-phy@1ef0000 {
 1258                         compatible = "allwinner,sun50i-a64-hdmi-phy";
 1259                         reg = <0x01ef0000 0x10000>;
 1260                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
 1261                                  <&ccu CLK_PLL_VIDEO0>;
 1262                         clock-names = "bus", "mod", "pll-0";
 1263                         resets = <&ccu RST_BUS_HDMI0>;
 1264                         reset-names = "phy";
 1265                         #phy-cells = <0>;
 1266                 };
 1267 
 1268                 rtc: rtc@1f00000 {
 1269                         compatible = "allwinner,sun50i-a64-rtc",
 1270                                      "allwinner,sun8i-h3-rtc";
 1271                         reg = <0x01f00000 0x400>;
 1272                         interrupt-parent = <&r_intc>;
 1273                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 1274                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 1275                         clock-output-names = "osc32k", "osc32k-out", "iosc";
 1276                         clocks = <&osc32k>;
 1277                         #clock-cells = <1>;
 1278                 };
 1279 
 1280                 r_intc: interrupt-controller@1f00c00 {
 1281                         compatible = "allwinner,sun50i-a64-r-intc",
 1282                                      "allwinner,sun6i-a31-r-intc";
 1283                         interrupt-controller;
 1284                         #interrupt-cells = <3>;
 1285                         reg = <0x01f00c00 0x400>;
 1286                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 1287                 };
 1288 
 1289                 r_ccu: clock@1f01400 {
 1290                         compatible = "allwinner,sun50i-a64-r-ccu";
 1291                         reg = <0x01f01400 0x100>;
 1292                         clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
 1293                                  <&ccu CLK_PLL_PERIPH0>;
 1294                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 1295                         #clock-cells = <1>;
 1296                         #reset-cells = <1>;
 1297                 };
 1298 
 1299                 codec_analog: codec-analog@1f015c0 {
 1300                         compatible = "allwinner,sun50i-a64-codec-analog";
 1301                         reg = <0x01f015c0 0x4>;
 1302                         status = "disabled";
 1303                 };
 1304 
 1305                 r_i2c: i2c@1f02400 {
 1306                         compatible = "allwinner,sun50i-a64-i2c",
 1307                                      "allwinner,sun6i-a31-i2c";
 1308                         reg = <0x01f02400 0x400>;
 1309                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 1310                         clocks = <&r_ccu CLK_APB0_I2C>;
 1311                         resets = <&r_ccu RST_APB0_I2C>;
 1312                         status = "disabled";
 1313                         #address-cells = <1>;
 1314                         #size-cells = <0>;
 1315                 };
 1316 
 1317                 r_ir: ir@1f02000 {
 1318                         compatible = "allwinner,sun50i-a64-ir",
 1319                                      "allwinner,sun6i-a31-ir";
 1320                         reg = <0x01f02000 0x400>;
 1321                         clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
 1322                         clock-names = "apb", "ir";
 1323                         resets = <&r_ccu RST_APB0_IR>;
 1324                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 1325                         pinctrl-names = "default";
 1326                         pinctrl-0 = <&r_ir_rx_pin>;
 1327                         status = "disabled";
 1328                 };
 1329 
 1330                 r_pwm: pwm@1f03800 {
 1331                         compatible = "allwinner,sun50i-a64-pwm",
 1332                                      "allwinner,sun5i-a13-pwm";
 1333                         reg = <0x01f03800 0x400>;
 1334                         clocks = <&osc24M>;
 1335                         pinctrl-names = "default";
 1336                         pinctrl-0 = <&r_pwm_pin>;
 1337                         #pwm-cells = <3>;
 1338                         status = "disabled";
 1339                 };
 1340 
 1341                 r_pio: pinctrl@1f02c00 {
 1342                         compatible = "allwinner,sun50i-a64-r-pinctrl";
 1343                         reg = <0x01f02c00 0x400>;
 1344                         interrupt-parent = <&r_intc>;
 1345                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 1346                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 1347                         clock-names = "apb", "hosc", "losc";
 1348                         gpio-controller;
 1349                         #gpio-cells = <3>;
 1350                         interrupt-controller;
 1351                         #interrupt-cells = <3>;
 1352 
 1353                         r_i2c_pl89_pins: r-i2c-pl89-pins {
 1354                                 pins = "PL8", "PL9";
 1355                                 function = "s_i2c";
 1356                         };
 1357 
 1358                         r_ir_rx_pin: r-ir-rx-pin {
 1359                                 pins = "PL11";
 1360                                 function = "s_cir_rx";
 1361                         };
 1362 
 1363                         r_pwm_pin: r-pwm-pin {
 1364                                 pins = "PL10";
 1365                                 function = "s_pwm";
 1366                         };
 1367 
 1368                         r_rsb_pins: r-rsb-pins {
 1369                                 pins = "PL0", "PL1";
 1370                                 function = "s_rsb";
 1371                         };
 1372                 };
 1373 
 1374                 r_rsb: rsb@1f03400 {
 1375                         compatible = "allwinner,sun8i-a23-rsb";
 1376                         reg = <0x01f03400 0x400>;
 1377                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 1378                         clocks = <&r_ccu 6>;
 1379                         clock-frequency = <3000000>;
 1380                         resets = <&r_ccu 2>;
 1381                         pinctrl-names = "default";
 1382                         pinctrl-0 = <&r_rsb_pins>;
 1383                         status = "disabled";
 1384                         #address-cells = <1>;
 1385                         #size-cells = <0>;
 1386                 };
 1387         };
 1388 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/allwinner/sun50i-a64.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/allwinner/sun50i-a64.dtsi
