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sys/contrib/device-tree/src/arm64/allwinner/sun50i-h616.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 // Copyright (C) 2020 Arm Ltd. 3 // based on the H6 dtsi, which is: 4 // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 5 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/clock/sun50i-h616-ccu.h> 8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h> 9 #include <dt-bindings/clock/sun6i-rtc.h> 10 #include <dt-bindings/reset/sun50i-h616-ccu.h> 11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h> 12 13 / { 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 compatible = "arm,cortex-a53"; 24 device_type = "cpu"; 25 reg = <0>; 26 enable-method = "psci"; 27 clocks = <&ccu CLK_CPUX>; 28 }; 29 30 cpu1: cpu@1 { 31 compatible = "arm,cortex-a53"; 32 device_type = "cpu"; 33 reg = <1>; 34 enable-method = "psci"; 35 clocks = <&ccu CLK_CPUX>; 36 }; 37 38 cpu2: cpu@2 { 39 compatible = "arm,cortex-a53"; 40 device_type = "cpu"; 41 reg = <2>; 42 enable-method = "psci"; 43 clocks = <&ccu CLK_CPUX>; 44 }; 45 46 cpu3: cpu@3 { 47 compatible = "arm,cortex-a53"; 48 device_type = "cpu"; 49 reg = <3>; 50 enable-method = "psci"; 51 clocks = <&ccu CLK_CPUX>; 52 }; 53 }; 54 55 reserved-memory { 56 #address-cells = <2>; 57 #size-cells = <2>; 58 ranges; 59 60 /* 61 * 256 KiB reserved for Trusted Firmware-A (BL31). 62 * This is added by BL31 itself, but some bootloaders fail 63 * to propagate this into the DTB handed to kernels. 64 */ 65 secmon@40000000 { 66 reg = <0x0 0x40000000 0x0 0x40000>; 67 no-map; 68 }; 69 }; 70 71 osc24M: osc24M-clk { 72 #clock-cells = <0>; 73 compatible = "fixed-clock"; 74 clock-frequency = <24000000>; 75 clock-output-names = "osc24M"; 76 }; 77 78 pmu { 79 compatible = "arm,cortex-a53-pmu"; 80 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 85 }; 86 87 psci { 88 compatible = "arm,psci-0.2"; 89 method = "smc"; 90 }; 91 92 timer { 93 compatible = "arm,armv8-timer"; 94 arm,no-tick-in-suspend; 95 interrupts = <GIC_PPI 13 96 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 97 <GIC_PPI 14 98 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 99 <GIC_PPI 11 100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 101 <GIC_PPI 10 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 103 }; 104 105 soc { 106 compatible = "simple-bus"; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges = <0x0 0x0 0x0 0x40000000>; 110 111 syscon: syscon@3000000 { 112 compatible = "allwinner,sun50i-h616-system-control"; 113 reg = <0x03000000 0x1000>; 114 #address-cells = <1>; 115 #size-cells = <1>; 116 ranges; 117 118 sram_c: sram@28000 { 119 compatible = "mmio-sram"; 120 reg = <0x00028000 0x30000>; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 ranges = <0 0x00028000 0x30000>; 124 }; 125 }; 126 127 ccu: clock@3001000 { 128 compatible = "allwinner,sun50i-h616-ccu"; 129 reg = <0x03001000 0x1000>; 130 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; 131 clock-names = "hosc", "losc", "iosc"; 132 #clock-cells = <1>; 133 #reset-cells = <1>; 134 }; 135 136 watchdog: watchdog@30090a0 { 137 compatible = "allwinner,sun50i-h616-wdt", 138 "allwinner,sun6i-a31-wdt"; 139 reg = <0x030090a0 0x20>; 140 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&osc24M>; 142 }; 143 144 pio: pinctrl@300b000 { 145 compatible = "allwinner,sun50i-h616-pinctrl"; 146 reg = <0x0300b000 0x400>; 147 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; 156 clock-names = "apb", "hosc", "losc"; 157 gpio-controller; 158 #gpio-cells = <3>; 159 interrupt-controller; 160 #interrupt-cells = <3>; 161 162 ext_rgmii_pins: rgmii-pins { 163 pins = "PI0", "PI1", "PI2", "PI3", "PI4", 164 "PI5", "PI7", "PI8", "PI9", "PI10", 165 "PI11", "PI12", "PI13", "PI14", "PI15", 166 "PI16"; 167 function = "emac0"; 168 drive-strength = <40>; 169 }; 170 171 i2c0_pins: i2c0-pins { 172 pins = "PI6", "PI7"; 173 function = "i2c0"; 174 }; 175 176 i2c3_ph_pins: i2c3-ph-pins { 177 pins = "PH4", "PH5"; 178 function = "i2c3"; 179 }; 180 181 ir_rx_pin: ir-rx-pin { 182 pins = "PH10"; 183 function = "ir_rx"; 184 }; 185 186 mmc0_pins: mmc0-pins { 187 pins = "PF0", "PF1", "PF2", "PF3", 188 "PF4", "PF5"; 189 function = "mmc0"; 190 drive-strength = <30>; 191 bias-pull-up; 192 }; 193 194 /omit-if-no-ref/ 195 mmc1_pins: mmc1-pins { 196 pins = "PG0", "PG1", "PG2", "PG3", 197 "PG4", "PG5"; 198 function = "mmc1"; 199 drive-strength = <30>; 200 bias-pull-up; 201 }; 202 203 mmc2_pins: mmc2-pins { 204 pins = "PC0", "PC1", "PC5", "PC6", 205 "PC8", "PC9", "PC10", "PC11", 206 "PC13", "PC14", "PC15", "PC16"; 207 function = "mmc2"; 208 drive-strength = <30>; 209 bias-pull-up; 210 }; 211 212 /omit-if-no-ref/ 213 spi0_pins: spi0-pins { 214 pins = "PC0", "PC2", "PC4"; 215 function = "spi0"; 216 }; 217 218 /omit-if-no-ref/ 219 spi0_cs0_pin: spi0-cs0-pin { 220 pins = "PC3"; 221 function = "spi0"; 222 }; 223 224 /omit-if-no-ref/ 225 spi1_pins: spi1-pins { 226 pins = "PH6", "PH7", "PH8"; 227 function = "spi1"; 228 }; 229 230 /omit-if-no-ref/ 231 spi1_cs0_pin: spi1-cs0-pin { 232 pins = "PH5"; 233 function = "spi1"; 234 }; 235 236 uart0_ph_pins: uart0-ph-pins { 237 pins = "PH0", "PH1"; 238 function = "uart0"; 239 }; 240 241 /omit-if-no-ref/ 242 uart1_pins: uart1-pins { 243 pins = "PG6", "PG7"; 244 function = "uart1"; 245 }; 246 247 /omit-if-no-ref/ 248 uart1_rts_cts_pins: uart1-rts-cts-pins { 249 pins = "PG8", "PG9"; 250 function = "uart1"; 251 }; 252 }; 253 254 gic: interrupt-controller@3021000 { 255 compatible = "arm,gic-400"; 256 reg = <0x03021000 0x1000>, 257 <0x03022000 0x2000>, 258 <0x03024000 0x2000>, 259 <0x03026000 0x2000>; 260 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 261 interrupt-controller; 262 #interrupt-cells = <3>; 263 }; 264 265 mmc0: mmc@4020000 { 266 compatible = "allwinner,sun50i-h616-mmc", 267 "allwinner,sun50i-a100-mmc"; 268 reg = <0x04020000 0x1000>; 269 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 270 clock-names = "ahb", "mmc"; 271 resets = <&ccu RST_BUS_MMC0>; 272 reset-names = "ahb"; 273 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&mmc0_pins>; 276 status = "disabled"; 277 max-frequency = <150000000>; 278 cap-sd-highspeed; 279 cap-mmc-highspeed; 280 mmc-ddr-3_3v; 281 cap-sdio-irq; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 }; 285 286 mmc1: mmc@4021000 { 287 compatible = "allwinner,sun50i-h616-mmc", 288 "allwinner,sun50i-a100-mmc"; 289 reg = <0x04021000 0x1000>; 290 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 291 clock-names = "ahb", "mmc"; 292 resets = <&ccu RST_BUS_MMC1>; 293 reset-names = "ahb"; 294 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&mmc1_pins>; 297 status = "disabled"; 298 max-frequency = <150000000>; 299 cap-sd-highspeed; 300 cap-mmc-highspeed; 301 mmc-ddr-3_3v; 302 cap-sdio-irq; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 }; 306 307 mmc2: mmc@4022000 { 308 compatible = "allwinner,sun50i-h616-emmc", 309 "allwinner,sun50i-a100-emmc"; 310 reg = <0x04022000 0x1000>; 311 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 312 clock-names = "ahb", "mmc"; 313 resets = <&ccu RST_BUS_MMC2>; 314 reset-names = "ahb"; 315 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&mmc2_pins>; 318 status = "disabled"; 319 max-frequency = <150000000>; 320 cap-sd-highspeed; 321 cap-mmc-highspeed; 322 mmc-ddr-3_3v; 323 cap-sdio-irq; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 }; 327 328 uart0: serial@5000000 { 329 compatible = "snps,dw-apb-uart"; 330 reg = <0x05000000 0x400>; 331 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 332 reg-shift = <2>; 333 reg-io-width = <4>; 334 clocks = <&ccu CLK_BUS_UART0>; 335 resets = <&ccu RST_BUS_UART0>; 336 status = "disabled"; 337 }; 338 339 uart1: serial@5000400 { 340 compatible = "snps,dw-apb-uart"; 341 reg = <0x05000400 0x400>; 342 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 343 reg-shift = <2>; 344 reg-io-width = <4>; 345 clocks = <&ccu CLK_BUS_UART1>; 346 resets = <&ccu RST_BUS_UART1>; 347 status = "disabled"; 348 }; 349 350 uart2: serial@5000800 { 351 compatible = "snps,dw-apb-uart"; 352 reg = <0x05000800 0x400>; 353 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 354 reg-shift = <2>; 355 reg-io-width = <4>; 356 clocks = <&ccu CLK_BUS_UART2>; 357 resets = <&ccu RST_BUS_UART2>; 358 status = "disabled"; 359 }; 360 361 uart3: serial@5000c00 { 362 compatible = "snps,dw-apb-uart"; 363 reg = <0x05000c00 0x400>; 364 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 365 reg-shift = <2>; 366 reg-io-width = <4>; 367 clocks = <&ccu CLK_BUS_UART3>; 368 resets = <&ccu RST_BUS_UART3>; 369 status = "disabled"; 370 }; 371 372 uart4: serial@5001000 { 373 compatible = "snps,dw-apb-uart"; 374 reg = <0x05001000 0x400>; 375 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 376 reg-shift = <2>; 377 reg-io-width = <4>; 378 clocks = <&ccu CLK_BUS_UART4>; 379 resets = <&ccu RST_BUS_UART4>; 380 status = "disabled"; 381 }; 382 383 uart5: serial@5001400 { 384 compatible = "snps,dw-apb-uart"; 385 reg = <0x05001400 0x400>; 386 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 387 reg-shift = <2>; 388 reg-io-width = <4>; 389 clocks = <&ccu CLK_BUS_UART5>; 390 resets = <&ccu RST_BUS_UART5>; 391 status = "disabled"; 392 }; 393 394 i2c0: i2c@5002000 { 395 compatible = "allwinner,sun50i-h616-i2c", 396 "allwinner,sun8i-v536-i2c", 397 "allwinner,sun6i-a31-i2c"; 398 reg = <0x05002000 0x400>; 399 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&ccu CLK_BUS_I2C0>; 401 resets = <&ccu RST_BUS_I2C0>; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&i2c0_pins>; 404 status = "disabled"; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 }; 408 409 i2c1: i2c@5002400 { 410 compatible = "allwinner,sun50i-h616-i2c", 411 "allwinner,sun8i-v536-i2c", 412 "allwinner,sun6i-a31-i2c"; 413 reg = <0x05002400 0x400>; 414 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&ccu CLK_BUS_I2C1>; 416 resets = <&ccu RST_BUS_I2C1>; 417 status = "disabled"; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 }; 421 422 i2c2: i2c@5002800 { 423 compatible = "allwinner,sun50i-h616-i2c", 424 "allwinner,sun8i-v536-i2c", 425 "allwinner,sun6i-a31-i2c"; 426 reg = <0x05002800 0x400>; 427 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&ccu CLK_BUS_I2C2>; 429 resets = <&ccu RST_BUS_I2C2>; 430 status = "disabled"; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 }; 434 435 i2c3: i2c@5002c00 { 436 compatible = "allwinner,sun50i-h616-i2c", 437 "allwinner,sun8i-v536-i2c", 438 "allwinner,sun6i-a31-i2c"; 439 reg = <0x05002c00 0x400>; 440 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&ccu CLK_BUS_I2C3>; 442 resets = <&ccu RST_BUS_I2C3>; 443 status = "disabled"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 }; 447 448 i2c4: i2c@5003000 { 449 compatible = "allwinner,sun50i-h616-i2c", 450 "allwinner,sun8i-v536-i2c", 451 "allwinner,sun6i-a31-i2c"; 452 reg = <0x05003000 0x400>; 453 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&ccu CLK_BUS_I2C4>; 455 resets = <&ccu RST_BUS_I2C4>; 456 status = "disabled"; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 }; 460 461 spi0: spi@5010000 { 462 compatible = "allwinner,sun50i-h616-spi", 463 "allwinner,sun8i-h3-spi"; 464 reg = <0x05010000 0x1000>; 465 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 467 clock-names = "ahb", "mod"; 468 resets = <&ccu RST_BUS_SPI0>; 469 status = "disabled"; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 }; 473 474 spi1: spi@5011000 { 475 compatible = "allwinner,sun50i-h616-spi", 476 "allwinner,sun8i-h3-spi"; 477 reg = <0x05011000 0x1000>; 478 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 480 clock-names = "ahb", "mod"; 481 resets = <&ccu RST_BUS_SPI1>; 482 status = "disabled"; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 }; 486 487 emac0: ethernet@5020000 { 488 compatible = "allwinner,sun50i-h616-emac0", 489 "allwinner,sun50i-a64-emac"; 490 reg = <0x05020000 0x10000>; 491 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 492 interrupt-names = "macirq"; 493 clocks = <&ccu CLK_BUS_EMAC0>; 494 clock-names = "stmmaceth"; 495 resets = <&ccu RST_BUS_EMAC0>; 496 reset-names = "stmmaceth"; 497 syscon = <&syscon>; 498 status = "disabled"; 499 500 mdio0: mdio { 501 compatible = "snps,dwmac-mdio"; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 }; 505 }; 506 507 rtc: rtc@7000000 { 508 compatible = "allwinner,sun50i-h616-rtc"; 509 reg = <0x07000000 0x400>; 510 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>, 512 <&ccu CLK_PLL_SYSTEM_32K>; 513 clock-names = "bus", "hosc", 514 "pll-32k"; 515 #clock-cells = <1>; 516 }; 517 518 r_ccu: clock@7010000 { 519 compatible = "allwinner,sun50i-h616-r-ccu"; 520 reg = <0x07010000 0x210>; 521 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 522 <&ccu CLK_PLL_PERIPH0>; 523 clock-names = "hosc", "losc", "iosc", "pll-periph"; 524 #clock-cells = <1>; 525 #reset-cells = <1>; 526 }; 527 528 r_pio: pinctrl@7022000 { 529 compatible = "allwinner,sun50i-h616-r-pinctrl"; 530 reg = <0x07022000 0x400>; 531 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, 532 <&rtc CLK_OSC32K>; 533 clock-names = "apb", "hosc", "losc"; 534 gpio-controller; 535 #gpio-cells = <3>; 536 537 /omit-if-no-ref/ 538 r_i2c_pins: r-i2c-pins { 539 pins = "PL0", "PL1"; 540 function = "s_i2c"; 541 }; 542 543 r_rsb_pins: r-rsb-pins { 544 pins = "PL0", "PL1"; 545 function = "s_rsb"; 546 }; 547 }; 548 549 ir: ir@7040000 { 550 compatible = "allwinner,sun50i-h616-ir", 551 "allwinner,sun6i-a31-ir"; 552 reg = <0x07040000 0x400>; 553 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&r_ccu CLK_R_APB1_IR>, 555 <&r_ccu CLK_IR>; 556 clock-names = "apb", "ir"; 557 resets = <&r_ccu RST_R_APB1_IR>; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&ir_rx_pin>; 560 status = "disabled"; 561 }; 562 563 r_i2c: i2c@7081400 { 564 compatible = "allwinner,sun50i-h616-i2c", 565 "allwinner,sun8i-v536-i2c", 566 "allwinner,sun6i-a31-i2c"; 567 reg = <0x07081400 0x400>; 568 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&r_ccu CLK_R_APB2_I2C>; 570 resets = <&r_ccu RST_R_APB2_I2C>; 571 status = "disabled"; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 }; 575 576 r_rsb: rsb@7083000 { 577 compatible = "allwinner,sun50i-h616-rsb", 578 "allwinner,sun8i-a23-rsb"; 579 reg = <0x07083000 0x400>; 580 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&r_ccu CLK_R_APB2_RSB>; 582 clock-frequency = <3000000>; 583 resets = <&r_ccu RST_R_APB2_RSB>; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&r_rsb_pins>; 586 status = "disabled"; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 }; 590 }; 591 };
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