meson-gxbb.dtsi

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    1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
    2 /*
    3  * Copyright (c) 2016 Andreas Färber
    4  */
    5 
    6 #include "meson-gx.dtsi"
    7 #include "meson-gx-mali450.dtsi"
    8 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
    9 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
   10 #include <dt-bindings/clock/gxbb-clkc.h>
   11 #include <dt-bindings/clock/gxbb-aoclkc.h>
   12 #include <dt-bindings/reset/gxbb-aoclkc.h>
   13 
   14 / {
   15         compatible = "amlogic,meson-gxbb";
   16 
   17         soc {
   18                 usb0_phy: phy@c0000000 {
   19                         compatible = "amlogic,meson-gxbb-usb2-phy";
   20                         #phy-cells = <0>;
   21                         reg = <0x0 0xc0000000 0x0 0x20>;
   22                         resets = <&reset RESET_USB_OTG>;
   23                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
   24                         clock-names = "usb_general", "usb";
   25                         status = "disabled";
   26                 };
   27 
   28                 usb1_phy: phy@c0000020 {
   29                         compatible = "amlogic,meson-gxbb-usb2-phy";
   30                         #phy-cells = <0>;
   31                         reg = <0x0 0xc0000020 0x0 0x20>;
   32                         resets = <&reset RESET_USB_OTG>;
   33                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
   34                         clock-names = "usb_general", "usb";
   35                         status = "disabled";
   36                 };
   37 
   38                 usb0: usb@c9000000 {
   39                         compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
   40                         reg = <0x0 0xc9000000 0x0 0x40000>;
   41                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
   42                         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
   43                         clock-names = "otg";
   44                         phys = <&usb0_phy>;
   45                         phy-names = "usb2-phy";
   46                         dr_mode = "host";
   47                         status = "disabled";
   48                 };
   49 
   50                 usb1: usb@c9100000 {
   51                         compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
   52                         reg = <0x0 0xc9100000 0x0 0x40000>;
   53                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
   54                         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
   55                         clock-names = "otg";
   56                         phys = <&usb1_phy>;
   57                         phy-names = "usb2-phy";
   58                         dr_mode = "host";
   59                         status = "disabled";
   60                 };
   61         };
   62 };
   63 
   64 &aiu {
   65         compatible = "amlogic,aiu-gxbb", "amlogic,aiu";
   66         clocks = <&clkc CLKID_AIU_GLUE>,
   67                  <&clkc CLKID_I2S_OUT>,
   68                  <&clkc CLKID_AOCLK_GATE>,
   69                  <&clkc CLKID_CTS_AMCLK>,
   70                  <&clkc CLKID_MIXER_IFACE>,
   71                  <&clkc CLKID_IEC958>,
   72                  <&clkc CLKID_IEC958_GATE>,
   73                  <&clkc CLKID_CTS_MCLK_I958>,
   74                  <&clkc CLKID_CTS_I958>;
   75         clock-names = "pclk",
   76                       "i2s_pclk",
   77                       "i2s_aoclk",
   78                       "i2s_mclk",
   79                       "i2s_mixer",
   80                       "spdif_pclk",
   81                       "spdif_aoclk",
   82                       "spdif_mclk",
   83                       "spdif_mclk_sel";
   84         resets = <&reset RESET_AIU>;
   85 };
   86 
   87 &aobus {
   88         pinctrl_aobus: pinctrl@14 {
   89                 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
   90                 #address-cells = <2>;
   91                 #size-cells = <2>;
   92                 ranges;
   93 
   94                 gpio_ao: bank@14 {
   95                         reg = <0x0 0x00014 0x0 0x8>,
   96                               <0x0 0x0002c 0x0 0x4>,
   97                               <0x0 0x00024 0x0 0x8>;
   98                         reg-names = "mux", "pull", "gpio";
   99                         gpio-controller;
  100                         #gpio-cells = <2>;
  101                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
  102                 };
  103 
  104                 uart_ao_a_pins: uart_ao_a {
  105                         mux {
  106                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
  107                                 function = "uart_ao";
  108                                 bias-disable;
  109                         };
  110                 };
  111 
  112                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
  113                         mux {
  114                                 groups = "uart_cts_ao_a",
  115                                        "uart_rts_ao_a";
  116                                 function = "uart_ao";
  117                                 bias-disable;
  118                         };
  119                 };
  120 
  121                 uart_ao_b_pins: uart_ao_b {
  122                         mux {
  123                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
  124                                 function = "uart_ao_b";
  125                                 bias-disable;
  126                         };
  127                 };
  128 
  129                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
  130                         mux {
  131                                 groups = "uart_cts_ao_b",
  132                                        "uart_rts_ao_b";
  133                                 function = "uart_ao_b";
  134                                 bias-disable;
  135                         };
  136                 };
  137 
  138                 remote_input_ao_pins: remote_input_ao {
  139                         mux {
  140                                 groups = "remote_input_ao";
  141                                 function = "remote_input_ao";
  142                                 bias-disable;
  143                         };
  144                 };
  145 
  146                 i2c_ao_pins: i2c_ao {
  147                         mux {
  148                                 groups = "i2c_sck_ao",
  149                                        "i2c_sda_ao";
  150                                 function = "i2c_ao";
  151                                 bias-disable;
  152                         };
  153                 };
  154 
  155                 pwm_ao_a_3_pins: pwm_ao_a_3 {
  156                         mux {
  157                                 groups = "pwm_ao_a_3";
  158                                 function = "pwm_ao_a_3";
  159                                 bias-disable;
  160                         };
  161                 };
  162 
  163                 pwm_ao_a_6_pins: pwm_ao_a_6 {
  164                         mux {
  165                                 groups = "pwm_ao_a_6";
  166                                 function = "pwm_ao_a_6";
  167                                 bias-disable;
  168                         };
  169                 };
  170 
  171                 pwm_ao_a_12_pins: pwm_ao_a_12 {
  172                         mux {
  173                                 groups = "pwm_ao_a_12";
  174                                 function = "pwm_ao_a_12";
  175                                 bias-disable;
  176                         };
  177                 };
  178 
  179                 pwm_ao_b_pins: pwm_ao_b {
  180                         mux {
  181                                 groups = "pwm_ao_b";
  182                                 function = "pwm_ao_b";
  183                                 bias-disable;
  184                         };
  185                 };
  186 
  187                 i2s_am_clk_pins: i2s_am_clk {
  188                         mux {
  189                                 groups = "i2s_am_clk";
  190                                 function = "i2s_out_ao";
  191                                 bias-disable;
  192                         };
  193                 };
  194 
  195                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
  196                         mux {
  197                                 groups = "i2s_out_ao_clk";
  198                                 function = "i2s_out_ao";
  199                                 bias-disable;
  200                         };
  201                 };
  202 
  203                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
  204                         mux {
  205                                 groups = "i2s_out_lr_clk";
  206                                 function = "i2s_out_ao";
  207                                 bias-disable;
  208                         };
  209                 };
  210 
  211                 i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
  212                         mux {
  213                                 groups = "i2s_out_ch01_ao";
  214                                 function = "i2s_out_ao";
  215                                 bias-disable;
  216                         };
  217                 };
  218 
  219                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
  220                         mux {
  221                                 groups = "i2s_out_ch23_ao";
  222                                 function = "i2s_out_ao";
  223                                 bias-disable;
  224                         };
  225                 };
  226 
  227                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
  228                         mux {
  229                                 groups = "i2s_out_ch45_ao";
  230                                 function = "i2s_out_ao";
  231                                 bias-disable;
  232                         };
  233                 };
  234 
  235                 spdif_out_ao_6_pins: spdif_out_ao_6 {
  236                         mux {
  237                                 groups = "spdif_out_ao_6";
  238                                 function = "spdif_out_ao";
  239                         };
  240                 };
  241 
  242                 spdif_out_ao_13_pins: spdif_out_ao_13 {
  243                         mux {
  244                                 groups = "spdif_out_ao_13";
  245                                 function = "spdif_out_ao";
  246                                 bias-disable;
  247                         };
  248                 };
  249 
  250                 ao_cec_pins: ao_cec {
  251                         mux {
  252                                 groups = "ao_cec";
  253                                 function = "cec_ao";
  254                                 bias-disable;
  255                         };
  256                 };
  257 
  258                 ee_cec_pins: ee_cec {
  259                         mux {
  260                                 groups = "ee_cec";
  261                                 function = "cec_ao";
  262                                 bias-disable;
  263                         };
  264                 };
  265         };
  266 };
  267 
  268 &cbus {
  269         spifc: spi@8c80 {
  270                 compatible = "amlogic,meson-gxbb-spifc";
  271                 reg = <0x0 0x08c80 0x0 0x80>;
  272                 #address-cells = <1>;
  273                 #size-cells = <0>;
  274                 clocks = <&clkc CLKID_SPI>;
  275                 status = "disabled";
  276         };
  277 };
  278 
  279 &cec_AO {
  280         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
  281         clock-names = "core";
  282 };
  283 
  284 &clkc_AO {
  285         compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
  286         clocks = <&xtal>, <&clkc CLKID_CLK81>;
  287         clock-names = "xtal", "mpeg-clk";
  288 };
  289 
  290 &efuse {
  291         clocks = <&clkc CLKID_EFUSE>;
  292 };
  293 
  294 &ethmac {
  295         clocks = <&clkc CLKID_ETH>,
  296                  <&clkc CLKID_FCLK_DIV2>,
  297                  <&clkc CLKID_MPLL2>,
  298                  <&clkc CLKID_FCLK_DIV2>;
  299         clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
  300 };
  301 
  302 &gpio_intc {
  303         compatible = "amlogic,meson-gpio-intc",
  304                      "amlogic,meson-gxbb-gpio-intc";
  305         status = "okay";
  306 };
  307 
  308 &hdmi_tx {
  309         compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
  310         resets = <&reset RESET_HDMITX_CAPB3>,
  311                  <&reset RESET_HDMI_SYSTEM_RESET>,
  312                  <&reset RESET_HDMI_TX>;
  313         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
  314         clocks = <&clkc CLKID_HDMI_PCLK>,
  315                  <&clkc CLKID_CLK81>,
  316                  <&clkc CLKID_GCLK_VENCI_INT0>;
  317         clock-names = "isfr", "iahb", "venci";
  318 };
  319 
  320 &sysctrl {
  321         clkc: clock-controller {
  322                 compatible = "amlogic,gxbb-clkc";
  323                 #clock-cells = <1>;
  324                 clocks = <&xtal>;
  325                 clock-names = "xtal";
  326         };
  327 };
  328 
  329 &hwrng {
  330         clocks = <&clkc CLKID_RNG0>;
  331         clock-names = "core";
  332 };
  333 
  334 &i2c_A {
  335         clocks = <&clkc CLKID_I2C>;
  336 };
  337 
  338 &i2c_AO {
  339         clocks = <&clkc CLKID_AO_I2C>;
  340 };
  341 
  342 &i2c_B {
  343         clocks = <&clkc CLKID_I2C>;
  344 };
  345 
  346 &i2c_C {
  347         clocks = <&clkc CLKID_I2C>;
  348 };
  349 
  350 &mali {
  351         compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
  352 
  353         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
  354         clock-names = "bus", "core";
  355 
  356         assigned-clocks = <&clkc CLKID_GP0_PLL>;
  357         assigned-clock-rates = <744000000>;
  358 };
  359 
  360 &periphs {
  361         pinctrl_periphs: pinctrl@4b0 {
  362                 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
  363                 #address-cells = <2>;
  364                 #size-cells = <2>;
  365                 ranges;
  366 
  367                 gpio: bank@4b0 {
  368                         reg = <0x0 0x004b0 0x0 0x28>,
  369                               <0x0 0x004e8 0x0 0x14>,
  370                               <0x0 0x00520 0x0 0x14>,
  371                               <0x0 0x00430 0x0 0x40>;
  372                         reg-names = "mux", "pull", "pull-enable", "gpio";
  373                         gpio-controller;
  374                         #gpio-cells = <2>;
  375                         gpio-ranges = <&pinctrl_periphs 0 0 119>;
  376                 };
  377 
  378                 emmc_pins: emmc {
  379                         mux-0 {
  380                                 groups = "emmc_nand_d07",
  381                                        "emmc_cmd";
  382                                 function = "emmc";
  383                                 bias-pull-up;
  384                         };
  385 
  386                         mux-1 {
  387                                 groups = "emmc_clk";
  388                                 function = "emmc";
  389                                 bias-disable;
  390                         };
  391                 };
  392 
  393                 emmc_ds_pins: emmc-ds {
  394                         mux {
  395                                 groups = "emmc_ds";
  396                                 function = "emmc";
  397                                 bias-pull-down;
  398                         };
  399                 };
  400 
  401                 emmc_clk_gate_pins: emmc_clk_gate {
  402                         mux {
  403                                 groups = "BOOT_8";
  404                                 function = "gpio_periphs";
  405                                 bias-pull-down;
  406                         };
  407                 };
  408 
  409                 nor_pins: nor {
  410                         mux {
  411                                 groups = "nor_d",
  412                                        "nor_q",
  413                                        "nor_c",
  414                                        "nor_cs";
  415                                 function = "nor";
  416                                 bias-disable;
  417                         };
  418                 };
  419 
  420                 spi_pins: spi-pins {
  421                         mux {
  422                                 groups = "spi_miso",
  423                                         "spi_mosi",
  424                                         "spi_sclk";
  425                                 function = "spi";
  426                                 bias-disable;
  427                         };
  428                 };
  429 
  430                 spi_ss0_pins: spi-ss0 {
  431                         mux {
  432                                 groups = "spi_ss0";
  433                                 function = "spi";
  434                                 bias-disable;
  435                         };
  436                 };
  437 
  438                 sdcard_pins: sdcard {
  439                         mux-0 {
  440                                 groups = "sdcard_d0",
  441                                        "sdcard_d1",
  442                                        "sdcard_d2",
  443                                        "sdcard_d3",
  444                                        "sdcard_cmd";
  445                                 function = "sdcard";
  446                                 bias-pull-up;
  447                         };
  448 
  449                         mux-1 {
  450                                 groups = "sdcard_clk";
  451                                 function = "sdcard";
  452                                 bias-disable;
  453                         };
  454                 };
  455 
  456                 sdcard_clk_gate_pins: sdcard_clk_gate {
  457                         mux {
  458                                 groups = "CARD_2";
  459                                 function = "gpio_periphs";
  460                                 bias-pull-down;
  461                         };
  462                 };
  463 
  464                 sdio_pins: sdio {
  465                         mux-0 {
  466                                 groups = "sdio_d0",
  467                                        "sdio_d1",
  468                                        "sdio_d2",
  469                                        "sdio_d3",
  470                                        "sdio_cmd";
  471                                 function = "sdio";
  472                                 bias-pull-up;
  473                         };
  474 
  475                         mux-1 {
  476                                 groups = "sdio_clk";
  477                                 function = "sdio";
  478                                 bias-disable;
  479                         };
  480                 };
  481 
  482                 sdio_clk_gate_pins: sdio_clk_gate {
  483                         mux {
  484                                 groups = "GPIOX_4";
  485                                 function = "gpio_periphs";
  486                                 bias-pull-down;
  487                         };
  488                 };
  489 
  490                 sdio_irq_pins: sdio_irq {
  491                         mux {
  492                                 groups = "sdio_irq";
  493                                 function = "sdio";
  494                                 bias-disable;
  495                         };
  496                 };
  497 
  498                 uart_a_pins: uart_a {
  499                         mux {
  500                                 groups = "uart_tx_a",
  501                                        "uart_rx_a";
  502                                 function = "uart_a";
  503                                 bias-disable;
  504                         };
  505                 };
  506 
  507                 uart_a_cts_rts_pins: uart_a_cts_rts {
  508                         mux {
  509                                 groups = "uart_cts_a",
  510                                        "uart_rts_a";
  511                                 function = "uart_a";
  512                                 bias-disable;
  513                         };
  514                 };
  515 
  516                 uart_b_pins: uart_b {
  517                         mux {
  518                                 groups = "uart_tx_b",
  519                                        "uart_rx_b";
  520                                 function = "uart_b";
  521                                 bias-disable;
  522                         };
  523                 };
  524 
  525                 uart_b_cts_rts_pins: uart_b_cts_rts {
  526                         mux {
  527                                 groups = "uart_cts_b",
  528                                        "uart_rts_b";
  529                                 function = "uart_b";
  530                                 bias-disable;
  531                         };
  532                 };
  533 
  534                 uart_c_pins: uart_c {
  535                         mux {
  536                                 groups = "uart_tx_c",
  537                                        "uart_rx_c";
  538                                 function = "uart_c";
  539                                 bias-disable;
  540                         };
  541                 };
  542 
  543                 uart_c_cts_rts_pins: uart_c_cts_rts {
  544                         mux {
  545                                 groups = "uart_cts_c",
  546                                        "uart_rts_c";
  547                                 function = "uart_c";
  548                                 bias-disable;
  549                         };
  550                 };
  551 
  552                 i2c_a_pins: i2c_a {
  553                         mux {
  554                                 groups = "i2c_sck_a",
  555                                        "i2c_sda_a";
  556                                 function = "i2c_a";
  557                                 bias-disable;
  558                         };
  559                 };
  560 
  561                 i2c_b_pins: i2c_b {
  562                         mux {
  563                                 groups = "i2c_sck_b",
  564                                        "i2c_sda_b";
  565                                 function = "i2c_b";
  566                                 bias-disable;
  567                         };
  568                 };
  569 
  570                 i2c_c_pins: i2c_c {
  571                         mux {
  572                                 groups = "i2c_sck_c",
  573                                        "i2c_sda_c";
  574                                 function = "i2c_c";
  575                                 bias-disable;
  576                         };
  577                 };
  578 
  579                 eth_rgmii_pins: eth-rgmii {
  580                         mux {
  581                                 groups = "eth_mdio",
  582                                        "eth_mdc",
  583                                        "eth_clk_rx_clk",
  584                                        "eth_rx_dv",
  585                                        "eth_rxd0",
  586                                        "eth_rxd1",
  587                                        "eth_rxd2",
  588                                        "eth_rxd3",
  589                                        "eth_rgmii_tx_clk",
  590                                        "eth_tx_en",
  591                                        "eth_txd0",
  592                                        "eth_txd1",
  593                                        "eth_txd2",
  594                                        "eth_txd3";
  595                                 function = "eth";
  596                                 bias-disable;
  597                         };
  598                 };
  599 
  600                 eth_rmii_pins: eth-rmii {
  601                         mux {
  602                                 groups = "eth_mdio",
  603                                        "eth_mdc",
  604                                        "eth_clk_rx_clk",
  605                                        "eth_rx_dv",
  606                                        "eth_rxd0",
  607                                        "eth_rxd1",
  608                                        "eth_tx_en",
  609                                        "eth_txd0",
  610                                        "eth_txd1";
  611                                 function = "eth";
  612                                 bias-disable;
  613                         };
  614                 };
  615 
  616                 pwm_a_x_pins: pwm_a_x {
  617                         mux {
  618                                 groups = "pwm_a_x";
  619                                 function = "pwm_a_x";
  620                                 bias-disable;
  621                         };
  622                 };
  623 
  624                 pwm_a_y_pins: pwm_a_y {
  625                         mux {
  626                                 groups = "pwm_a_y";
  627                                 function = "pwm_a_y";
  628                                 bias-disable;
  629                         };
  630                 };
  631 
  632                 pwm_b_pins: pwm_b {
  633                         mux {
  634                                 groups = "pwm_b";
  635                                 function = "pwm_b";
  636                                 bias-disable;
  637                         };
  638                 };
  639 
  640                 pwm_d_pins: pwm_d {
  641                         mux {
  642                                 groups = "pwm_d";
  643                                 function = "pwm_d";
  644                                 bias-disable;
  645                         };
  646                 };
  647 
  648                 pwm_e_pins: pwm_e {
  649                         mux {
  650                                 groups = "pwm_e";
  651                                 function = "pwm_e";
  652                                 bias-disable;
  653                         };
  654                 };
  655 
  656                 pwm_f_x_pins: pwm_f_x {
  657                         mux {
  658                                 groups = "pwm_f_x";
  659                                 function = "pwm_f_x";
  660                                 bias-disable;
  661                         };
  662                 };
  663 
  664                 pwm_f_y_pins: pwm_f_y {
  665                         mux {
  666                                 groups = "pwm_f_y";
  667                                 function = "pwm_f_y";
  668                                 bias-disable;
  669                         };
  670                 };
  671 
  672                 hdmi_hpd_pins: hdmi_hpd {
  673                         mux {
  674                                 groups = "hdmi_hpd";
  675                                 function = "hdmi_hpd";
  676                                 bias-disable;
  677                         };
  678                 };
  679 
  680                 hdmi_i2c_pins: hdmi_i2c {
  681                         mux {
  682                                 groups = "hdmi_sda", "hdmi_scl";
  683                                 function = "hdmi_i2c";
  684                                 bias-disable;
  685                         };
  686                 };
  687 
  688                 i2sout_ch23_y_pins: i2sout_ch23_y {
  689                         mux {
  690                                 groups = "i2sout_ch23_y";
  691                                 function = "i2s_out";
  692                                 bias-disable;
  693                         };
  694                 };
  695 
  696                 i2sout_ch45_y_pins: i2sout_ch45_y {
  697                         mux {
  698                                 groups = "i2sout_ch45_y";
  699                                 function = "i2s_out";
  700                                 bias-disable;
  701                         };
  702                 };
  703 
  704                 i2sout_ch67_y_pins: i2sout_ch67_y {
  705                         mux {
  706                                 groups = "i2sout_ch67_y";
  707                                 function = "i2s_out";
  708                                 bias-disable;
  709                         };
  710                 };
  711 
  712                 spdif_out_y_pins: spdif_out_y {
  713                         mux {
  714                                 groups = "spdif_out_y";
  715                                 function = "spdif_out";
  716                                 bias-disable;
  717                         };
  718                 };
  719         };
  720 };
  721 
  722 &pwrc {
  723         resets = <&reset RESET_VIU>,
  724                  <&reset RESET_VENC>,
  725                  <&reset RESET_VCBUS>,
  726                  <&reset RESET_BT656>,
  727                  <&reset RESET_DVIN_RESET>,
  728                  <&reset RESET_RDMA>,
  729                  <&reset RESET_VENCI>,
  730                  <&reset RESET_VENCP>,
  731                  <&reset RESET_VDAC>,
  732                  <&reset RESET_VDI6>,
  733                  <&reset RESET_VENCL>,
  734                  <&reset RESET_VID_LOCK>;
  735         reset-names = "viu", "venc", "vcbus", "bt656",
  736                       "dvin", "rdma", "venci", "vencp",
  737                       "vdac", "vdi6", "vencl", "vid_lock";
  738         clocks = <&clkc CLKID_VPU>,
  739                  <&clkc CLKID_VAPB>;
  740         clock-names = "vpu", "vapb";
  741         /*
  742          * VPU clocking is provided by two identical clock paths
  743          * VPU_0 and VPU_1 muxed to a single clock by a glitch
  744          * free mux to safely change frequency while running.
  745          * Same for VAPB but with a final gate after the glitch free mux.
  746          */
  747         assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
  748                           <&clkc CLKID_VPU_0>,
  749                           <&clkc CLKID_VPU>, /* Glitch free mux */
  750                           <&clkc CLKID_VAPB_0_SEL>,
  751                           <&clkc CLKID_VAPB_0>,
  752                           <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
  753         assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
  754                                  <0>, /* Do Nothing */
  755                                  <&clkc CLKID_VPU_0>,
  756                                  <&clkc CLKID_FCLK_DIV4>,
  757                                  <0>, /* Do Nothing */
  758                                  <&clkc CLKID_VAPB_0>;
  759         assigned-clock-rates = <0>, /* Do Nothing */
  760                                <666666666>,
  761                                <0>, /* Do Nothing */
  762                                <0>, /* Do Nothing */
  763                                <250000000>,
  764                                <0>; /* Do Nothing */
  765 };
  766 
  767 &saradc {
  768         compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
  769         clocks = <&xtal>,
  770                  <&clkc CLKID_SAR_ADC>,
  771                  <&clkc CLKID_SAR_ADC_CLK>,
  772                  <&clkc CLKID_SAR_ADC_SEL>;
  773         clock-names = "clkin", "core", "adc_clk", "adc_sel";
  774 };
  775 
  776 &sd_emmc_a {
  777         clocks = <&clkc CLKID_SD_EMMC_A>,
  778                  <&clkc CLKID_SD_EMMC_A_CLK0>,
  779                  <&clkc CLKID_FCLK_DIV2>;
  780         clock-names = "core", "clkin0", "clkin1";
  781         resets = <&reset RESET_SD_EMMC_A>;
  782 };
  783 
  784 &sd_emmc_b {
  785         clocks = <&clkc CLKID_SD_EMMC_B>,
  786                  <&clkc CLKID_SD_EMMC_B_CLK0>,
  787                  <&clkc CLKID_FCLK_DIV2>;
  788         clock-names = "core", "clkin0", "clkin1";
  789         resets = <&reset RESET_SD_EMMC_B>;
  790 };
  791 
  792 &sd_emmc_c {
  793         clocks = <&clkc CLKID_SD_EMMC_C>,
  794                  <&clkc CLKID_SD_EMMC_C_CLK0>,
  795                  <&clkc CLKID_FCLK_DIV2>;
  796         clock-names = "core", "clkin0", "clkin1";
  797         resets = <&reset RESET_SD_EMMC_C>;
  798 };
  799 
  800 &simplefb_hdmi {
  801         clocks = <&clkc CLKID_HDMI_PCLK>,
  802                  <&clkc CLKID_CLK81>,
  803                  <&clkc CLKID_GCLK_VENCI_INT0>;
  804 };
  805 
  806 &spicc {
  807         clocks = <&clkc CLKID_SPICC>;
  808         clock-names = "core";
  809         resets = <&reset RESET_PERIPHS_SPICC>;
  810         num-cs = <1>;
  811 };
  812 
  813 &spifc {
  814         clocks = <&clkc CLKID_SPI>;
  815 };
  816 
  817 &uart_A {
  818         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
  819         clock-names = "xtal", "pclk", "baud";
  820 };
  821 
  822 &uart_AO {
  823         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
  824         clock-names = "xtal", "pclk", "baud";
  825 };
  826 
  827 &uart_AO_B {
  828         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
  829         clock-names = "xtal", "pclk", "baud";
  830 };
  831 
  832 &uart_B {
  833         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
  834         clock-names = "xtal", "pclk", "baud";
  835 };
  836 
  837 &uart_C {
  838         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
  839         clock-names = "xtal", "pclk", "baud";
  840 };
  841 
  842 &vpu {
  843         compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
  844         power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
  845 };
  846 
  847 &vdec {
  848         compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec";
  849         clocks = <&clkc CLKID_DOS_PARSER>,
  850                  <&clkc CLKID_DOS>,
  851                  <&clkc CLKID_VDEC_1>,
  852                  <&clkc CLKID_VDEC_HEVC>;
  853         clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
  854         resets = <&reset RESET_PARSER>;
  855         reset-names = "esparser";
  856 };
Cache object: f9cc0ffacba46586c589b8ec96ea51d6
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/amlogic/meson-gxbb.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/amlogic/meson-gxbb.dtsi
