meson-gxl.dtsi

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    1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
    2 /*
    3  * Copyright (c) 2016 Endless Computers, Inc.
    4  * Author: Carlo Caione <carlo@endlessm.com>
    5  */
    6 
    7 #include "meson-gx.dtsi"
    8 #include <dt-bindings/clock/gxbb-clkc.h>
    9 #include <dt-bindings/clock/gxbb-aoclkc.h>
   10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
   11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
   12 
   13 / {
   14         compatible = "amlogic,meson-gxl";
   15 
   16         soc {
   17                 usb: usb@d0078080 {
   18                         compatible = "amlogic,meson-gxl-usb-ctrl";
   19                         reg = <0x0 0xd0078080 0x0 0x20>;
   20                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
   21                         #address-cells = <2>;
   22                         #size-cells = <2>;
   23                         ranges;
   24 
   25                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
   26                         clock-names = "usb_ctrl", "ddr";
   27                         resets = <&reset RESET_USB_OTG>;
   28 
   29                         dr_mode = "otg";
   30 
   31                         phys = <&usb2_phy0>, <&usb2_phy1>;
   32                         phy-names = "usb2-phy0", "usb2-phy1";
   33 
   34                         dwc2: usb@c9100000 {
   35                                 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
   36                                 reg = <0x0 0xc9100000 0x0 0x40000>;
   37                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
   38                                 clocks = <&clkc CLKID_USB1>;
   39                                 clock-names = "otg";
   40                                 phys = <&usb2_phy1>;
   41                                 dr_mode = "peripheral";
   42                                 g-rx-fifo-size = <192>;
   43                                 g-np-tx-fifo-size = <128>;
   44                                 g-tx-fifo-size = <128 128 16 16 16>;
   45                         };
   46 
   47                         dwc3: usb@c9000000 {
   48                                 compatible = "snps,dwc3";
   49                                 reg = <0x0 0xc9000000 0x0 0x100000>;
   50                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
   51                                 dr_mode = "host";
   52                                 maximum-speed = "high-speed";
   53                                 snps,dis_u2_susphy_quirk;
   54                         };
   55                 };
   56 
   57                 acodec: audio-controller@c8832000 {
   58                         compatible = "amlogic,t9015";
   59                         reg = <0x0 0xc8832000 0x0 0x14>;
   60                         #sound-dai-cells = <0>;
   61                         sound-name-prefix = "ACODEC";
   62                         clocks = <&clkc CLKID_ACODEC>;
   63                         clock-names = "pclk";
   64                         resets = <&reset RESET_ACODEC>;
   65                         status = "disabled";
   66                 };
   67 
   68                 crypto: crypto@c883e000 {
   69                         compatible = "amlogic,gxl-crypto";
   70                         reg = <0x0 0xc883e000 0x0 0x36>;
   71                         interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
   72                                      <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
   73                         clocks = <&clkc CLKID_BLKMV>;
   74                         clock-names = "blkmv";
   75                         status = "okay";
   76                 };
   77         };
   78 };
   79 
   80 &aiu {
   81         compatible = "amlogic,aiu-gxl", "amlogic,aiu";
   82         clocks = <&clkc CLKID_AIU_GLUE>,
   83                  <&clkc CLKID_I2S_OUT>,
   84                  <&clkc CLKID_AOCLK_GATE>,
   85                  <&clkc CLKID_CTS_AMCLK>,
   86                  <&clkc CLKID_MIXER_IFACE>,
   87                  <&clkc CLKID_IEC958>,
   88                  <&clkc CLKID_IEC958_GATE>,
   89                  <&clkc CLKID_CTS_MCLK_I958>,
   90                  <&clkc CLKID_CTS_I958>;
   91         clock-names = "pclk",
   92                       "i2s_pclk",
   93                       "i2s_aoclk",
   94                       "i2s_mclk",
   95                       "i2s_mixer",
   96                       "spdif_pclk",
   97                       "spdif_aoclk",
   98                       "spdif_mclk",
   99                       "spdif_mclk_sel";
  100         resets = <&reset RESET_AIU>;
  101 };
  102 
  103 &apb {
  104         usb2_phy0: phy@78000 {
  105                 compatible = "amlogic,meson-gxl-usb2-phy";
  106                 #phy-cells = <0>;
  107                 reg = <0x0 0x78000 0x0 0x20>;
  108                 clocks = <&clkc CLKID_USB>;
  109                 clock-names = "phy";
  110                 resets = <&reset RESET_USB_OTG>;
  111                 reset-names = "phy";
  112                 status = "okay";
  113         };
  114 
  115         usb2_phy1: phy@78020 {
  116                 compatible = "amlogic,meson-gxl-usb2-phy";
  117                 #phy-cells = <0>;
  118                 reg = <0x0 0x78020 0x0 0x20>;
  119                 clocks = <&clkc CLKID_USB>;
  120                 clock-names = "phy";
  121                 resets = <&reset RESET_USB_OTG>;
  122                 reset-names = "phy";
  123                 status = "okay";
  124         };
  125 };
  126 
  127 &efuse {
  128         clocks = <&clkc CLKID_EFUSE>;
  129 };
  130 
  131 &ethmac {
  132         clocks = <&clkc CLKID_ETH>,
  133                  <&clkc CLKID_FCLK_DIV2>,
  134                  <&clkc CLKID_MPLL2>,
  135                  <&clkc CLKID_FCLK_DIV2>;
  136         clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
  137 
  138         mdio0: mdio {
  139                 #address-cells = <1>;
  140                 #size-cells = <0>;
  141                 compatible = "snps,dwmac-mdio";
  142         };
  143 };
  144 
  145 &aobus {
  146         pinctrl_aobus: pinctrl@14 {
  147                 compatible = "amlogic,meson-gxl-aobus-pinctrl";
  148                 #address-cells = <2>;
  149                 #size-cells = <2>;
  150                 ranges;
  151 
  152                 gpio_ao: bank@14 {
  153                         reg = <0x0 0x00014 0x0 0x8>,
  154                               <0x0 0x0002c 0x0 0x4>,
  155                               <0x0 0x00024 0x0 0x8>;
  156                         reg-names = "mux", "pull", "gpio";
  157                         gpio-controller;
  158                         #gpio-cells = <2>;
  159                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
  160                 };
  161 
  162                 uart_ao_a_pins: uart_ao_a {
  163                         mux {
  164                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
  165                                 function = "uart_ao";
  166                                 bias-disable;
  167                         };
  168                 };
  169 
  170                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
  171                         mux {
  172                                 groups = "uart_cts_ao_a",
  173                                        "uart_rts_ao_a";
  174                                 function = "uart_ao";
  175                                 bias-disable;
  176                         };
  177                 };
  178 
  179                 uart_ao_b_pins: uart_ao_b {
  180                         mux {
  181                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
  182                                 function = "uart_ao_b";
  183                                 bias-disable;
  184                         };
  185                 };
  186 
  187                 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
  188                         mux {
  189                                 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
  190                                 function = "uart_ao_b";
  191                                 bias-disable;
  192                         };
  193                 };
  194 
  195                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
  196                         mux {
  197                                 groups = "uart_cts_ao_b",
  198                                        "uart_rts_ao_b";
  199                                 function = "uart_ao_b";
  200                                 bias-disable;
  201                         };
  202                 };
  203 
  204                 remote_input_ao_pins: remote_input_ao {
  205                         mux {
  206                                 groups = "remote_input_ao";
  207                                 function = "remote_input_ao";
  208                                 bias-disable;
  209                         };
  210                 };
  211 
  212                 i2c_ao_pins: i2c_ao {
  213                         mux {
  214                                 groups = "i2c_sck_ao",
  215                                        "i2c_sda_ao";
  216                                 function = "i2c_ao";
  217                                 bias-disable;
  218                         };
  219                 };
  220 
  221                 pwm_ao_a_3_pins: pwm_ao_a_3 {
  222                         mux {
  223                                 groups = "pwm_ao_a_3";
  224                                 function = "pwm_ao_a";
  225                                 bias-disable;
  226                         };
  227                 };
  228 
  229                 pwm_ao_a_8_pins: pwm_ao_a_8 {
  230                         mux {
  231                                 groups = "pwm_ao_a_8";
  232                                 function = "pwm_ao_a";
  233                                 bias-disable;
  234                         };
  235                 };
  236 
  237                 pwm_ao_b_pins: pwm_ao_b {
  238                         mux {
  239                                 groups = "pwm_ao_b";
  240                                 function = "pwm_ao_b";
  241                                 bias-disable;
  242                         };
  243                 };
  244 
  245                 pwm_ao_b_6_pins: pwm_ao_b_6 {
  246                         mux {
  247                                 groups = "pwm_ao_b_6";
  248                                 function = "pwm_ao_b";
  249                                 bias-disable;
  250                         };
  251                 };
  252 
  253                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
  254                         mux {
  255                                 groups = "i2s_out_ch23_ao";
  256                                 function = "i2s_out_ao";
  257                                 bias-disable;
  258                         };
  259                 };
  260 
  261                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
  262                         mux {
  263                                 groups = "i2s_out_ch45_ao";
  264                                 function = "i2s_out_ao";
  265                                 bias-disable;
  266                         };
  267                 };
  268 
  269                 spdif_out_ao_6_pins: spdif_out_ao_6 {
  270                         mux {
  271                                 groups = "spdif_out_ao_6";
  272                                 function = "spdif_out_ao";
  273                                 bias-disable;
  274                         };
  275                 };
  276 
  277                 spdif_out_ao_9_pins: spdif_out_ao_9 {
  278                         mux {
  279                                 groups = "spdif_out_ao_9";
  280                                 function = "spdif_out_ao";
  281                                 bias-disable;
  282                         };
  283                 };
  284 
  285                 ao_cec_pins: ao_cec {
  286                         mux {
  287                                 groups = "ao_cec";
  288                                 function = "cec_ao";
  289                                 bias-disable;
  290                         };
  291                 };
  292 
  293                 ee_cec_pins: ee_cec {
  294                         mux {
  295                                 groups = "ee_cec";
  296                                 function = "cec_ao";
  297                                 bias-disable;
  298                         };
  299                 };
  300         };
  301 };
  302 
  303 &cec_AO {
  304         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
  305         clock-names = "core";
  306 };
  307 
  308 &clkc_AO {
  309         compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
  310         clocks = <&xtal>, <&clkc CLKID_CLK81>;
  311         clock-names = "xtal", "mpeg-clk";
  312 };
  313 
  314 &gpio_intc {
  315         compatible = "amlogic,meson-gpio-intc",
  316                      "amlogic,meson-gxl-gpio-intc";
  317         status = "okay";
  318 };
  319 
  320 &hdmi_tx {
  321         compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
  322         resets = <&reset RESET_HDMITX_CAPB3>,
  323                  <&reset RESET_HDMI_SYSTEM_RESET>,
  324                  <&reset RESET_HDMI_TX>;
  325         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
  326         clocks = <&clkc CLKID_HDMI_PCLK>,
  327                  <&clkc CLKID_CLK81>,
  328                  <&clkc CLKID_GCLK_VENCI_INT0>;
  329         clock-names = "isfr", "iahb", "venci";
  330 };
  331 
  332 &sysctrl {
  333         clkc: clock-controller {
  334                 compatible = "amlogic,gxl-clkc";
  335                 #clock-cells = <1>;
  336                 clocks = <&xtal>;
  337                 clock-names = "xtal";
  338         };
  339 };
  340 
  341 &hwrng {
  342         clocks = <&clkc CLKID_RNG0>;
  343         clock-names = "core";
  344 };
  345 
  346 &i2c_A {
  347         clocks = <&clkc CLKID_I2C>;
  348 };
  349 
  350 &i2c_AO {
  351         clocks = <&clkc CLKID_AO_I2C>;
  352 };
  353 
  354 &i2c_B {
  355         clocks = <&clkc CLKID_I2C>;
  356 };
  357 
  358 &i2c_C {
  359         clocks = <&clkc CLKID_I2C>;
  360 };
  361 
  362 &periphs {
  363         pinctrl_periphs: pinctrl@4b0 {
  364                 compatible = "amlogic,meson-gxl-periphs-pinctrl";
  365                 #address-cells = <2>;
  366                 #size-cells = <2>;
  367                 ranges;
  368 
  369                 gpio: bank@4b0 {
  370                         reg = <0x0 0x004b0 0x0 0x28>,
  371                               <0x0 0x004e8 0x0 0x14>,
  372                               <0x0 0x00520 0x0 0x14>,
  373                               <0x0 0x00430 0x0 0x40>;
  374                         reg-names = "mux", "pull", "pull-enable", "gpio";
  375                         gpio-controller;
  376                         #gpio-cells = <2>;
  377                         gpio-ranges = <&pinctrl_periphs 0 0 100>;
  378                 };
  379 
  380                 emmc_pins: emmc {
  381                         mux-0 {
  382                                 groups = "emmc_nand_d07",
  383                                        "emmc_cmd";
  384                                 function = "emmc";
  385                                 bias-pull-up;
  386                         };
  387 
  388                         mux-1 {
  389                                 groups = "emmc_clk";
  390                                 function = "emmc";
  391                                 bias-disable;
  392                         };
  393                 };
  394 
  395                 emmc_ds_pins: emmc-ds {
  396                         mux {
  397                                 groups = "emmc_ds";
  398                                 function = "emmc";
  399                                 bias-pull-down;
  400                         };
  401                 };
  402 
  403                 emmc_clk_gate_pins: emmc_clk_gate {
  404                         mux {
  405                                 groups = "BOOT_8";
  406                                 function = "gpio_periphs";
  407                                 bias-pull-down;
  408                         };
  409                 };
  410 
  411                 nor_pins: nor {
  412                         mux {
  413                                 groups = "nor_d",
  414                                        "nor_q",
  415                                        "nor_c",
  416                                        "nor_cs";
  417                                 function = "nor";
  418                                 bias-disable;
  419                         };
  420                 };
  421 
  422                 spi_pins: spi-pins {
  423                         mux {
  424                                 groups = "spi_miso",
  425                                         "spi_mosi",
  426                                         "spi_sclk";
  427                                 function = "spi";
  428                                 bias-disable;
  429                         };
  430                 };
  431 
  432                 spi_ss0_pins: spi-ss0 {
  433                         mux {
  434                                 groups = "spi_ss0";
  435                                 function = "spi";
  436                                 bias-disable;
  437                         };
  438                 };
  439 
  440                 sdcard_pins: sdcard {
  441                         mux-0 {
  442                                 groups = "sdcard_d0",
  443                                        "sdcard_d1",
  444                                        "sdcard_d2",
  445                                        "sdcard_d3",
  446                                        "sdcard_cmd";
  447                                 function = "sdcard";
  448                                 bias-pull-up;
  449                         };
  450 
  451                         mux-1 {
  452                                 groups = "sdcard_clk";
  453                                 function = "sdcard";
  454                                 bias-disable;
  455                         };
  456                 };
  457 
  458                 sdcard_clk_gate_pins: sdcard_clk_gate {
  459                         mux {
  460                                 groups = "CARD_2";
  461                                 function = "gpio_periphs";
  462                                 bias-pull-down;
  463                         };
  464                 };
  465 
  466                 sdio_pins: sdio {
  467                         mux-0 {
  468                                 groups = "sdio_d0",
  469                                        "sdio_d1",
  470                                        "sdio_d2",
  471                                        "sdio_d3",
  472                                        "sdio_cmd";
  473                                 function = "sdio";
  474                                 bias-pull-up;
  475                         };
  476 
  477                         mux-1 {
  478                                 groups = "sdio_clk";
  479                                 function = "sdio";
  480                                 bias-disable;
  481                         };
  482                 };
  483 
  484                 sdio_clk_gate_pins: sdio_clk_gate {
  485                         mux {
  486                                 groups = "GPIOX_4";
  487                                 function = "gpio_periphs";
  488                                 bias-pull-down;
  489                         };
  490                 };
  491 
  492                 sdio_irq_pins: sdio_irq {
  493                         mux {
  494                                 groups = "sdio_irq";
  495                                 function = "sdio";
  496                                 bias-disable;
  497                         };
  498                 };
  499 
  500                 uart_a_pins: uart_a {
  501                         mux {
  502                                 groups = "uart_tx_a",
  503                                        "uart_rx_a";
  504                                 function = "uart_a";
  505                                 bias-disable;
  506                         };
  507                 };
  508 
  509                 uart_a_cts_rts_pins: uart_a_cts_rts {
  510                         mux {
  511                                 groups = "uart_cts_a",
  512                                        "uart_rts_a";
  513                                 function = "uart_a";
  514                                 bias-disable;
  515                         };
  516                 };
  517 
  518                 uart_b_pins: uart_b {
  519                         mux {
  520                                 groups = "uart_tx_b",
  521                                        "uart_rx_b";
  522                                 function = "uart_b";
  523                                 bias-disable;
  524                         };
  525                 };
  526 
  527                 uart_b_cts_rts_pins: uart_b_cts_rts {
  528                         mux {
  529                                 groups = "uart_cts_b",
  530                                        "uart_rts_b";
  531                                 function = "uart_b";
  532                                 bias-disable;
  533                         };
  534                 };
  535 
  536                 uart_c_pins: uart_c {
  537                         mux {
  538                                 groups = "uart_tx_c",
  539                                        "uart_rx_c";
  540                                 function = "uart_c";
  541                                 bias-disable;
  542                         };
  543                 };
  544 
  545                 uart_c_cts_rts_pins: uart_c_cts_rts {
  546                         mux {
  547                                 groups = "uart_cts_c",
  548                                        "uart_rts_c";
  549                                 function = "uart_c";
  550                                 bias-disable;
  551                         };
  552                 };
  553 
  554                 i2c_a_pins: i2c_a {
  555                         mux {
  556                                 groups = "i2c_sck_a",
  557                                      "i2c_sda_a";
  558                                 function = "i2c_a";
  559                                 bias-disable;
  560                         };
  561                 };
  562 
  563                 i2c_b_pins: i2c_b {
  564                         mux {
  565                                 groups = "i2c_sck_b",
  566                                       "i2c_sda_b";
  567                                 function = "i2c_b";
  568                                 bias-disable;
  569                         };
  570                 };
  571 
  572                 i2c_c_pins: i2c_c {
  573                         mux {
  574                                 groups = "i2c_sck_c",
  575                                       "i2c_sda_c";
  576                                 function = "i2c_c";
  577                                 bias-disable;
  578                         };
  579                 };
  580 
  581                 i2c_c_dv18_pins: i2c_c_dv18 {
  582                         mux {
  583                                 groups = "i2c_sck_c_dv19",
  584                                       "i2c_sda_c_dv18";
  585                                 function = "i2c_c";
  586                                 bias-disable;
  587                         };
  588                 };
  589 
  590                 eth_pins: eth_c {
  591                         mux {
  592                                 groups = "eth_mdio",
  593                                        "eth_mdc",
  594                                        "eth_clk_rx_clk",
  595                                        "eth_rx_dv",
  596                                        "eth_rxd0",
  597                                        "eth_rxd1",
  598                                        "eth_rxd2",
  599                                        "eth_rxd3",
  600                                        "eth_rgmii_tx_clk",
  601                                        "eth_tx_en",
  602                                        "eth_txd0",
  603                                        "eth_txd1",
  604                                        "eth_txd2",
  605                                        "eth_txd3";
  606                                 function = "eth";
  607                                 bias-disable;
  608                         };
  609                 };
  610 
  611                 eth_link_led_pins: eth_link_led {
  612                         mux {
  613                                 groups = "eth_link_led";
  614                                 function = "eth_led";
  615                                 bias-disable;
  616                         };
  617                 };
  618 
  619                 eth_act_led_pins: eth_act_led {
  620                         mux {
  621                                 groups = "eth_act_led";
  622                                 function = "eth_led";
  623                         };
  624                 };
  625                 
  626                 pwm_a_pins: pwm_a {
  627                         mux {
  628                                 groups = "pwm_a";
  629                                 function = "pwm_a";
  630                                 bias-disable;
  631                         };
  632                 };
  633 
  634                 pwm_b_pins: pwm_b {
  635                         mux {
  636                                 groups = "pwm_b";
  637                                 function = "pwm_b";
  638                                 bias-disable;
  639                         };
  640                 };
  641 
  642                 pwm_c_pins: pwm_c {
  643                         mux {
  644                                 groups = "pwm_c";
  645                                 function = "pwm_c";
  646                                 bias-disable;
  647                         };
  648                 };
  649 
  650                 pwm_d_pins: pwm_d {
  651                         mux {
  652                                 groups = "pwm_d";
  653                                 function = "pwm_d";
  654                                 bias-disable;
  655                         };
  656                 };
  657 
  658                 pwm_e_pins: pwm_e {
  659                         mux {
  660                                 groups = "pwm_e";
  661                                 function = "pwm_e";
  662                                 bias-disable;
  663                         };
  664                 };
  665 
  666                 pwm_f_clk_pins: pwm_f_clk {
  667                         mux {
  668                                 groups = "pwm_f_clk";
  669                                 function = "pwm_f";
  670                                 bias-disable;
  671                         };
  672                 };
  673 
  674                 pwm_f_x_pins: pwm_f_x {
  675                         mux {
  676                                 groups = "pwm_f_x";
  677                                 function = "pwm_f";
  678                                 bias-disable;
  679                         };
  680                 };
  681 
  682                 hdmi_hpd_pins: hdmi_hpd {
  683                         mux {
  684                                 groups = "hdmi_hpd";
  685                                 function = "hdmi_hpd";
  686                                 bias-disable;
  687                         };
  688                 };
  689 
  690                 hdmi_i2c_pins: hdmi_i2c {
  691                         mux {
  692                                 groups = "hdmi_sda", "hdmi_scl";
  693                                 function = "hdmi_i2c";
  694                                 bias-disable;
  695                         };
  696                 };
  697 
  698                 i2s_am_clk_pins: i2s_am_clk {
  699                         mux {
  700                                 groups = "i2s_am_clk";
  701                                 function = "i2s_out";
  702                                 bias-disable;
  703                         };
  704                 };
  705 
  706                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
  707                         mux {
  708                                 groups = "i2s_out_ao_clk";
  709                                 function = "i2s_out";
  710                                 bias-disable;
  711                         };
  712                 };
  713 
  714                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
  715                         mux {
  716                                 groups = "i2s_out_lr_clk";
  717                                 function = "i2s_out";
  718                                 bias-disable;
  719                         };
  720                 };
  721 
  722                 i2s_out_ch01_pins: i2s_out_ch01 {
  723                         mux {
  724                                 groups = "i2s_out_ch01";
  725                                 function = "i2s_out";
  726                                 bias-disable;
  727                         };
  728                 };
  729                 i2sout_ch23_z_pins: i2sout_ch23_z {
  730                         mux {
  731                                 groups = "i2sout_ch23_z";
  732                                 function = "i2s_out";
  733                                 bias-disable;
  734                         };
  735                 };
  736 
  737                 i2sout_ch45_z_pins: i2sout_ch45_z {
  738                         mux {
  739                                 groups = "i2sout_ch45_z";
  740                                 function = "i2s_out";
  741                                 bias-disable;
  742                         };
  743                 };
  744 
  745                 i2sout_ch67_z_pins: i2sout_ch67_z {
  746                         mux {
  747                                 groups = "i2sout_ch67_z";
  748                                 function = "i2s_out";
  749                                 bias-disable;
  750                         };
  751                 };
  752 
  753                 spdif_out_h_pins: spdif_out_ao_h {
  754                         mux {
  755                                 groups = "spdif_out_h";
  756                                 function = "spdif_out";
  757                                 bias-disable;
  758                         };
  759                 };
  760         };
  761 
  762         eth-phy-mux {
  763                 compatible = "mdio-mux-mmioreg", "mdio-mux";
  764                 #address-cells = <1>;
  765                 #size-cells = <0>;
  766                 reg = <0x0 0x55c 0x0 0x4>;
  767                 mux-mask = <0xffffffff>;
  768                 mdio-parent-bus = <&mdio0>;
  769 
  770                 internal_mdio: mdio@e40908ff {
  771                         reg = <0xe40908ff>;
  772                         #address-cells = <1>;
  773                         #size-cells = <0>;
  774 
  775                         internal_phy: ethernet-phy@8 {
  776                                 compatible = "ethernet-phy-id0181.4400";
  777                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  778                                 reg = <8>;
  779                                 max-speed = <100>;
  780                         };
  781                 };
  782 
  783                 external_mdio: mdio@2009087f {
  784                         reg = <0x2009087f>;
  785                         #address-cells = <1>;
  786                         #size-cells = <0>;
  787                 };
  788         };
  789 };
  790 
  791 &pwrc {
  792         resets = <&reset RESET_VIU>,
  793                  <&reset RESET_VENC>,
  794                  <&reset RESET_VCBUS>,
  795                  <&reset RESET_BT656>,
  796                  <&reset RESET_DVIN_RESET>,
  797                  <&reset RESET_RDMA>,
  798                  <&reset RESET_VENCI>,
  799                  <&reset RESET_VENCP>,
  800                  <&reset RESET_VDAC>,
  801                  <&reset RESET_VDI6>,
  802                  <&reset RESET_VENCL>,
  803                  <&reset RESET_VID_LOCK>;
  804         reset-names = "viu", "venc", "vcbus", "bt656",
  805                       "dvin", "rdma", "venci", "vencp",
  806                       "vdac", "vdi6", "vencl", "vid_lock";
  807         clocks = <&clkc CLKID_VPU>,
  808                  <&clkc CLKID_VAPB>;
  809         clock-names = "vpu", "vapb";
  810         /*
  811          * VPU clocking is provided by two identical clock paths
  812          * VPU_0 and VPU_1 muxed to a single clock by a glitch
  813          * free mux to safely change frequency while running.
  814          * Same for VAPB but with a final gate after the glitch free mux.
  815          */
  816         assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
  817                           <&clkc CLKID_VPU_0>,
  818                           <&clkc CLKID_VPU>, /* Glitch free mux */
  819                           <&clkc CLKID_VAPB_0_SEL>,
  820                           <&clkc CLKID_VAPB_0>,
  821                           <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
  822         assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
  823                                  <0>, /* Do Nothing */
  824                                  <&clkc CLKID_VPU_0>,
  825                                  <&clkc CLKID_FCLK_DIV4>,
  826                                  <0>, /* Do Nothing */
  827                                  <&clkc CLKID_VAPB_0>;
  828         assigned-clock-rates = <0>, /* Do Nothing */
  829                                <666666666>,
  830                                <0>, /* Do Nothing */
  831                                <0>, /* Do Nothing */
  832                                <250000000>,
  833                                <0>; /* Do Nothing */
  834 };
  835 
  836 &saradc {
  837         compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
  838         clocks = <&xtal>,
  839                  <&clkc CLKID_SAR_ADC>,
  840                  <&clkc CLKID_SAR_ADC_CLK>,
  841                  <&clkc CLKID_SAR_ADC_SEL>;
  842         clock-names = "clkin", "core", "adc_clk", "adc_sel";
  843 };
  844 
  845 &sd_emmc_a {
  846         clocks = <&clkc CLKID_SD_EMMC_A>,
  847                  <&clkc CLKID_SD_EMMC_A_CLK0>,
  848                  <&clkc CLKID_FCLK_DIV2>;
  849         clock-names = "core", "clkin0", "clkin1";
  850         resets = <&reset RESET_SD_EMMC_A>;
  851 };
  852 
  853 &sd_emmc_b {
  854         clocks = <&clkc CLKID_SD_EMMC_B>,
  855                  <&clkc CLKID_SD_EMMC_B_CLK0>,
  856                  <&clkc CLKID_FCLK_DIV2>;
  857         clock-names = "core", "clkin0", "clkin1";
  858         resets = <&reset RESET_SD_EMMC_B>;
  859 };
  860 
  861 &sd_emmc_c {
  862         clocks = <&clkc CLKID_SD_EMMC_C>,
  863                  <&clkc CLKID_SD_EMMC_C_CLK0>,
  864                  <&clkc CLKID_FCLK_DIV2>;
  865         clock-names = "core", "clkin0", "clkin1";
  866         resets = <&reset RESET_SD_EMMC_C>;
  867 };
  868 
  869 &simplefb_hdmi {
  870         clocks = <&clkc CLKID_HDMI_PCLK>,
  871                  <&clkc CLKID_CLK81>,
  872                  <&clkc CLKID_GCLK_VENCI_INT0>;
  873 };
  874 
  875 &spicc {
  876         clocks = <&clkc CLKID_SPICC>;
  877         clock-names = "core";
  878         resets = <&reset RESET_PERIPHS_SPICC>;
  879         num-cs = <1>;
  880 };
  881 
  882 &spifc {
  883         clocks = <&clkc CLKID_SPI>;
  884 };
  885 
  886 &uart_A {
  887         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
  888         clock-names = "xtal", "pclk", "baud";
  889 };
  890 
  891 &uart_AO {
  892         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
  893         clock-names = "xtal", "pclk", "baud";
  894 };
  895 
  896 &uart_AO_B {
  897         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
  898         clock-names = "xtal", "pclk", "baud";
  899 };
  900 
  901 &uart_B {
  902         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
  903         clock-names = "xtal", "pclk", "baud";
  904 };
  905 
  906 &uart_C {
  907         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
  908         clock-names = "xtal", "pclk", "baud";
  909 };
  910 
  911 &vpu {
  912         compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
  913         power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
  914 };
  915 
  916 &vdec {
  917         compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
  918         clocks = <&clkc CLKID_DOS_PARSER>,
  919                  <&clkc CLKID_DOS>,
  920                  <&clkc CLKID_VDEC_1>,
  921                  <&clkc CLKID_VDEC_HEVC>;
  922         clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
  923         resets = <&reset RESET_PARSER>;
  924         reset-names = "esparser";
  925 };
Cache object: fb368bd20dd2beae560e59ed2efb98f9
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/amlogic/meson-gxl.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/amlogic/meson-gxl.dtsi
