Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/arm/juno-r1.dts
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1 /* 2 * ARM Ltd. Juno Platform 3 * 4 * Copyright (c) 2015 ARM Ltd. 5 * 6 * This file is licensed under a dual GPLv2 or BSD license. 7 */ 8 9 /dts-v1/; 10 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/arm/coresight-cti-dt.h> 13 #include "juno-base.dtsi" 14 #include "juno-cs-r1r2.dtsi" 15 16 / { 17 model = "ARM Juno development board (r1)"; 18 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 serial0 = &soc_uart0; 25 }; 26 27 chosen { 28 stdout-path = "serial0:115200n8"; 29 }; 30 31 psci { 32 compatible = "arm,psci-0.2"; 33 method = "smc"; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 cpu-map { 41 cluster0 { 42 core0 { 43 cpu = <&A57_0>; 44 }; 45 core1 { 46 cpu = <&A57_1>; 47 }; 48 }; 49 50 cluster1 { 51 core0 { 52 cpu = <&A53_0>; 53 }; 54 core1 { 55 cpu = <&A53_1>; 56 }; 57 core2 { 58 cpu = <&A53_2>; 59 }; 60 core3 { 61 cpu = <&A53_3>; 62 }; 63 }; 64 }; 65 66 idle-states { 67 entry-method = "psci"; 68 69 CPU_SLEEP_0: cpu-sleep-0 { 70 compatible = "arm,idle-state"; 71 arm,psci-suspend-param = <0x0010000>; 72 local-timer-stop; 73 entry-latency-us = <300>; 74 exit-latency-us = <1200>; 75 min-residency-us = <2000>; 76 }; 77 78 CLUSTER_SLEEP_0: cluster-sleep-0 { 79 compatible = "arm,idle-state"; 80 arm,psci-suspend-param = <0x1010000>; 81 local-timer-stop; 82 entry-latency-us = <400>; 83 exit-latency-us = <1200>; 84 min-residency-us = <2500>; 85 }; 86 }; 87 88 A57_0: cpu@0 { 89 compatible = "arm,cortex-a57"; 90 reg = <0x0 0x0>; 91 device_type = "cpu"; 92 enable-method = "psci"; 93 i-cache-size = <0xc000>; 94 i-cache-line-size = <64>; 95 i-cache-sets = <256>; 96 d-cache-size = <0x8000>; 97 d-cache-line-size = <64>; 98 d-cache-sets = <256>; 99 next-level-cache = <&A57_L2>; 100 clocks = <&scpi_dvfs 0>; 101 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 102 capacity-dmips-mhz = <1024>; 103 }; 104 105 A57_1: cpu@1 { 106 compatible = "arm,cortex-a57"; 107 reg = <0x0 0x1>; 108 device_type = "cpu"; 109 enable-method = "psci"; 110 i-cache-size = <0xc000>; 111 i-cache-line-size = <64>; 112 i-cache-sets = <256>; 113 d-cache-size = <0x8000>; 114 d-cache-line-size = <64>; 115 d-cache-sets = <256>; 116 next-level-cache = <&A57_L2>; 117 clocks = <&scpi_dvfs 0>; 118 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 119 capacity-dmips-mhz = <1024>; 120 }; 121 122 A53_0: cpu@100 { 123 compatible = "arm,cortex-a53"; 124 reg = <0x0 0x100>; 125 device_type = "cpu"; 126 enable-method = "psci"; 127 i-cache-size = <0x8000>; 128 i-cache-line-size = <64>; 129 i-cache-sets = <256>; 130 d-cache-size = <0x8000>; 131 d-cache-line-size = <64>; 132 d-cache-sets = <128>; 133 next-level-cache = <&A53_L2>; 134 clocks = <&scpi_dvfs 1>; 135 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 136 capacity-dmips-mhz = <578>; 137 }; 138 139 A53_1: cpu@101 { 140 compatible = "arm,cortex-a53"; 141 reg = <0x0 0x101>; 142 device_type = "cpu"; 143 enable-method = "psci"; 144 i-cache-size = <0x8000>; 145 i-cache-line-size = <64>; 146 i-cache-sets = <256>; 147 d-cache-size = <0x8000>; 148 d-cache-line-size = <64>; 149 d-cache-sets = <128>; 150 next-level-cache = <&A53_L2>; 151 clocks = <&scpi_dvfs 1>; 152 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 153 capacity-dmips-mhz = <578>; 154 }; 155 156 A53_2: cpu@102 { 157 compatible = "arm,cortex-a53"; 158 reg = <0x0 0x102>; 159 device_type = "cpu"; 160 enable-method = "psci"; 161 i-cache-size = <0x8000>; 162 i-cache-line-size = <64>; 163 i-cache-sets = <256>; 164 d-cache-size = <0x8000>; 165 d-cache-line-size = <64>; 166 d-cache-sets = <128>; 167 next-level-cache = <&A53_L2>; 168 clocks = <&scpi_dvfs 1>; 169 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 170 capacity-dmips-mhz = <578>; 171 }; 172 173 A53_3: cpu@103 { 174 compatible = "arm,cortex-a53"; 175 reg = <0x0 0x103>; 176 device_type = "cpu"; 177 enable-method = "psci"; 178 i-cache-size = <0x8000>; 179 i-cache-line-size = <64>; 180 i-cache-sets = <256>; 181 d-cache-size = <0x8000>; 182 d-cache-line-size = <64>; 183 d-cache-sets = <128>; 184 next-level-cache = <&A53_L2>; 185 clocks = <&scpi_dvfs 1>; 186 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 187 capacity-dmips-mhz = <578>; 188 }; 189 190 A57_L2: l2-cache0 { 191 compatible = "cache"; 192 cache-size = <0x200000>; 193 cache-line-size = <64>; 194 cache-sets = <2048>; 195 cache-level = <2>; 196 }; 197 198 A53_L2: l2-cache1 { 199 compatible = "cache"; 200 cache-size = <0x100000>; 201 cache-line-size = <64>; 202 cache-sets = <1024>; 203 cache-level = <2>; 204 }; 205 }; 206 207 pmu-a57 { 208 compatible = "arm,cortex-a57-pmu"; 209 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>; 211 interrupt-affinity = <&A57_0>, 212 <&A57_1>; 213 }; 214 215 pmu-a53 { 216 compatible = "arm,cortex-a53-pmu"; 217 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 221 interrupt-affinity = <&A53_0>, 222 <&A53_1>, 223 <&A53_2>, 224 <&A53_3>; 225 }; 226 }; 227 228 &memtimer { 229 status = "okay"; 230 }; 231 232 &pcie_ctlr { 233 status = "okay"; 234 }; 235 236 &smmu_pcie { 237 status = "okay"; 238 }; 239 240 &etm0 { 241 cpu = <&A57_0>; 242 }; 243 244 &etm1 { 245 cpu = <&A57_1>; 246 }; 247 248 &etm2 { 249 cpu = <&A53_0>; 250 }; 251 252 &etm3 { 253 cpu = <&A53_1>; 254 }; 255 256 &etm4 { 257 cpu = <&A53_2>; 258 }; 259 260 &etm5 { 261 cpu = <&A53_3>; 262 }; 263 264 &big_cluster_thermal_zone { 265 status = "okay"; 266 }; 267 268 &little_cluster_thermal_zone { 269 status = "okay"; 270 }; 271 272 &gpu0_thermal_zone { 273 status = "okay"; 274 }; 275 276 &gpu1_thermal_zone { 277 status = "okay"; 278 }; 279 280 &etf0_out_port { 281 remote-endpoint = <&csys2_funnel_in_port0>; 282 }; 283 284 &replicator_in_port0 { 285 remote-endpoint = <&csys2_funnel_out_port>; 286 }; 287 288 &csys1_funnel_in_port0 { 289 remote-endpoint = <&stm_out_port>; 290 }; 291 292 &stm_out_port { 293 remote-endpoint = <&csys1_funnel_in_port0>; 294 }; 295 296 &cpu_debug0 { 297 cpu = <&A57_0>; 298 }; 299 300 &cpu_debug1 { 301 cpu = <&A57_1>; 302 }; 303 304 &cpu_debug2 { 305 cpu = <&A53_0>; 306 }; 307 308 &cpu_debug3 { 309 cpu = <&A53_1>; 310 }; 311 312 &cpu_debug4 { 313 cpu = <&A53_2>; 314 }; 315 316 &cpu_debug5 { 317 cpu = <&A53_3>; 318 }; 319 320 &cti0 { 321 cpu = <&A57_0>; 322 }; 323 324 &cti1 { 325 cpu = <&A57_1>; 326 }; 327 328 &cti2 { 329 cpu = <&A53_0>; 330 }; 331 332 &cti3 { 333 cpu = <&A53_1>; 334 }; 335 336 &cti4 { 337 cpu = <&A53_2>; 338 }; 339 340 &cti5 { 341 cpu = <&A53_3>; 342 };
Cache object: 80fb257fc52f67d836f0ad4ce2b42be3
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