vexpress-v2f-1xv7-ca53x2.dts

Version: - FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10

    1 // SPDX-License-Identifier: GPL-2.0
    2 /*
    3  * ARM Ltd. Versatile Express
    4  *
    5  * LogicTile Express 20MG
    6  * V2F-1XV7
    7  *
    8  * Cortex-A53 (2 cores) Soft Macrocell Model
    9  *
   10  * HBI-0247C
   11  */
   12 
   13 /dts-v1/;
   14 
   15 #include <dt-bindings/interrupt-controller/arm-gic.h>
   16 #include "vexpress-v2m-rs1.dtsi"
   17 
   18 / {
   19         model = "V2F-1XV7 Cortex-A53x2 SMM";
   20         arm,hbi = <0x247>;
   21         arm,vexpress,site = <0xf>;
   22         compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
   23         interrupt-parent = <&gic>;
   24         #address-cells = <2>;
   25         #size-cells = <2>;
   26 
   27         chosen {
   28                 stdout-path = "serial0:38400n8";
   29         };
   30 
   31         aliases {
   32                 serial0 = &v2m_serial0;
   33                 serial1 = &v2m_serial1;
   34                 serial2 = &v2m_serial2;
   35                 serial3 = &v2m_serial3;
   36                 i2c0 = &v2m_i2c_dvi;
   37                 i2c1 = &v2m_i2c_pcie;
   38         };
   39 
   40         cpus {
   41                 #address-cells = <2>;
   42                 #size-cells = <0>;
   43 
   44                 cpu@0 {
   45                         device_type = "cpu";
   46                         compatible = "arm,cortex-a53";
   47                         reg = <0 0>;
   48                         next-level-cache = <&L2_0>;
   49                 };
   50 
   51                 cpu@1 {
   52                         device_type = "cpu";
   53                         compatible = "arm,cortex-a53";
   54                         reg = <0 1>;
   55                         next-level-cache = <&L2_0>;
   56                 };
   57 
   58                 L2_0: l2-cache0 {
   59                         compatible = "cache";
   60                 };
   61         };
   62 
   63         memory@80000000 {
   64                 device_type = "memory";
   65                 reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
   66         };
   67 
   68         reserved-memory {
   69                 #address-cells = <2>;
   70                 #size-cells = <2>;
   71                 ranges;
   72 
   73                 /* Chipselect 2 is physically at 0x18000000 */
   74                 vram: vram@18000000 {
   75                         /* 8 MB of designated video RAM */
   76                         compatible = "shared-dma-pool";
   77                         reg = <0 0x18000000 0 0x00800000>;
   78                         no-map;
   79                 };
   80         };
   81 
   82         gic: interrupt-controller@2c001000 {
   83                 compatible = "arm,gic-400";
   84                 #interrupt-cells = <3>;
   85                 #address-cells = <0>;
   86                 interrupt-controller;
   87                 reg = <0 0x2c001000 0 0x1000>,
   88                       <0 0x2c002000 0 0x2000>,
   89                       <0 0x2c004000 0 0x2000>,
   90                       <0 0x2c006000 0 0x2000>;
   91                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
   92         };
   93 
   94         timer {
   95                 compatible = "arm,armv8-timer";
   96                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
   97                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
   98                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
   99                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  100         };
  101 
  102         pmu {
  103                 compatible = "arm,armv8-pmuv3";
  104                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
  105                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  106         };
  107 
  108         dcc {
  109                 compatible = "arm,vexpress,config-bus";
  110                 arm,vexpress,config-bridge = <&v2m_sysreg>;
  111 
  112                 smbclk: smclk {
  113                         /* SMC clock */
  114                         compatible = "arm,vexpress-osc";
  115                         arm,vexpress-sysreg,func = <1 4>;
  116                         freq-range = <40000000 40000000>;
  117                         #clock-cells = <0>;
  118                         clock-output-names = "smclk";
  119                 };
  120 
  121                 volt-vio {
  122                         /* VIO to expansion board above */
  123                         compatible = "arm,vexpress-volt";
  124                         arm,vexpress-sysreg,func = <2 0>;
  125                         regulator-name = "VIO_UP";
  126                         regulator-min-microvolt = <800000>;
  127                         regulator-max-microvolt = <1800000>;
  128                         regulator-always-on;
  129                 };
  130 
  131                 volt-12v {
  132                         /* 12V from power connector J6 */
  133                         compatible = "arm,vexpress-volt";
  134                         arm,vexpress-sysreg,func = <2 1>;
  135                         regulator-name = "12";
  136                         regulator-always-on;
  137                 };
  138 
  139                 temp-fpga {
  140                         /* FPGA temperature */
  141                         compatible = "arm,vexpress-temp";
  142                         arm,vexpress-sysreg,func = <4 0>;
  143                         label = "FPGA";
  144                 };
  145         };
  146 
  147         smb: bus@8000000 {
  148                 ranges = <0x8000000 0 0x8000000 0x18000000>;
  149         };
  150 };

Cache object: 00c285f0402c19ebdad02e34511c8ae9

[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.

FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/arm/vexpress-v2f-1xv7-ca53x2.dts