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sys/contrib/device-tree/src/arm64/broadcom/northstar2/ns2.dtsi
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1 /* 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015 Broadcom. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Broadcom Corporation nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /memreserve/ 0x81000000 0x00200000; 34 35 #include <dt-bindings/interrupt-controller/arm-gic.h> 36 #include <dt-bindings/clock/bcm-ns2.h> 37 38 / { 39 compatible = "brcm,ns2"; 40 interrupt-parent = <&gic>; 41 #address-cells = <2>; 42 #size-cells = <2>; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 A57_0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a57"; 51 reg = <0 0>; 52 enable-method = "psci"; 53 next-level-cache = <&CLUSTER0_L2>; 54 }; 55 56 A57_1: cpu@1 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a57"; 59 reg = <0 1>; 60 enable-method = "psci"; 61 next-level-cache = <&CLUSTER0_L2>; 62 }; 63 64 A57_2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a57"; 67 reg = <0 2>; 68 enable-method = "psci"; 69 next-level-cache = <&CLUSTER0_L2>; 70 }; 71 72 A57_3: cpu@3 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a57"; 75 reg = <0 3>; 76 enable-method = "psci"; 77 next-level-cache = <&CLUSTER0_L2>; 78 }; 79 80 CLUSTER0_L2: l2-cache@0 { 81 compatible = "cache"; 82 }; 83 }; 84 85 psci { 86 compatible = "arm,psci-1.0"; 87 method = "smc"; 88 }; 89 90 timer { 91 compatible = "arm,armv8-timer"; 92 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | 93 IRQ_TYPE_LEVEL_LOW)>, 94 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | 95 IRQ_TYPE_LEVEL_LOW)>, 96 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | 97 IRQ_TYPE_LEVEL_LOW)>, 98 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | 99 IRQ_TYPE_LEVEL_LOW)>; 100 }; 101 102 pmu { 103 compatible = "arm,armv8-pmuv3"; 104 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-affinity = <&A57_0>, 109 <&A57_1>, 110 <&A57_2>, 111 <&A57_3>; 112 }; 113 114 pcie0: pcie@20020000 { 115 compatible = "brcm,iproc-pcie"; 116 reg = <0 0x20020000 0 0x1000>; 117 dma-coherent; 118 119 #interrupt-cells = <1>; 120 interrupt-map-mask = <0 0 0 0>; 121 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; 122 123 linux,pci-domain = <0>; 124 125 bus-range = <0x00 0xff>; 126 127 #address-cells = <3>; 128 #size-cells = <2>; 129 device_type = "pci"; 130 ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>; 131 132 brcm,pcie-ob; 133 brcm,pcie-ob-oarr-size; 134 brcm,pcie-ob-axi-offset = <0x00000000>; 135 brcm,pcie-ob-window-size = <256>; 136 137 status = "disabled"; 138 139 phys = <&pci_phy0>; 140 phy-names = "pcie-phy"; 141 142 msi-parent = <&v2m0>; 143 }; 144 145 pcie4: pcie@50020000 { 146 compatible = "brcm,iproc-pcie"; 147 reg = <0 0x50020000 0 0x1000>; 148 dma-coherent; 149 150 #interrupt-cells = <1>; 151 interrupt-map-mask = <0 0 0 0>; 152 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 153 154 linux,pci-domain = <4>; 155 156 bus-range = <0x00 0xff>; 157 158 #address-cells = <3>; 159 #size-cells = <2>; 160 device_type = "pci"; 161 ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>; 162 163 brcm,pcie-ob; 164 brcm,pcie-ob-oarr-size; 165 brcm,pcie-ob-axi-offset = <0x30000000>; 166 brcm,pcie-ob-window-size = <256>; 167 168 status = "disabled"; 169 170 phys = <&pci_phy1>; 171 phy-names = "pcie-phy"; 172 173 msi-parent = <&v2m0>; 174 }; 175 176 pcie8: pcie@60c00000 { 177 compatible = "brcm,iproc-pcie-paxc"; 178 reg = <0 0x60c00000 0 0x1000>; 179 dma-coherent; 180 linux,pci-domain = <8>; 181 182 bus-range = <0x0 0x1>; 183 184 #address-cells = <3>; 185 #size-cells = <2>; 186 device_type = "pci"; 187 ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>; 188 189 status = "disabled"; 190 191 msi-parent = <&v2m0>; 192 }; 193 194 soc: soc { 195 compatible = "simple-bus"; 196 #address-cells = <1>; 197 #size-cells = <1>; 198 ranges = <0 0 0 0xffffffff>; 199 200 #include "ns2-clock.dtsi" 201 202 enet: ethernet@61000000 { 203 compatible = "brcm,ns2-amac"; 204 reg = <0x61000000 0x1000>, 205 <0x61090000 0x1000>, 206 <0x61030000 0x100>; 207 reg-names = "amac_base", "idm_base", "nicpm_base"; 208 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 209 dma-coherent; 210 phy-handle = <&gphy0>; 211 phy-mode = "rgmii"; 212 status = "disabled"; 213 }; 214 215 pdc0: iproc-pdc0@612c0000 { 216 compatible = "brcm,iproc-pdc-mbox"; 217 reg = <0x612c0000 0x445>; /* PDC FS0 regs */ 218 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 219 #mbox-cells = <1>; 220 dma-coherent; 221 brcm,rx-status-len = <32>; 222 brcm,use-bcm-hdr; 223 }; 224 225 crypto0: crypto@612d0000 { 226 compatible = "brcm,spum-crypto"; 227 reg = <0x612d0000 0x900>; 228 mboxes = <&pdc0 0>; 229 }; 230 231 pdc1: iproc-pdc1@612e0000 { 232 compatible = "brcm,iproc-pdc-mbox"; 233 reg = <0x612e0000 0x445>; /* PDC FS1 regs */ 234 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 235 #mbox-cells = <1>; 236 dma-coherent; 237 brcm,rx-status-len = <32>; 238 brcm,use-bcm-hdr; 239 }; 240 241 crypto1: crypto@612f0000 { 242 compatible = "brcm,spum-crypto"; 243 reg = <0x612f0000 0x900>; 244 mboxes = <&pdc1 0>; 245 }; 246 247 pdc2: iproc-pdc2@61300000 { 248 compatible = "brcm,iproc-pdc-mbox"; 249 reg = <0x61300000 0x445>; /* PDC FS2 regs */ 250 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 251 #mbox-cells = <1>; 252 dma-coherent; 253 brcm,rx-status-len = <32>; 254 brcm,use-bcm-hdr; 255 }; 256 257 crypto2: crypto@61310000 { 258 compatible = "brcm,spum-crypto"; 259 reg = <0x61310000 0x900>; 260 mboxes = <&pdc2 0>; 261 }; 262 263 pdc3: iproc-pdc3@61320000 { 264 compatible = "brcm,iproc-pdc-mbox"; 265 reg = <0x61320000 0x445>; /* PDC FS3 regs */ 266 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 267 #mbox-cells = <1>; 268 dma-coherent; 269 brcm,rx-status-len = <32>; 270 brcm,use-bcm-hdr; 271 }; 272 273 crypto3: crypto@61330000 { 274 compatible = "brcm,spum-crypto"; 275 reg = <0x61330000 0x900>; 276 mboxes = <&pdc3 0>; 277 }; 278 279 dma0: dma-controller@61360000 { 280 compatible = "arm,pl330", "arm,primecell"; 281 reg = <0x61360000 0x1000>; 282 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 291 #dma-cells = <1>; 292 clocks = <&iprocslow>; 293 clock-names = "apb_pclk"; 294 }; 295 296 smmu: mmu@64000000 { 297 compatible = "arm,mmu-500"; 298 reg = <0x64000000 0x40000>; 299 #global-interrupts = <2>; 300 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 334 #iommu-cells = <1>; 335 }; 336 337 pinctrl: pinctrl@6501d130 { 338 compatible = "brcm,ns2-pinmux"; 339 reg = <0x6501d130 0x08>, 340 <0x660a0028 0x04>, 341 <0x660009b0 0x40>; 342 }; 343 344 gpio_aon: gpio@65024800 { 345 compatible = "brcm,iproc-gpio"; 346 reg = <0x65024800 0x50>, 347 <0x65024008 0x18>; 348 ngpios = <6>; 349 #gpio-cells = <2>; 350 gpio-controller; 351 }; 352 353 gic: interrupt-controller@65210000 { 354 compatible = "arm,gic-400"; 355 #interrupt-cells = <3>; 356 interrupt-controller; 357 reg = <0x65210000 0x1000>, 358 <0x65220000 0x1000>, 359 <0x65240000 0x2000>, 360 <0x65260000 0x1000>; 361 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 362 IRQ_TYPE_LEVEL_HIGH)>; 363 364 #address-cells = <1>; 365 #size-cells = <1>; 366 ranges = <0 0x652e0000 0x80000>; 367 368 v2m0: v2m@0 { 369 compatible = "arm,gic-v2m-frame"; 370 interrupt-parent = <&gic>; 371 msi-controller; 372 reg = <0x00000 0x1000>; 373 arm,msi-base-spi = <72>; 374 arm,msi-num-spis = <16>; 375 }; 376 377 v2m1: v2m@10000 { 378 compatible = "arm,gic-v2m-frame"; 379 interrupt-parent = <&gic>; 380 msi-controller; 381 reg = <0x10000 0x1000>; 382 arm,msi-base-spi = <88>; 383 arm,msi-num-spis = <16>; 384 }; 385 386 v2m2: v2m@20000 { 387 compatible = "arm,gic-v2m-frame"; 388 interrupt-parent = <&gic>; 389 msi-controller; 390 reg = <0x20000 0x1000>; 391 arm,msi-base-spi = <104>; 392 arm,msi-num-spis = <16>; 393 }; 394 395 v2m3: v2m@30000 { 396 compatible = "arm,gic-v2m-frame"; 397 interrupt-parent = <&gic>; 398 msi-controller; 399 reg = <0x30000 0x1000>; 400 arm,msi-base-spi = <120>; 401 arm,msi-num-spis = <16>; 402 }; 403 404 v2m4: v2m@40000 { 405 compatible = "arm,gic-v2m-frame"; 406 interrupt-parent = <&gic>; 407 msi-controller; 408 reg = <0x40000 0x1000>; 409 arm,msi-base-spi = <136>; 410 arm,msi-num-spis = <16>; 411 }; 412 413 v2m5: v2m@50000 { 414 compatible = "arm,gic-v2m-frame"; 415 interrupt-parent = <&gic>; 416 msi-controller; 417 reg = <0x50000 0x1000>; 418 arm,msi-base-spi = <152>; 419 arm,msi-num-spis = <16>; 420 }; 421 422 v2m6: v2m@60000 { 423 compatible = "arm,gic-v2m-frame"; 424 interrupt-parent = <&gic>; 425 msi-controller; 426 reg = <0x60000 0x1000>; 427 arm,msi-base-spi = <168>; 428 arm,msi-num-spis = <16>; 429 }; 430 431 v2m7: v2m@70000 { 432 compatible = "arm,gic-v2m-frame"; 433 interrupt-parent = <&gic>; 434 msi-controller; 435 reg = <0x70000 0x1000>; 436 arm,msi-base-spi = <184>; 437 arm,msi-num-spis = <16>; 438 }; 439 }; 440 441 cci@65590000 { 442 compatible = "arm,cci-400"; 443 #address-cells = <1>; 444 #size-cells = <1>; 445 reg = <0x65590000 0x1000>; 446 ranges = <0 0x65590000 0x10000>; 447 448 pmu@9000 { 449 compatible = "arm,cci-400-pmu,r1", 450 "arm,cci-400-pmu"; 451 reg = <0x9000 0x4000>; 452 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 458 }; 459 }; 460 461 usbdrd_phy: phy@66000960 { 462 #phy-cells = <0>; 463 compatible = "brcm,ns2-drd-phy"; 464 reg = <0x66000960 0x24>, 465 <0x67012800 0x4>, 466 <0x6501d148 0x4>, 467 <0x664d0700 0x4>; 468 reg-names = "icfg", "rst-ctrl", 469 "crmu-ctrl", "usb2-strap"; 470 id-gpios = <&gpio_g 30 0>; 471 vbus-gpios = <&gpio_g 31 0>; 472 status = "disabled"; 473 }; 474 475 pwm: pwm@66010000 { 476 compatible = "brcm,iproc-pwm"; 477 reg = <0x66010000 0x28>; 478 clocks = <&osc>; 479 #pwm-cells = <3>; 480 status = "disabled"; 481 }; 482 483 mdio_mux_iproc: mdio-mux@66020000 { 484 compatible = "brcm,mdio-mux-iproc"; 485 reg = <0x66020000 0x250>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 489 mdio@0 { 490 reg = <0x0>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 494 pci_phy0: pci-phy@0 { 495 compatible = "brcm,ns2-pcie-phy"; 496 reg = <0x0>; 497 #phy-cells = <0>; 498 status = "disabled"; 499 }; 500 }; 501 502 mdio@7 { 503 reg = <0x7>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 507 pci_phy1: pci-phy@0 { 508 compatible = "brcm,ns2-pcie-phy"; 509 reg = <0x0>; 510 #phy-cells = <0>; 511 status = "disabled"; 512 }; 513 }; 514 515 mdio@10 { 516 reg = <0x10>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 }; 520 }; 521 522 timer0: timer@66030000 { 523 compatible = "arm,sp804", "arm,primecell"; 524 reg = <0x66030000 0x1000>; 525 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&iprocslow>, 527 <&iprocslow>, 528 <&iprocslow>; 529 clock-names = "timer1", "timer2", "apb_pclk"; 530 }; 531 532 timer1: timer@66040000 { 533 compatible = "arm,sp804", "arm,primecell"; 534 reg = <0x66040000 0x1000>; 535 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&iprocslow>, 537 <&iprocslow>, 538 <&iprocslow>; 539 clock-names = "timer1", "timer2", "apb_pclk"; 540 }; 541 542 timer2: timer@66050000 { 543 compatible = "arm,sp804", "arm,primecell"; 544 reg = <0x66050000 0x1000>; 545 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&iprocslow>, 547 <&iprocslow>, 548 <&iprocslow>; 549 clock-names = "timer1", "timer2", "apb_pclk"; 550 }; 551 552 timer3: timer@66060000 { 553 compatible = "arm,sp804", "arm,primecell"; 554 reg = <0x66060000 0x1000>; 555 interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&iprocslow>, 557 <&iprocslow>, 558 <&iprocslow>; 559 clock-names = "timer1", "timer2", "apb_pclk"; 560 }; 561 562 i2c0: i2c@66080000 { 563 compatible = "brcm,iproc-i2c"; 564 reg = <0x66080000 0x100>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 568 clock-frequency = <100000>; 569 status = "disabled"; 570 }; 571 572 wdt0: watchdog@66090000 { 573 compatible = "arm,sp805", "arm,primecell"; 574 reg = <0x66090000 0x1000>; 575 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&iprocslow>, <&iprocslow>; 577 clock-names = "wdog_clk", "apb_pclk"; 578 }; 579 580 gpio_g: gpio@660a0000 { 581 compatible = "brcm,iproc-gpio"; 582 reg = <0x660a0000 0x50>; 583 ngpios = <32>; 584 #gpio-cells = <2>; 585 gpio-controller; 586 interrupt-controller; 587 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 588 }; 589 590 i2c1: i2c@660b0000 { 591 compatible = "brcm,iproc-i2c"; 592 reg = <0x660b0000 0x100>; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; 596 clock-frequency = <100000>; 597 status = "disabled"; 598 }; 599 600 uart0: serial@66100000 { 601 compatible = "snps,dw-apb-uart"; 602 reg = <0x66100000 0x100>; 603 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&iprocslow>; 605 reg-shift = <2>; 606 reg-io-width = <4>; 607 status = "disabled"; 608 }; 609 610 uart1: serial@66110000 { 611 compatible = "snps,dw-apb-uart"; 612 reg = <0x66110000 0x100>; 613 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&iprocslow>; 615 reg-shift = <2>; 616 reg-io-width = <4>; 617 status = "disabled"; 618 }; 619 620 uart2: serial@66120000 { 621 compatible = "snps,dw-apb-uart"; 622 reg = <0x66120000 0x100>; 623 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&iprocslow>; 625 reg-shift = <2>; 626 reg-io-width = <4>; 627 status = "disabled"; 628 }; 629 630 uart3: serial@66130000 { 631 compatible = "snps,dw-apb-uart"; 632 reg = <0x66130000 0x100>; 633 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; 634 reg-shift = <2>; 635 reg-io-width = <4>; 636 clocks = <&osc>; 637 status = "disabled"; 638 }; 639 640 ssp0: spi@66180000 { 641 compatible = "arm,pl022", "arm,primecell"; 642 reg = <0x66180000 0x1000>; 643 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&iprocslow>, <&iprocslow>; 645 clock-names = "sspclk", "apb_pclk"; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 status = "disabled"; 649 }; 650 651 ssp1: spi@66190000 { 652 compatible = "arm,pl022", "arm,primecell"; 653 reg = <0x66190000 0x1000>; 654 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&iprocslow>, <&iprocslow>; 656 clock-names = "sspclk", "apb_pclk"; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 status = "disabled"; 660 }; 661 662 hwrng: hwrng@66220000 { 663 compatible = "brcm,iproc-rng200"; 664 reg = <0x66220000 0x28>; 665 }; 666 667 sata_phy: sata_phy@663f0100 { 668 compatible = "brcm,iproc-ns2-sata-phy"; 669 reg = <0x663f0100 0x1f00>, 670 <0x663f004c 0x10>; 671 reg-names = "phy", "phy-ctrl"; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 675 sata_phy0: sata-phy@0 { 676 reg = <0>; 677 #phy-cells = <0>; 678 status = "disabled"; 679 }; 680 681 sata_phy1: sata-phy@1 { 682 reg = <1>; 683 #phy-cells = <0>; 684 status = "disabled"; 685 }; 686 }; 687 688 sata: sata@663f2000 { 689 compatible = "brcm,iproc-ahci", "generic-ahci"; 690 reg = <0x663f2000 0x1000>; 691 dma-coherent; 692 reg-names = "ahci"; 693 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 status = "disabled"; 697 698 sata0: sata-port@0 { 699 reg = <0>; 700 phys = <&sata_phy0>; 701 phy-names = "sata-phy"; 702 }; 703 704 sata1: sata-port@1 { 705 reg = <1>; 706 phys = <&sata_phy1>; 707 phy-names = "sata-phy"; 708 }; 709 }; 710 711 sdio0: sdhci@66420000 { 712 compatible = "brcm,sdhci-iproc-cygnus"; 713 reg = <0x66420000 0x100>; 714 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 715 dma-coherent; 716 bus-width = <8>; 717 clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; 718 status = "disabled"; 719 }; 720 721 sdio1: sdhci@66430000 { 722 compatible = "brcm,sdhci-iproc-cygnus"; 723 reg = <0x66430000 0x100>; 724 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 725 dma-coherent; 726 bus-width = <8>; 727 clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; 728 status = "disabled"; 729 }; 730 731 nand: nand@66460000 { 732 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; 733 reg = <0x66460000 0x600>, 734 <0x67015408 0x600>, 735 <0x66460f00 0x20>; 736 reg-names = "nand", "iproc-idm", "iproc-ext"; 737 interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 738 739 #address-cells = <1>; 740 #size-cells = <0>; 741 742 brcm,nand-has-wp; 743 }; 744 745 qspi: spi@66470200 { 746 compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"; 747 reg = <0x66470200 0x184>, 748 <0x66470000 0x124>, 749 <0x67017408 0x004>, 750 <0x664703a0 0x01c>; 751 reg-names = "mspi", "bspi", "intr_regs", 752 "intr_status_reg"; 753 interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; 754 interrupt-names = "spi_l1_intr"; 755 clocks = <&iprocmed>; 756 clock-names = "iprocmed"; 757 num-cs = <2>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 }; 761 762 }; 763 };
Cache object: 5eb414cd7019c5ac2bb59e670099aac7
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